On 2022-05-05 17:47, Andrey Grodzovsky wrote:
>
> On 2022-05-05 15:49, Felix Kuehling wrote:
>>
>> Am 2022-05-05 um 14:57 schrieb Andrey Grodzovsky:
>>>
>>> On 2022-05-05 11:06, Christian König wrote:
Am 05.05.22 um 15:54 schrieb Andrey Grodzovsky:
>
> On 2022-05-05 09:23,
The only thing that matters is that the IP should be halted before
programming the ring buffers.
What about rephrasing the commit messages to highlight the issue a
little bit better?
On Fri, May 6, 2022 at 12:33 AM Alex Deucher wrote:
>
> On Sat, Apr 30, 2022 at 3:34 AM wrote:
> >
> > From:
On 2022-05-05 16:04, Alex Deucher wrote:
> From: Likun Gao
>
> Support memory power gating control for LSDMA.
>
> Signed-off-by: Likun Gao
> Reviewed-by: Hawking Zhang
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 1 +
>
On 2022-05-05 16:04, Alex Deucher wrote:
> From: Likun Gao
>
> Support constant data filling in PIO mode for LSDMA.
>
> Signed-off-by: Likun Gao
> Reviewed-by: Christian König
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 40 +++
>
On 2022-05-05 16:04, Alex Deucher wrote:
> From: Likun Gao
>
> Support memory to memory linear copy in PIO mode for LSDMA.
>
> Signed-off-by: Likun Gao
> Reviewed-by: Christian König
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 26 ++
>
Hello,
While trying to program the HD 7350 Cedar GPU to run with DPM
under the 157MHz/200MHz sclk/mclk powerstate, for single_display,
and with forced LOW performance on the SMC, the DMA ring seems
to hang.
After the desired power state is programmed, the DMA and CP rings
0xcafedead tests are
On 04/22, Harry Wentland wrote:
>
>
> On 2022-04-22 10:28, Melissa Wen wrote:
> > On 04/21, Harry Wentland wrote:
> > >
> > >
> > > On 2022-04-21 15:20, Melissa Wen wrote:
> > > > On 04/21, Harry Wentland wrote:
> > > > >
> > > > >
> > > > > On 2022-04-21 10:37, Melissa Wen wrote:
> > > > >
On 2022-05-05 15:49, Felix Kuehling wrote:
Am 2022-05-05 um 14:57 schrieb Andrey Grodzovsky:
On 2022-05-05 11:06, Christian König wrote:
Am 05.05.22 um 15:54 schrieb Andrey Grodzovsky:
On 2022-05-05 09:23, Christian König wrote:
Am 05.05.22 um 15:15 schrieb Andrey Grodzovsky:
On
@apop...@nvidia.com Could you please check this patch? It's somehow related to
migrate_device_page() for long term device coherent pages.
Regards,
Alex Sierra
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Sierra
> Sent: Thursday, May 5, 2022 4:34 PM
> To: j...@nvidia.com
>
The objective is to test device migration mechanism in pages marked
as COW, for private and coherent device type. In case of writing to
COW private page(s), a page fault will migrate pages back to system
memory first. Then, these pages will be duplicated. In case of COW
device coherent type, pages
The intention is to test hmm device coherent type under different get
user pages paths. Also, test gup with FOLL_LONGTERM flag set in
device coherent pages. These pages should get migrated back to system
memory.
Signed-off-by: Alex Sierra
---
tools/testing/selftests/vm/hmm-tests.c | 104
With DEVICE_COHERENT, we'll soon have vm_normal_pages() return
device-managed anonymous pages that are not LRU pages. Although they
behave like normal pages for purposes of mapping in CPU page, and for
COW. They do not support LRU lists, NUMA migration or THP.
We also introduced a FOLL_LRU flag
In order to configure device coherent in test_hmm, two module parameters
should be passed, which correspond to the SP start address of each
device (2) spm_addr_dev0 & spm_addr_dev1. If no parameters are passed,
private device type is configured.
Signed-off-by: Alex Sierra
Acked-by: Felix
Add two more parameters to set spm_addr_dev0 & spm_addr_dev1
addresses. These two parameters configure the start SP
addresses for each device in test_hmm driver.
Consequently, this configures zone device type as coherent.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
Reviewed-by: Alistair
Coherent device type memory on VRAM to RAM migration, has similar access
as System RAM from the CPU. This flag sets the source from the sender.
Which in Coherent type case, should be set as
MIGRATE_VMA_SELECT_DEVICE_COHERENT.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
Signed-off-by:
Device Coherent type uses device memory that is coherently accesible by
the CPU. This could be shown as SP (special purpose) memory range
at the BIOS-e820 memory enumeration. If no SP memory is supported in
system, this could be faked by setting CONFIG_EFI_FAKE_MEMMAP.
Currently, test_hmm only
Test cases such as migrate_fault and migrate_multiple, were modified to
explicit migrate from device to sys memory without the need of page
faults, when using device coherent type.
Snapshot test case updated to read memory device type first and based
on that, get the proper returned results
When CPU is connected throug XGMI, it has coherent
access to VRAM resource. In this case that resource
is taken from a table in the device gmc aperture base.
This resource is used along with the device type, which could
be DEVICE_PRIVATE or DEVICE_COHERENT to create the device
page map region.
new ioctl cmd added to query zone device type. This will be
used once the test_hmm adds zone device coherent type.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
Reviewed-by: Alistair Poppple
Signed-off-by: Christoph Hellwig
---
lib/test_hmm.c | 23 +--
From: Alistair Popple
Currently any attempts to pin a device coherent page will fail. This is
because device coherent pages need to be managed by a device driver, and
pinning them would prevent a driver from migrating them off the device.
However this is no reason to fail pinning of these
During remove_migration_pte(), entries for device coherent type pages
that were not created through special migration ptes, ignore _PAGE_RW
flag. This path can be found at migrate_device_page(), where valid
vma is not required. In this case, migrate_vma_collect_pmd() is not
called and special
From: Alistair Popple
migrate_vma_setup() checks that a valid vma is passed so that the page
tables can be walked to find the pfns associated with a given address
range. However in some cases the pfns are already known, such as when
migrating device coherent pages during pin_user_pages() meaning
This case is used to migrate pages from device memory, back to system
memory. Device coherent type memory is cache coherent from device and CPU
point of view.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
Reviewed-by: Alistair Poppple
Signed-off-by: Christoph Hellwig
---
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a process can be migrated to such memory. However,
no one should be allowed to pin such memory so that it can always be
evicted.
This is our MEMORY_DEVICE_COHERENT patch series rebased and updated
for current 5.18-rc5.
Changes since the last version:
- Fixed problems with migration during long-term pinning in
get_user_pages
- Open coded vm_normal_lru_pages as suggested in previous code review
- Update hmm_gup_test with
From: Xiaojian Du
This patch will add SMU v13.0.4 into the IP discovery list.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Jack Xiao
Due to gfxoff on, cpu accessing registers is not expected.
v2: remove bug-on, fix the vmhub check
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 49 +-
1 file changed, 48
From: Kenneth Feng
temporarily disable ac/dc on smu_v13_0_7 due to the force clock issue.
Signed-off-by: Kenneth Feng
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Evan Quan
Enable SMU 13.0.0 BACO support.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 11 +++
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 75 +++
From: Graham Sider
Add amdgpu_no_queue_eviction_on_vm_fault condition to
event_interrupt_isr_v11 return. If no queue eviction on vm fault
specified, function should return false for client/source ids specifying
vm fault.
Signed-off-by: Graham Sider
Reviewed-by: Mukul Joshi
Signed-off-by: Alex
From: Evan Quan
With PMFW 78.35.0, the FCLK DPM is ready to go on SMU 13.0.0.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Graham Sider
Implement gmc_v11_0_get_vmid_pasid_mapping_info to fix
gmc_v11_0_flush_gpu_tlb_pasid logic. Change from gfx10 to use
IH_VMID_*_LUT registers for VMID -> PASID mapping.
Signed-off-by: Graham Sider
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
From: Graham Sider
WPTR_POLL_ENABLE = 1 was kept to support legacy doorbell programming in
SimNow environment. Disable for real hardware.
Signed-off-by: Graham Sider
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
1 file changed, 1
From: Kenneth Feng
enable gfxoff control interface on smu_v13_0_7
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
From: Evan Quan
There is a known "sdma busy" issue with gfxoff enabled. Let's disable
the gfxoff feature temporarily until that issue is fixed.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file
From: Evan Quan
There is some problem with average frequency reading for now. So,
we switch to the target frequency reading.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +-
1 file changed, 1
From: Evan Quan
Instead of using AverageFclkFrequencyPostDs/AverageFclkFrequencyPreDs,
we turn to target clock frequency(CurrClock[PPCLK_FCLK]).
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +-
1
From: Evan Quan
Enable SMU 13.0.0 UCLK DPM.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Evan Quan
The output from metrics table for current link status changed.
We need to update our driver accordingly.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++--
1 file changed, 3
From: Evan Quan
Enable those features supported by latest PMFW 78.34.0.
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Likun Gao
Add new sysfs interface to shows the status of psp vbflash status.
V2: rename the sysfs interface, and set more return value.
(0: not start; 1: in progress; MBX115 value when vbflash finish)
V3: warning fixes
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
From: Likun Gao
Add sysfs interface to copy VBIOS.
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
From: Andrey Grodzovsky
Add psp vbflash function for psp v13.
v2: fix warnings
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 74
From: Andrey Grodzovsky
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../include/asic_reg/mp/mp_13_0_2_offset.h| 48 +
.../include/asic_reg/mp/mp_13_0_2_sh_mask.h | 72 +++
2 files changed, 120 insertions(+)
From: Likun Gao
Add LSDMA ip block for LSDMA v6.0.2.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
From: Likun Gao
Support memory power gating control for LSDMA.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 1 +
drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c | 16 +++-
From: Likun Gao
Support memory power gating control for lsdma 6.0.2.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
From: Likun Gao
Support constant data filling in PIO mode for LSDMA.
Signed-off-by: Likun Gao
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 40 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 6 +++
From: Likun Gao
Support memory to memory linear copy in PIO mode for LSDMA.
Signed-off-by: Likun Gao
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 26 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 5 +++
Light SDMA (LSDMA) is a supplimental SDMA block on SDMA 6.x
for use by the kernel driver. Patch 1 adds large header
updates so was not sent to the list.
Hawking Zhang (1):
drm/amdgpu: add lsdma v6_0_0 ip headers
Likun Gao (7):
drm/amdgpu: add lsdma block
drm/amdgpu: support mem copy for
From: Likun Gao
Add LSDMA ip block for LSDMA v6.0.0.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
From: Likun Gao
Add Light SDMA (LSDMA) block and related function. LSDMA
is a small instance of SDMA mainly for kernel driver use.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 4 +--
Am 2022-05-05 um 14:57 schrieb Andrey Grodzovsky:
On 2022-05-05 11:06, Christian König wrote:
Am 05.05.22 um 15:54 schrieb Andrey Grodzovsky:
On 2022-05-05 09:23, Christian König wrote:
Am 05.05.22 um 15:15 schrieb Andrey Grodzovsky:
On 2022-05-05 06:09, Christian König wrote:
Am
Signed-off-by: Danijel Slivka
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 70a0aad05426..e96216ab9a39 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++
On 2022-05-05 11:06, Christian König wrote:
Am 05.05.22 um 15:54 schrieb Andrey Grodzovsky:
On 2022-05-05 09:23, Christian König wrote:
Am 05.05.22 um 15:15 schrieb Andrey Grodzovsky:
On 2022-05-05 06:09, Christian König wrote:
Am 04.05.22 um 18:18 schrieb Andrey Grodzovsky:
Problem:
On Thu, May 5, 2022 at 12:49 PM James Zhu wrote:
>
> Fixed compiling error.
>
> Signed-off-by: James Zhu
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c
Fixed compiling error.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c
b/drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c
index 08fd61622f95..f4f97f0f5c64 100644
---
On Sat, Apr 30, 2022 at 3:34 AM wrote:
>
> From: Haohui Mai
>
> The patch fully deactivates the DMA engine before setting up the ring
> buffer to avoid potential data races and crashes.
Does this actually fix an issue you are seeing? I don't think it will
hurt anything, but I also don't think
Am 05.05.22 um 15:54 schrieb Andrey Grodzovsky:
On 2022-05-05 09:23, Christian König wrote:
Am 05.05.22 um 15:15 schrieb Andrey Grodzovsky:
On 2022-05-05 06:09, Christian König wrote:
Am 04.05.22 um 18:18 schrieb Andrey Grodzovsky:
Problem:
During hive reset caused by command timing out on
Acked-by: Alex Deucher
On Thu, May 5, 2022 at 5:06 AM Christian König
wrote:
>
> It's over a decade ago that this was actually used for more than ring and
> IB tests. Just use the static register directly where needed and nuke the
> now useless infrastructure.
>
> Signed-off-by: Christian König
[why]
Currently the psr configuration parameters are hardcoded before
feeding into the DC helper before passing to DMUB FW. We'd rework
to call a shared helper to calculate/update generic psr config
fields which are relying on the stream timing and eDP sink PSR
caps to avoid hard-coding.
[how]
-
[why]
To involve the cursor position into dirty rectangle calculation.
[how]
- separate plane and cursor update by different DMUB command
- send the cursor information while cursor updating, when updating
cursor position/attribute, store cursor pos/attr to hubp, and
notify dmub FW to exit psr
[why]
Feature requires synchronization of dig, pipe, and cursor locking
between driver and DMUB fw for PSR-SU
[how]
return True if PSR-SU in the checker should_use_dmub_lock()
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 ++
1 file changed, 2
From: Leo Li
[WHY]
For additional power savings, PSR SU (also referred to as PSR2) can be
enabled on eDP panels with PSR SU support.
PSR2 saves more power compared to PSR1 by allowing more opportunities
for the display hardware to be shut down. In comparison to PSR1, Shut
down can now occur
[why]
Currently the amdgpu DM psr configuration parameters are hardcoded
before feeding into the DC helper to setup PSR. We would define a
helper which is to calculate parts of the psr config fields to
avoid hard-coding.
[how]
To make helper shareable, declare and define the helper in the
[why]
When DC driver send PSR exit dmub command to DMUB FW, it might not
wait until PSR exit. Then it may hit the following deadlock situation.
1. DC driver send HW LOCK command to DMUB FW due to frame update
2. DMUB FW Set the HW lock
3. DMUB execute PSR exit sequence and stuck at polling DPG
[why]
Some specific TCON chip has HW limitation to support PSRSU+DSC.
[how]
Force ffu mode when DSC enabled if we detect it is the specific
model from sink OUI DPCD. And disable ABM update for this case.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
[Why & How]
While support ALPM, do ALPM state transition while PSR entry/exit.
ALPM is needed for PSR-SU feature, and since the function is ready,
we'd enable it by default.
- Add psr level definition to enable/disable ALPM and set ALPM
powerdone mode.
- Enable ALPM by default
Signed-off-by:
[Why]
To support PSR2 Source DPCD configuration
[How]
Update the PSR2 Source DPCD settings while the PSR2 enabled
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 ++-
.../drm/amd/display/dc/inc/hw/link_encoder.h | 13 ++-
2 files
[why]
The current PSR SU programming margin is fixed base on FHD 60HZ
panel. If the resolution and refresh rate become higher, the time
of current margin might not cover the programming SU time.
[how]
Notice that the programming SU time is the same among different
panels.
Instead of fixing the
[Why]
The Y-granularity panel parameter indicate the grid
pattern granularity in the Y direction for PSRSU.
[How]
Send the Y-granularity data by PSR_COPY_SETTINGS dmub command.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
[Why & how]
We only support line capture indication as 0 for PSRSU
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
[why & how]
We need to implement the VSC packet rev4 that is required by PSRSU.
Follow the eDP 1.5 spec pg. 257
Signed-off-by: David Zhang
---
.../display/modules/info_packet/info_packet.c | 29 +--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git
[why & how]
Based on PSRSU specification, every selective update frame need to use
two SDP to indicate the frame active range. So we occupy another GSP1
for PSRSU execution.
Signed-off-by: David Zhang
---
.../display/dc/dcn30/dcn30_dio_stream_encoder.c | 15 +++
1 file changed, 15
[why]
PSR-SU is implemented in upstreamed dmub FW but not enabled on
DM and DC. We'd add necessary and missing definitions in dmub
cmd header to align w/ the up-to-date DMUB FW for PSR-SU support.
[how]
Add definitions and items below into dmub cmd header:
- DMUB psr version enumeration for
[why]
In PSR-SU design, the DMUB FW handles the combination of multiple
dirty rectangles.
[how]
- create DC dmub update dirty rectangle helper which sends the
dirty rectangles per pipe from DC to DMUB, and DMUB FW will
handle to combine the dirty RECTs
- call the helper from DC commit plane
[why & how]
set psr version as PSR-SU in kernel-FW interface function to ensure
the correct dmub command parameter is fed into FW.
Signed-off-by: David Zhang
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
David Zhang (16):
drm/amd/display: align dmub cmd header to latest dmub FW to support
PSR-SU
drm/amd/display: feed PSR-SU as psr version to dmub FW
drm/amd/display: combine dirty rectangles in DMUB FW
drm/amd/display: update GSP1 generic info packet for PSRSU
drm/amd/display:
On 2022-05-05 09:23, Christian König wrote:
Am 05.05.22 um 15:15 schrieb Andrey Grodzovsky:
On 2022-05-05 06:09, Christian König wrote:
Am 04.05.22 um 18:18 schrieb Andrey Grodzovsky:
Problem:
During hive reset caused by command timing out on a ring
extra resets are generated by triggered
Am 05.05.22 um 15:15 schrieb Andrey Grodzovsky:
On 2022-05-05 06:09, Christian König wrote:
Am 04.05.22 um 18:18 schrieb Andrey Grodzovsky:
Problem:
During hive reset caused by command timing out on a ring
extra resets are generated by triggered by KFD which is
unable to accesses registers on
On 2022-05-05 06:09, Christian König wrote:
Am 04.05.22 um 18:18 schrieb Andrey Grodzovsky:
Problem:
During hive reset caused by command timing out on a ring
extra resets are generated by triggered by KFD which is
unable to accesses registers on the resetting ASIC.
Fix: Rework GPU reset to
Am 04.05.22 um 18:18 schrieb Andrey Grodzovsky:
Problem:
During hive reset caused by command timing out on a ring
extra resets are generated by triggered by KFD which is
unable to accesses registers on the resetting ASIC.
Fix: Rework GPU reset to use a list of pending reset jobs
such that the
[Public]
Hi Lyude,
Thanks for raising this!
Please see my comments inline : )
> From: Zuo, Jerry
> Sent: Thursday, May 5, 2022 10:30
> To: Lyude Paul; Lin, Wayne; Wentland, Harry; amd-gfx@lists.freedesktop.org
> Subject: RE: Do we really need to
It's over a decade ago that this was actually used for more than ring and
IB tests. Just use the static register directly where needed and nuke the
now useless infrastructure.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 36 --
Am 05.05.22 um 05:19 schrieb Alex Deucher:
Some copy paste leftovers for older asics. They were protected
by __BIG_ENDIAN, so we didn't notice them initially.
Reported-by: kernel test robot
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
I'm wondering if that is are actually
Dear Paul,
Patch edited:
[why]
lru_list not empty warning in sw fini during repeated device bind unbind.
There should be a amdgpu_fence_wait_empty() before the flush_delayed_work()
call as Christian suggested.
[how]
Move to do flush_delayed_work for ttm bo delayed delete wq after
Am 05.05.22 um 04:58 schrieb Alex Deucher:
Check of the base offset for the IP exists rather than
explicitly checking for how many instances of a particular
IP there are. This is what soc15.c already does. Expand
this to nv.c and soc21.c.
Signed-off-by: Alex Deucher
I still think the
Dear Yiging,
Thank you for your patch.
Am 05.05.22 um 08:35 schrieb Yiqing Yao:
[why]
lru_list not empty warning in sw fini during repeated device bind unbind.
There should be a amdgpu_fence_wait_empty() before the flush_delayed_work()
call as sugested.
sug*g*ested
Suggested by whom? Or do
Am 05.05.22 um 08:35 schrieb Yiqing Yao:
[why]
lru_list not empty warning in sw fini during repeated device bind unbind.
There should be a amdgpu_fence_wait_empty() before the flush_delayed_work()
call as sugested.
[how]
Do flush_delayed_work for ttm bo delayed delete wq after
Am 05.05.22 um 05:20 schrieb Lang Yu:
Then other IPs can use this utility.
Oh, we intentionally move the scratch register handling from the device
code into the GFX code a few years ago.
Why is that suddenly necessary here again?
Regards,
Christian.
Signed-off-by: Lang Yu
---
[why]
lru_list not empty warning in sw fini during repeated device bind unbind.
There should be a amdgpu_fence_wait_empty() before the flush_delayed_work()
call as sugested.
[how]
Do flush_delayed_work for ttm bo delayed delete wq after fence_driver_hw_fini.
Signed-off-by: Yiqing Yao
---
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