date:20230209

RE: [PATCH] drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10

2023-02-09 Thread Quan, Evan

[AMD Official Use Only - General]



> -Original Message-
> From: amd-gfx  On Behalf Of
> Kenneth Feng
> Sent: Friday, February 10, 2023 1:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth 
> Subject: [PATCH] drm/amd/amdgpu: implement mode2 reset on
> smu_v13_0_10
> 
> implement mode2 reset on smu_v13_0_10
> 
> Signed-off-by: Kenneth Feng 
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
>  drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 303
> ++
>  drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.h |  32 ++
>  .../gpu/drm/amd/include/kgd_pp_interface.h|   1 +
>  drivers/gpu/drm/amd/pm/amdgpu_dpm.c   |  18 ++
>  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |   1 +
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  18 ++
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |   1 +
>  .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h  |   1 +
>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
>  .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  27 ++
>  12 files changed, 412 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.h
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 24d8a03091b9..a7a0e385298d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -80,7 +80,7 @@ amdgpu-y += \
>   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o
> nbio_v7_0.o vega10_reg_init.o \
>   vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o
> mxgpu_nv.o \
>   nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o
> aldebaran.o soc21.o \
> - sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o
> lsdma_v6_0.o
> + sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o
> nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
> 
>  # add DF block
>  amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> index f778466bb9db..6437ead87e5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> @@ -24,6 +24,7 @@
>  #include "amdgpu_reset.h"
>  #include "aldebaran.h"
>  #include "sienna_cichlid.h"
> +#include "smu_v13_0_10.h"
> 
>  int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
>struct amdgpu_reset_handler *handler)
> @@ -44,6 +45,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
>   case IP_VERSION(11, 0, 7):
>   ret = sienna_cichlid_reset_init(adev);
>   break;
> + case IP_VERSION(13, 0, 10):
> + ret = smu_v13_0_10_reset_init(adev);
> + break;
>   default:
>   break;
>   }
> @@ -62,6 +66,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
>   case IP_VERSION(11, 0, 7):
>   ret = sienna_cichlid_reset_fini(adev);
>   break;
> + case IP_VERSION(13, 0, 10):
> + ret = smu_v13_0_10_reset_fini(adev);
> + break;
>   default:
>   break;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
> b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
> new file mode 100644
> index ..ae29620b1ea4
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
> @@ -0,0 +1,303 @@
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "smu_v13_0_10.h"
> +#include "amdgpu_reset.h"
> +#include "amdgpu_dpm.h"
> +#include "amdgpu_job.h"
> +#include "amdgpu_ring.h"
> +#include "amdgpu_ras.h"
> +#include "amdgpu_psp.h"
> +
> +static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control
> *reset_ctl)
> +{
> +

[PATCH] drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10

2023-02-09 Thread Kenneth Feng

implement mode2 reset on smu_v13_0_10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 303 ++
 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.h |  32 ++
 .../gpu/drm/amd/include/kgd_pp_interface.h|   1 +
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c   |  18 ++
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |   1 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  18 ++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |   1 +
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h  |   1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  27 ++
 12 files changed, 412 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 24d8a03091b9..a7a0e385298d 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -80,7 +80,7 @@ amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o 
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o 
mxgpu_nv.o \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o 
soc21.o \
-   sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o 
lsdma_v6_0.o
+   sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o 
hdp_v5_2.o lsdma_v6_0.o
 
 # add DF block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index f778466bb9db..6437ead87e5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -24,6 +24,7 @@
 #include "amdgpu_reset.h"
 #include "aldebaran.h"
 #include "sienna_cichlid.h"
+#include "smu_v13_0_10.h"
 
 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
 struct amdgpu_reset_handler *handler)
@@ -44,6 +45,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 7):
ret = sienna_cichlid_reset_init(adev);
break;
+   case IP_VERSION(13, 0, 10):
+   ret = smu_v13_0_10_reset_init(adev);
+   break;
default:
break;
}
@@ -62,6 +66,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 7):
ret = sienna_cichlid_reset_fini(adev);
break;
+   case IP_VERSION(13, 0, 10):
+   ret = smu_v13_0_10_reset_fini(adev);
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c 
b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
new file mode 100644
index ..ae29620b1ea4
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "smu_v13_0_10.h"
+#include "amdgpu_reset.h"
+#include "amdgpu_dpm.h"
+#include "amdgpu_job.h"
+#include "amdgpu_ring.h"
+#include "amdgpu_ras.h"
+#include "amdgpu_psp.h"
+
+static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control 
*reset_ctl)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
+   if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev))
+   return true;
+
+   return false;
+}
+
+static struct amdgpu_reset_handler *
+smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
+   struct amdgpu_reset_context *reset_context)
+{
+   struct amdgpu_reset_handler *handler;
+   struct amdgpu_device *adev =

RE: [PATCH] drm/amdgpu: only WARN freeing buffers when DMA is unavailable

2023-02-09 Thread Quan, Evan

[AMD Official Use Only - General]

Hi Jack,

Are you trying to fix the call trace popped up on resuming below?
It seems mes created some bo for its self test and freed it up later at the 
final stage of the resuming process.
All these happened before the in_suspend flag cleared. And that triggered the 
call trace.
Is my understanding correct?

[74084.799260] WARNING: CPU: 2 PID: 2891 at 
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:425 amdgpu_bo_free_kernel+0xfc/0x110 
[amdgpu]
[74084.811019] Modules linked in: nls_iso8859_1 amdgpu(OE) iommu_v2 gpu_sched 
drm_buddy drm_ttm_helper ttm drm_display_helper drm_kms_helper i2c_algo_bit 
fb_sys_fops syscopyarea sysfillrect sysimgblt snd_sm
[74084.811042]  ip_tables x_tables autofs4 hid_logitech_hidpp hid_logitech_dj 
hid_generic e1000e usbhid ptp uas hid video i2c_i801 ahci pps_core crc32_pclmul 
i2c_smbus usb_storage libahci wmi
[74084.914519] CPU: 2 PID: 2891 Comm: kworker/u16:38 Tainted: GW IOE
  6.0.0-custom #1
[74084.923146] Hardware name: ASUS System Product Name/PRIME Z390-A, BIOS 2004 
11/02/2021
[74084.931074] Workqueue: events_unbound async_run_entry_fn
[74084.936393] RIP: 0010:amdgpu_bo_free_kernel+0xfc/0x110 [amdgpu]
[74084.942422] Code: 00 4d 85 ed 74 08 49 c7 45 00 00 00 00 00 4d 85 e4 74 08 
49 c7 04 24 00 00 00 00 5b 41 5c 41 5d 41 5e 41 5f 5d c3 cc cc cc cc <0f> 0b e9 
39 ff ff ff 3d 00 fe ff ff 0f 85 75 96 47 00 ebf
[74084.961199] RSP: :bed6812ebb90 EFLAGS: 00010202
[74084.966435] RAX:  RBX: bed6812ebc50 RCX: 
[74084.973578] RDX: bed6812ebc70 RSI: bed6812ebc60 RDI: bed6812ebc50
[74084.980725] RBP: bed6812ebbb8 R08:  R09: 01ff
[74084.987869] R10: bed6812ebb40 R11:  R12: bed6812ebc70
[74084.995015] R13: bed6812ebc60 R14: 963a2945cc00 R15: 9639c7da5630
[74085.002160] FS:  () GS:963d1dc8() 
knlGS:
[74085.010262] CS:  0010 DS:  ES:  CR0: 80050033
[74085.016016] CR2:  CR3: 000377c0a001 CR4: 003706e0
[74085.023164] DR0:  DR1:  DR2: 
[74085.030307] DR3:  DR6: fffe0ff0 DR7: 0400
[74085.037453] Call Trace:
[74085.039911]  
[74085.042023]  amdgpu_mes_self_test+0x385/0x460 [amdgpu]
[74085.047293]  mes_v11_0_late_init+0x44/0x50 [amdgpu]
[74085.052291]  amdgpu_device_ip_late_init+0x50/0x270 [amdgpu]
[74085.058032]  amdgpu_device_resume+0xb0/0x2d0 [amdgpu]
[74085.063187]  amdgpu_pmops_resume+0x37/0x70 [amdgpu]
[74085.068162]  pci_pm_resume+0x68/0x100
[74085.071836]  ? pci_legacy_resume+0x80/0x80
[74085.075943]  dpm_run_callback+0x4c/0x160
[74085.079873]  device_resume+0xad/0x210
[74085.083546]  async_resume+0x1e/0x40
[74085.087046]  async_run_entry_fn+0x30/0x120
[74085.091152]  process_one_work+0x21a/0x3f0
[74085.095173]  worker_thread+0x50/0x3e0
[74085.098845]  ? process_one_work+0x3f0/0x3f0
[74085.103039]  kthread+0xfa/0x130
[74085.106189]  ? kthread_complete_and_exit+0x20/0x20
[74085.110993]  ret_from_fork+0x1f/0x30
[74085.114576]  
[74085.116773] ---[ end trace  ]---

BR
Evan
From: amd-gfx  On Behalf Of Christian 
König
Sent: Monday, February 6, 2023 5:00 PM
To: Xiao, Jack ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org; Deucher, Alexander 

Subject: Re: [PATCH] drm/amdgpu: only WARN freeing buffers when DMA is 
unavailable

Am 06.02.23 um 09:28 schrieb Xiao, Jack:

[AMD Official Use Only - General]

  >> >> It's simply not allowed to free up 
resources during suspend since those can't be acquired again during resume.
  >> The in_suspend flag is set at the beginning of 
suspend and unset at the end of resume. It can't filter the case you mentioned.

   Why not? This is exactly what it should do.

[Jack] If freeing up resources during resume, it should not hit the issue you 
described. But only checking in_suspend flag would take these cases as warning.

No, once more: Freeing up or allocating resources between suspend and resume is 
illegal!

If you free up a resource during resume you should absolutely hit that, this is 
intentional!

Regards,
Christian.


Regards,
Jack

From: Koenig, Christian 

Sent: Monday, February 6, 2023 4:06 PM
To: Xiao, Jack ; Christian König 
; 
amd-gfx@lists.freedesktop.org; Deucher, 
Alexander 
Subject: Re: [PATCH] drm/amdgpu: only WARN freeing buffers when DMA is 
unavailable

Am 06.02.23 um 08:23 schrieb Xiao, Jack:

[AMD Official Use Only - General]

>> Nope, that is not related to any hw state.

can use other flag.

>> It's simply not allowed to free up resources during suspend since those 
>> can't be acquired again during resume.
The in_suspend flag is set at

RE: gpu_metrics does not provide 'current_gfxclk', 'current_uclk', 'average_cpu_power' & 'temperature_core' on AMD Ryzen 7000 CPU

2023-02-09 Thread Quan, Evan

[AMD Official Use Only - General]

For some members, "0" is a valid value. 
Thus "0x" is used instead to tell the output is invalid/unsupported.

BR
Evan
> -Original Message-
> From: amd-gfx  On Behalf Of
> sfrcorne
> Sent: Wednesday, February 8, 2023 7:12 AM
> To: Alex Deucher 
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: gpu_metrics does not provide 'current_gfxclk', 'current_uclk',
> 'average_cpu_power' & 'temperature_core' on AMD Ryzen 7000 CPU
> 
> Dear Alex,
> 
> If current_gfxclk is not supported for my CPU, then using
> average_gfxclk_frequency instead is indeed the best solution in my opinion.
> I will try to get a fix merged for my CPU in Mangohud.
> 
> On a side note: you mentioned that unsupported fields would be 0 but I
> don't think this is correct. In the Linux kernel/driver there is a line of 
> code
> that first set all values to 0xFF by a memset() and then populates the
> supported fields.
> 
> see
> "https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/pm/s
> wsmu/smu_cmn.c#L999": memset(header, 0xFF, structure_size);
> 
> The value of the unsupported uint16_t fields thus should be 0x (or 65535
> in decimal). This is also what I get when reading the gpu_metrics file. I just
> wanted to mention this in case someone reads this in the Archive.
> 
> Anyway, thank you for your help!
> 
> Kind regards,
> sfrcorne
> 
> --- Original Message ---
> On Tuesday, February 7th, 2023 at 05:05, Alex Deucher
>  wrote:
> 
> 
> > On Mon, Feb 6, 2023 at 5:48 PM sfrcorne sfrco...@protonmail.com wrote:
> >
> > > Dear Alex,
> > >
> > > First of all, thank you for your response. Personally, I use a Ryzen 5 
> > > 7600X
> however people with a Ryzen 9 7900X are also reporting this issue. The
> relevant bug report in Mangohud can be found here:
> "https://github.com/flightlessmango/MangoHud/issues/868;.
> > >
> > > I looked around a bit in both the Mangohud source code and the Linux
> kernel source code.
> > >
> > > (Mangohud source): From what I understand, Mangohud looks for a file
> "/sys/class/drm/card*/device/gpu_metrics". If this file exists (and it does
> exists on my machine), it tries to read this file and extract the relevant GPU
> data (and in case of an APU also the CPU data) from it (these are the values I
> was talking about in my previous mail). When the file
> "/sys/class/drm/card*/device/gpu_metrics" exists, it will not use the data
> provided by hwmon (/sys/class/hwmon/hwmon*/*).
> > >
> > > (Linux kernel): The gpu_metrics file contains different data, depending
> on what version is used. All valid versions can be found in the source code:
> "https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/includ
> e/kgd_pp_interface.h#L725". For my CPU/APU the 'gpu_metrics_v2_1'
> structure is used (I tested this by reading the gpu_metrics file myself).
> Furthermore, I think that for my case, this structure is set by the function
> "https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/pm/s
> wsmu/smu13/smu_v13_0_5_ppt.c#L459" but I am not completely sure
> about this.
> >
> >
> > The metrics provided by the SMU firmware varies from asic to asic.
> > For things that are not supported by the metrics table for a
> > particular asic, those fields would be 0. You can see what metrics are
> > supported for your asic in smu_v13_0_5_get_gpu_metrics() as that
> > function populates the supported fields from the firmware to the
> > common structure. current_gfxclk is not supported in your asic, but
> > average_gfxclk_frequency is. So you'd want to use whichever field is
> > available for a particular asic in Mangohud.
> >
> > > Lastly, I am not familiar with umr. I assume that you are referring to
> "https://gitlab.freedesktop.org/tomstdenis/umr;? If I find some time this
> weekend, then I will look into this some more.
> >
> >
> > Yes, that is the right link. umr uses the same interface as mangohud,
> > so you should see the same data.
> >
> > Alex
> >
> > > Kind regards,
> > > sfrcorne
> > >
> > > --- Original Message ---
> > > On Monday, February 6th, 2023 at 22:22, Alex Deucher
> alexdeuc...@gmail.com wrote:
> > >
> > > > On Mon, Feb 6, 2023 at 9:22 AM sfrcorne sfrco...@protonmail.com
> wrote:
> > > >
> > > > > Hello,
> > > > >
> > > > > I hope this is the correct place to ask my question. I was not sure 
> > > > > if I
> should have opened a new issue on Gitlab or send an email here, since I
> don't know know whether this is a bug or intended behaviour.
> > > > >
> > > > > The question is about the new AMD Ryzen 7000 CPU's. These new
> CPU's have an iGPU and consequently provide a gpu_metrics file for
> monitoring the GPU/CPU (APU?). This file is used by programs like
> Mangohud, that try to read (among other values) the following 4 values:
> > > > > - current_gfxclk
> > > > > - current_uclk
> > > > > - average_cpu_power
> > > > > - temperature_core
> > > > > However it appears that on AMD Ryzen 7000 CPU's these 4 values are
> not

RE: [PATCH v2] drm/amdkfd: To fix sdma page fault issue for GC 11.x

2023-02-09 Thread Zhang, Yifan

[Public]

This patch is :

Reviewed-by: Yifan Zhang 

-Original Message-
From: Ji, Ruili  
Sent: Thursday, February 9, 2023 2:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix ; Deucher, Alexander 
; Liu, Aaron ; Zhang, Yifan 
; Ji, Ruili 
Subject: [PATCH v2] drm/amdkfd: To fix sdma page fault issue for GC 11.x

From: Ruili Ji 

For the MQD memory, KMD would always allocate 4K memory, and mes scheduler 
would write to the end of MQD for unmap flag.

Signed-off-by: Ruili Ji 
---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c |  5 +++--  
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c  | 15 ++-
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c06ada0844ba..7a95698d83f7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2373,7 +2373,7 @@ struct device_queue_manager 
*device_queue_manager_init(struct kfd_dev *dev)
if (init_mqd_managers(dqm))
goto out_free;
 
-   if (allocate_hiq_sdma_mqd(dqm)) {
+   if (!dev->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) {
pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
goto out_free;
}
@@ -2397,7 +2397,8 @@ static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,  
void device_queue_manager_uninit(struct device_queue_manager *dqm)  {
dqm->ops.uninitialize(dqm);
-   deallocate_hiq_sdma_mqd(dqm->dev, >hiq_sdma_mqd);
+   if (!dqm->dev->shared_resources.enable_mes)
+   deallocate_hiq_sdma_mqd(dqm->dev, >hiq_sdma_mqd);
kfree(dqm);
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 4f6390f3236e..4a9af800b1f1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -308,11 +308,16 @@ static void init_mqd_sdma(struct mqd_manager *mm, void 
**mqd,
struct queue_properties *q)
 {
struct v11_sdma_mqd *m;
+   int size;
 
m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr;
 
-   memset(m, 0, sizeof(struct v11_sdma_mqd));
+   if (mm->dev->shared_resources.enable_mes)
+   size = PAGE_SIZE;
+   else
+   size = sizeof(struct v11_sdma_mqd);
 
+   memset(m, 0, size);
*mqd = m;
if (gart_addr)
*gart_addr = mqd_mem_obj->gpu_addr;
@@ -443,6 +448,14 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE 
type,  #if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;  #endif
+   /*
+* To allocate SDMA MQDs by generic functions
+* when MES is enabled.
+*/
+   if (dev->shared_resources.enable_mes) {
+   mqd->allocate_mqd = allocate_mqd;
+   mqd->free_mqd = kfd_free_mqd_cp;
+   }
pr_debug("%s@%i\n", __func__, __LINE__);
break;
default:
--
2.25.1

RE: [PATCH 4/4] Revert "drm/amd/display: disable S/G display on DCN 3.1.5"

2023-02-09 Thread Zhang, Yifan

[Public]

This series is 

Reviewed-by: Yifan Zhang 


-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, February 9, 2023 10:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 4/4] Revert "drm/amd/display: disable S/G display on DCN 3.1.5"

This reverts commit 3cc67fe1b3aa1ac4720e002f2aa2d08c9199a584.

Some users have reported flickerng with S/G display.  We've tried extensively 
to reproduce and debug the issue on a wide variety of platform configurations 
(DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able 
to.  We disabled S/G display on a number of platforms to address this but that 
leads to failure to pin framebuffers errors and blank displays when there is 
memory pressure or no displays at all on systems with limited carveout (e.g., 
Chromebooks).
We have a parameter to disable this as a debugging option as a way for users to 
disable this, depending on their use case, and for us to help debug this 
further.  Having this enabled seems like the lesser of to evils.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f7ba65fd8f48..7f16be84f3b1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1571,6 +1571,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 4):
+   case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
init_data.flags.gpu_vm_support = true;
break;
--
2.39.1

Re: [PATCH 3/3] drm/connector: Deprecate split for BT.2020 in drm_colorspace enum

2023-02-09 Thread Ville Syrjälä

On Thu, Feb 09, 2023 at 05:03:19PM +, Simon Ser wrote:
> On Thursday, February 9th, 2023 at 17:38, Joshua Ashton  
> wrote:
> 
> > > I mean, the strings are the uAPI, not the integers, right?
> >
> > Both are uAPI these days.
> 
> Yes. The integers are uAPI, if you change them you'll break libliftoff
> users. There is an old thread discussing this somewhere. The tl;dr was
> that there is no use-case for exposing the same string with a different
> integer, so no good reason to justify the substantial complexity of
> handling this case.

If people actually depend on that we should probably have tests to
make sure no one breaks it by accident.

-- 
Ville Syrjälä
Intel

[pull] amdgpu drm-fixes-6.2

2023-02-09 Thread Alex Deucher

Hi Dave, Daniel,

A few last minute display fixes.

The following changes since commit c6ac406cd8ff610a2d5da298b1d3071acfcde7f0:

  drm/amdgpu/smu: skip pptable init under sriov (2023-02-08 22:33:37 -0500)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-fixes-6.2-2023-02-09

for you to fetch changes up to e7d636476ba73e61460619bd8822e16af3cba509:

  Revert "drm/amd/display: disable S/G display on DCN 3.1.5" (2023-02-09 
10:29:28 -0500)


amd-drm-fixes-6.2-2023-02-09:

amdgpu:
- Add a parameter to disable S/G display
- Re-enable S/G display on all DCNs


Alex Deucher (4):
  drm/amdgpu: add S/G display parameter
  Revert "drm/amd/display: disable S/G display on DCN 3.1.2/3"
  Revert "drm/amd/display: disable S/G display on DCN 2.1.0"
  Revert "drm/amd/display: disable S/G display on DCN 3.1.5"

 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 11 +++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  7 +++
 3 files changed, 19 insertions(+)

Re: [regression][6.0] After commit b261509952bc19d1012cf732f853659be6ebc61e I see WARNING message at drivers/gpu/drm/drm_modeset_lock.c:276 drm_modeset_drop_locks+0x63/0x70

2023-02-09 Thread Leo Li


Hi Mikhail, seems like your report flew past me, thanks for the ping.

This might be a simple issue of not backing off when deadlock was hit.
drm_atomic_normalize_zpos() can return an error code, and I ignored it
(oops!)

Can you give this patch a try?
https://gitlab.freedesktop.org/-/snippets/7414

- Leo

On 2/9/23 04:27, Mikhail Gavrilov wrote:

Harry, please don't ignore me.
This issue still happens in 6.1 and 6.2
Leo you are the author of the problematic commit please don't stand aside.
Really nobody is interested in clean logs without warnings and errors?
I am 100% sure that reverting commit
b261509952bc19d1012cf732f853659be6ebc61e will stop these warnings. I
also attached fresh logs from 6.2.0-0.rc6.
6.2-rc7 I started to build without commit
b261509952bc19d1012cf732f853659be6ebc61e to avoid these warnings.


On Thu, Oct 13, 2022 at 6:36 PM Mikhail Gavrilov


Hi!
I bisected an issue of the 6.0 kernel which started happening after
6.0-rc7 on all my machines.

Backtrace of this issue looks like as:

[ 2807.339439] [ cut here ]
[ 2807.339445] WARNING: CPU: 11 PID: 2061 at
drivers/gpu/drm/drm_modeset_lock.c:276
drm_modeset_drop_locks+0x63/0x70
[ 2807.339453] Modules linked in: tls uinput rfcomm snd_seq_dummy
snd_hrtimer nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast
nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet
nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat nf_nat
nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip_set nf_tables nfnetlink
qrtr bnep intel_rapl_msr intel_rapl_common snd_sof_amd_renoir
snd_sof_amd_acp snd_sof_pci snd_hda_codec_realtek sunrpc snd_sof
snd_hda_codec_hdmi snd_hda_codec_generic snd_sof_utils snd_hda_intel
snd_intel_dspcfg mt7921e snd_intel_sdw_acpi binfmt_misc snd_soc_core
mt7921_common snd_hda_codec snd_compress vfat ac97_bus edac_mce_amd
mt76_connac_lib snd_pcm_dmaengine fat snd_hda_core snd_rpl_pci_acp6x
snd_pci_acp6x mt76 btusb snd_hwdep kvm_amd btrtl snd_seq btbcm
mac80211 snd_seq_device kvm btintel btmtk libarc4 snd_pcm
snd_pci_acp5x bluetooth snd_timer snd_rn_pci_acp3x irqbypass
snd_acp_config snd_soc_acpi cfg80211 rapl snd joydev pcspkr
asus_nb_wmi wmi_bmof
[ 2807.339519]  snd_pci_acp3x soundcore i2c_piix4 k10temp amd_pmc
asus_wireless zram amdgpu drm_ttm_helper ttm hid_asus asus_wmi
crct10dif_pclmul iommu_v2 crc32_pclmul ledtrig_audio crc32c_intel
gpu_sched sparse_keymap platform_profile hid_multitouch
polyval_clmulni nvme ucsi_acpi drm_buddy polyval_generic
drm_display_helper ghash_clmulni_intel serio_raw nvme_core ccp
typec_ucsi rfkill sp5100_tco r8169 cec nvme_common typec wmi video
i2c_hid_acpi i2c_hid ip6_tables ip_tables fuse
[ 2807.339540] Unloaded tainted modules: acpi_cpufreq():1
acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1
acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1
amd64_edac():1 acpi_cpufreq():1 acpi_cpufreq():1 amd64_edac():1
amd64_edac():1 acpi_cpufreq():1 pcc_cpufreq():1 fjes():1
amd64_edac():1 acpi_cpufreq():1 amd64_edac():1 acpi_cpufreq():1
fjes():1 pcc_cpufreq():1 amd64_edac():1 acpi_cpufreq():1 fjes():1
amd64_edac():1 acpi_cpufreq():1 pcc_cpufreq():1 amd64_edac():1
fjes():1 acpi_cpufreq():1 acpi_cpufreq():1 pcc_cpufreq():1
amd64_edac():1 fjes():1 acpi_cpufreq():1 amd64_edac():1
pcc_cpufreq():1 acpi_cpufreq():1 fjes():1 amd64_edac():1
pcc_cpufreq():1 pcc_cpufreq():1 amd64_edac():1 acpi_cpufreq():1
fjes():1 pcc_cpufreq():1 amd64_edac():1 acpi_cpufreq():1
acpi_cpufreq():1 amd64_edac():1 pcc_cpufreq():1 fjes():1
acpi_cpufreq():1 amd64_edac():1 pcc_cpufreq():1 amd64_edac():1
acpi_cpufreq():1 fjes():1 pcc_cpufreq():1 acpi_cpufreq():1
pcc_cpufreq():1 fjes():1
[ 2807.339579]  acpi_cpufreq():1 fjes():1 pcc_cpufreq():1
acpi_cpufreq():1 pcc_cpufreq():1 acpi_cpufreq():1 fjes():1
acpi_cpufreq():1 pcc_cpufreq():1 fjes():1 pcc_cpufreq():1
acpi_cpufreq():1 fjes():1 acpi_cpufreq():1 fjes():1 fjes():1 fjes():1
fjes():1 fjes():1 fjes():1 fjes():1 fjes():1 fjes():1 fjes():1
fjes():1 fjes():1 fjes():1 fjes():1
[ 2807.339596] CPU: 11 PID: 2061 Comm: gnome-shell Tainted: GW
L 6.0.0-rc4-07-cb0eca01ad9756e853efec3301203c2b5b45aa9f+ #16
[ 2807.339598] Hardware name: ASUSTeK COMPUTER INC. ROG Strix
G513QY_G513QY/G513QY, BIOS G513QY.318 03/29/2022
[ 2807.339600] RIP: 0010:drm_modeset_drop_locks+0x63/0x70
[ 2807.339602] Code: 42 08 48 89 10 48 89 1b 48 8d bb 50 ff ff ff 48
89 5b 08 e8 3f 41 55 00 48 8b 45 78 49 39 c4 75 c6 5b 5d 41 5c c3 cc
cc cc cc <0f> 0b eb ac 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 55
41 54
[ 2807.339604] RSP: 0018:b6ad46e07b80 EFLAGS: 00010282
[ 2807.339606] RAX: 0001 RBX:  RCX: 0002
[ 2807.339607] RDX: 0001 RSI: a6a118b1 RDI: b6ad46e07c00
[ 2807.339608] RBP: b6ad46e07c00 R08:  R09: 
[ 2807.339609] R10:  R11: 0001 R12: 
[ 2807.339610] R13: 9801ca24bb00 R14: 9801ca24bb00 R15:

Re: [PATCH 3/3] drm/connector: Deprecate split for BT.2020 in drm_colorspace enum

2023-02-09 Thread Simon Ser

On Thursday, February 9th, 2023 at 17:38, Joshua Ashton  
wrote:

> > I mean, the strings are the uAPI, not the integers, right?
>
> Both are uAPI these days.

Yes. The integers are uAPI, if you change them you'll break libliftoff
users. There is an old thread discussing this somewhere. The tl;dr was
that there is no use-case for exposing the same string with a different
integer, so no good reason to justify the substantial complexity of
handling this case.

Re: [PATCH 3/3] drm/connector: Deprecate split for BT.2020 in drm_colorspace enum

2023-02-09 Thread Joshua Ashton





On 2/8/23 09:30, Pekka Paalanen wrote:

On Fri,  3 Feb 2023 02:07:44 +
Joshua Ashton  wrote:


Userspace has no way of controlling or knowing the pixel encoding
currently, so there is no way for it to ever get the right values here.

When we do add pixel_encoding control from userspace,we can pick the
right value for the colorimetry packet based on the
pixel_encoding + the colorspace.

Let's deprecate these values, and have one BT.2020 colorspace entry
that userspace can use.

Note: _CYCC was effectively 'removed' by this change, but that was not
possible to be taken advantage of anyway, as there is currently no
pixel_encoding control so it would not be possible to output
linear YCbCr.

Signed-off-by: Joshua Ashton 

Cc: Pekka Paalanen 
Cc: Sebastian Wick 
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar 
Cc: Ville Syrjälä 
Cc: Joshua Ashton 
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
  drivers/gpu/drm/display/drm_hdmi_helper.c |  9 -
  drivers/gpu/drm/drm_connector.c   | 12 ++--
  drivers/gpu/drm/i915/display/intel_dp.c   | 20 +---
  include/drm/drm_connector.h   | 19 ++-
  4 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c 
b/drivers/gpu/drm/display/drm_hdmi_helper.c
index 0264abe55278..c85860600395 100644
--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ -99,8 +99,7 @@ EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
  #define HDMI_COLORIMETRY_OPYCC_601(C(3) | EC(3) | ACE(0))
  #define HDMI_COLORIMETRY_OPRGB(C(3) | EC(4) | ACE(0))
  #define HDMI_COLORIMETRY_BT2020_CYCC  (C(3) | EC(5) | ACE(0))
-#define HDMI_COLORIMETRY_BT2020_RGB(C(3) | EC(6) | ACE(0))
-#define HDMI_COLORIMETRY_BT2020_YCC(C(3) | EC(6) | ACE(0))
+#define HDMI_COLORIMETRY_BT2020(C(3) | EC(6) | ACE(0))
  #define HDMI_COLORIMETRY_DCI_P3_RGB_D65   (C(3) | EC(7) | ACE(0))
  #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER   (C(3) | EC(7) | ACE(1))
  
@@ -113,9 +112,9 @@ static const u32 hdmi_colorimetry_val[] = {

[DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
[DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
[DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
-   [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
-   [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
-   [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
+   [DRM_MODE_COLORIMETRY_BT2020_DEPRECATED_1] = HDMI_COLORIMETRY_BT2020,
+   [DRM_MODE_COLORIMETRY_BT2020_DEPRECATED_2] = HDMI_COLORIMETRY_BT2020,
+   [DRM_MODE_COLORIMETRY_BT2020] = HDMI_COLORIMETRY_BT2020,
  };
  
  #undef C

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 61c29ce74b03..58699ab15a6a 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1029,11 +1029,11 @@ static const struct drm_prop_enum_list 
hdmi_colorspaces[] = {
/* Colorimetry based on IEC 61966-2-5 */
{ DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+   { DRM_MODE_COLORIMETRY_BT2020_DEPRECATED_1, "BT2020_DEPRECATED_1" },
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+   { DRM_MODE_COLORIMETRY_BT2020_DEPRECATED_2, "BT2020_DEPRECATED_2" },
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+   { DRM_MODE_COLORIMETRY_BT2020, "BT2020" },
/* Added as part of Additional Colorimetry Extension in 861.G */
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65, "DCI-P3_RGB_D65" },
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
@@ -1054,7 +1054,7 @@ static const struct drm_prop_enum_list dp_colorspaces[] = 
{
/* Colorimetry based on SMPTE RP 431-2 */
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65, "DCI-P3_RGB_D65" },
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+   { DRM_MODE_COLORIMETRY_BT2020, "BT2020" },
{ DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
{ DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
/* Standard Definition Colorimetry based on IEC 61966-2-4 */
@@ -1066,9 +1066,9 @@ static const struct drm_prop_enum_list dp_colorspaces[] = 
{
/* Colorimetry based on IEC 61966-2-5 [33] */
{ DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
/* Colorimetry based on ITU-R BT.2020 */
-   { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+   { DRM_MODE_COLORIMETRY_BT2020_DEPRECATED_1, "BT2020_DEPRECATED_1" },
/* Colorimetry based on ITU-R BT.2020 */
-   {

[linux-next:master] BUILD REGRESSION 20f513df926fac0594a3b65f79d856bd64251861

2023-02-09 Thread kernel test robot

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 20f513df926fac0594a3b65f79d856bd64251861  Add linux-next specific 
files for 20230209

Error/Warning reports:

https://lore.kernel.org/oe-kbuild-all/202301302110.metnwkbd-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202301310939.tagcoezb-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202302061911.c7xvhx9v-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202302062224.byzetxh1-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202302092211.54eydhyh-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

Documentation/sphinx/templates/kernel-toc.html: 1:36 Invalid token: #}
ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/fsl-edma.ko] 
undefined!
ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/idma64.ko] 
undefined!
FAILED: load BTF from vmlinux: No data available
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hubbub.c:1011:6: warning: 
no previous prototype for 'hubbub31_init' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:948:6: warning: 
no previous prototype for 'hubbub32_init' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubp.c:158:6: warning: no 
previous prototype for 'hubp32_init' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:62:18: 
warning: variable 'cursor_bpp' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1296:32:
 warning: variable 'result_write_min_hblank' set but not used 
[-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:280:42:
 warning: variable 'ds_port' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training.c:1586:38:
 warning: variable 'result' set but not used [-Wunused-but-set-variable]
drivers/net/can/dev/bittiming.c:145:24: error: too many arguments to function 
'can_calc_bittiming'
ftrace-ops.c:(.init.text+0x2c3): undefined reference to `__udivdi3'
libbpf: failed to find '.BTF' ELF section in vmlinux

Unverified Error/Warning (likely false positive, please contact us if 
interested):

drivers/tty/serial/8250/8250_dfl.c:63 dfl_uart_get_params() error: 
uninitialized symbol 'clk_freq'.
drivers/tty/serial/8250/8250_dfl.c:69 dfl_uart_get_params() error: 
uninitialized symbol 'fifo_len'.
drivers/tty/serial/8250/8250_dfl.c:90 dfl_uart_get_params() error: 
uninitialized symbol 'reg_layout'.
drivers/usb/gadget/composite.c:2082:33: sparse: sparse: restricted __le16 
degrades to integer
drivers/usb/gadget/function/uvc_configfs.c:537:2-8: preceding lock on line 528
drivers/usb/gadget/udc/renesas_usbf.c:2284:37: sparse:left side has type 
unsigned short
drivers/usb/gadget/udc/renesas_usbf.c:2284:37: sparse:right side has type 
restricted __le16
drivers/usb/gadget/udc/renesas_usbf.c:2284:37: sparse: sparse: invalid 
assignment: |=
drivers/usb/gadget/udc/renesas_usbf.c:2325:31: sparse: sparse: restricted 
__le16 degrades to integer
drivers/usb/host/xhci-plat.c:371 xhci_generic_plat_probe() error: we previously 
assumed 'sysdev' could be null (see line 361)
sound/firewire/amdtp-stream.c:1187 process_rx_packets() error: uninitialized 
symbol 'curr_cycle_time'.

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used
|-- alpha-randconfig-s043-20230209
|   `-- 
drivers-usb-gadget-composite.c:sparse:sparse:restricted-__le16-degrades-to-integer
|-- arc-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used
|-- arm-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used
|-- arm-randconfig-r046-20230209
|   `-- 
drivers-net-can-dev-bittiming.c:error:too-many-arguments-to-function-can_calc

Re: [PATCH 1/4] drm/amdgpu: add S/G display parameter

2023-02-09 Thread Harry Wentland

On 2/9/23 09:37, Christian König wrote:
> Am 09.02.23 um 15:11 schrieb Alex Deucher:
>> Some users have reported flickerng with S/G display.  We've
>> tried extensively to reproduce and debug the issue on a wide
>> variety of platform configurations (DRAM bandwidth, etc.) and
>> a variety of monitors, but so far have not been able to.  We
>> disabled S/G display on a number of platforms to address this
>> but that leads to failure to pin framebuffers errors and
>> blank displays when there is memory pressure or no displays
>> at all on systems with limited carveout (e.g., Chromebooks).
>> Add a option to disable this as a debugging option as a
>> way for users to disable this, depending on their use case,
>> and for us to help debug this further.
>>
>> Signed-off-by: Alex Deucher 
> 
> Acked-by: Christian König  for the series.
> 

Series is
Reviewed-by: Harry Wentland 

Harry

>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 11 +++
>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
>>   3 files changed, 15 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 64f9cc6fbbf0..187597024c1e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -242,6 +242,7 @@ extern int amdgpu_num_kcq;
>>     #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
>>   extern int amdgpu_vcnfw_log;
>> +extern int amdgpu_sg_display;
>>     extern int amdgpu_force_sg_display;
>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index fa3788bb6a2c..afa5c39c9c74 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -188,6 +188,7 @@ int amdgpu_num_kcq = -1;
>>   int amdgpu_smartshift_bias;
>>   int amdgpu_use_xgmi_p2p = 1;
>>   int amdgpu_vcnfw_log;
>> +int amdgpu_sg_display = -1; /* auto */
>>     static void amdgpu_drv_delayed_reset_work_handler(struct work_struct 
>> *work);
>>   @@ -933,6 +934,16 @@ module_param_named(num_kcq, amdgpu_num_kcq, int, 
>> 0444);
>>   MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 
>> 1 = enable)");
>>   module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
>>   +/**
>> + * DOC: sg_display (int)
>> + * Disable S/G (scatter/gather) display (i.e., display from system memory).
>> + * This option is only relevant on APUs.  Set this option to 0 to disable
>> + * S/G display if you experience flickering or other issues under memory
>> + * pressure and report the issue.
>> + */
>> +MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = 
>> disable)");
>> +module_param_named(sg_display, amdgpu_sg_display, int, 0444);
>> +
>>   /**
>>    * DOC: smu_pptable_id (int)
>>    * Used to override pptable id. id = 0 use VBIOS pptable.
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index bf06875e6a01..1babdfaa789a 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -1576,6 +1576,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>>   }
>>   break;
>>   }
>> +    if (init_data.flags.gpu_vm_support &&
>> +    (amdgpu_sg_display == 0))
>> +    adev->mode_info.gpu_vm_support = false;
>>     if (init_data.flags.gpu_vm_support)
>>   adev->mode_info.gpu_vm_support = true;
>

Re: [PATCH 1/4] drm/amdgpu: add S/G display parameter

2023-02-09 Thread Christian König


Am 09.02.23 um 15:11 schrieb Alex Deucher:

Some users have reported flickerng with S/G display.  We've
tried extensively to reproduce and debug the issue on a wide
variety of platform configurations (DRAM bandwidth, etc.) and
a variety of monitors, but so far have not been able to.  We
disabled S/G display on a number of platforms to address this
but that leads to failure to pin framebuffers errors and
blank displays when there is memory pressure or no displays
at all on systems with limited carveout (e.g., Chromebooks).
Add a option to disable this as a debugging option as a
way for users to disable this, depending on their use case,
and for us to help debug this further.

Signed-off-by: Alex Deucher 


Acked-by: Christian König  for the series.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 11 +++
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
  3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 64f9cc6fbbf0..187597024c1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -242,6 +242,7 @@ extern int amdgpu_num_kcq;
  
  #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)

  extern int amdgpu_vcnfw_log;
+extern int amdgpu_sg_display;
  
  extern int amdgpu_force_sg_display;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index fa3788bb6a2c..afa5c39c9c74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -188,6 +188,7 @@ int amdgpu_num_kcq = -1;
  int amdgpu_smartshift_bias;
  int amdgpu_use_xgmi_p2p = 1;
  int amdgpu_vcnfw_log;
+int amdgpu_sg_display = -1; /* auto */
  
  static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
  
@@ -933,6 +934,16 @@ module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);

  MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = 
enable)");
  module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
  
+/**

+ * DOC: sg_display (int)
+ * Disable S/G (scatter/gather) display (i.e., display from system memory).
+ * This option is only relevant on APUs.  Set this option to 0 to disable
+ * S/G display if you experience flickering or other issues under memory
+ * pressure and report the issue.
+ */
+MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
+module_param_named(sg_display, amdgpu_sg_display, int, 0444);
+
  /**
   * DOC: smu_pptable_id (int)
   * Used to override pptable id. id = 0 use VBIOS pptable.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bf06875e6a01..1babdfaa789a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1576,6 +1576,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
}
break;
}
+   if (init_data.flags.gpu_vm_support &&
+   (amdgpu_sg_display == 0))
+   adev->mode_info.gpu_vm_support = false;
  
  	if (init_data.flags.gpu_vm_support)

adev->mode_info.gpu_vm_support = true;

Re: [PATCH][next] drm/amd/display: Fix spelling mistakes of function name in error message

2023-02-09 Thread Alex Deucher

Applied.  Thanks!

Alex

On Thu, Feb 9, 2023 at 7:53 AM Colin Ian King  wrote:
>
> The function name is being reported as dc_link_contruct when it is
> actually dc_link_construct_phy. Fix this by using %s and the __func__
> for the function name.
>
> Signed-off-by: Colin Ian King 
> ---
>  drivers/gpu/drm/amd/display/dc/link/link_factory.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c 
> b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
> index 13a766273755..3fc93fc593fb 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
> @@ -452,7 +452,7 @@ static bool dc_link_construct_phy(struct dc_link *link,
> link->psr_settings.psr_vtotal_control_support = false;
> link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
>
> -   DC_LOG_DC("BIOS object table - dc_link_contruct finished 
> successfully.\n");
> +   DC_LOG_DC("BIOS object table - %s finished successfully.\n", 
> __func__);
> return true;
>  device_tag_fail:
> link->link_enc->funcs->destroy(>link_enc);
> @@ -469,7 +469,7 @@ static bool dc_link_construct_phy(struct dc_link *link,
> link->hpd_gpio = NULL;
> }
>
> -   DC_LOG_DC("BIOS object table - dc_link_contruct failed.\n");
> +   DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
> return false;
>  }
>
> --
> 2.30.2
>

Re: [PATCH v2] drm/amd/display: remove duplicate include header

2023-02-09 Thread Alex Deucher

Applied.  Thanks!

Alex

On Thu, Feb 9, 2023 at 5:48 AM  wrote:
>
> From: Ye Xingchen 
>
> link_hwss.h is included more than once in link_dpms.c .
>
> Signed-off-by: Ye Xingchen 
> ---
> v1 -> v2
> Fix the U+00A0 non-breaking space in the subject line.
>  drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c 
> b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> index 9cdfa7f7dc77..0c26b3589608 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> @@ -51,7 +51,6 @@
>  #include "link_enc_cfg.h"
>  #include "resource.h"
>  #include "dsc.h"
> -#include "link_hwss.h"
>  #include "dccg.h"
>  #include "clk_mgr.h"
>  #include "atomfirmware.h"
> --
> 2.25.1

Re: [PATCH] drm/amd/display: fix link_validation build failure

2023-02-09 Thread Alex Deucher

Applied.  Thanks!

Alex

On Thu, Feb 9, 2023 at 7:45 AM Arnd Bergmann  wrote:
>
> From: Arnd Bergmann 
>
> When CONFIG_DRM_AMD_DC_DCN is disabled, the is_frl member
> is not defined:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c: In function 
> 'dp_active_dongle_validate_timing':
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:126:66: 
> error: 'const struct dc_dsc_config' has no member named 'is_frl'
>   126 | if (timing->flags.DSC && 
> !timing->dsc_cfg.is_frl)
>   |  ^
>
> Use the same #ifdef as the other references to this.
>
> Fixes: 5461d1ea ("drm/amd/display: break down dc_link.c")
> Signed-off-by: Arnd Bergmann 
> ---
>  drivers/gpu/drm/amd/display/dc/link/link_validation.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c 
> b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
> index cd821d077d73..8ddebf3bdd46 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
> @@ -123,9 +123,11 @@ static bool dp_active_dongle_validate_timing(
> if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP 
> to HDMI FRL converter
> struct dc_crtc_timing outputTiming = *timing;
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
> /* DP input has DSC, HDMI FRL output doesn't 
> have DSC, remove DSC from output timing */
> outputTiming.flags.DSC = 0;
> +#endif
> if (dc_bandwidth_in_kbps_from_timing() > 
> dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
> return false;
> } else { // DP to HDMI TMDS converter
> --
> 2.39.1
>

Re: [PATCH] drm/amd/display: set should_disable_otg storage-class-specifier to static

2023-02-09 Thread Alex Deucher

Applied.  Thanks!

Alex

On Thu, Feb 9, 2023 at 8:41 AM Tom Rix  wrote:
>
> smatch reports
> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:90:6:
>   warning: symbol 'should_disable_otg' was not declared. Should it be static?
>
> should_disable_otg() is only used in dcn315_clk_mgr.c, so it should be static
>
> Signed-off-by: Tom Rix 
> ---
>  drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
> index 8c368bcc8e7e..a737782b2840 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
> @@ -87,7 +87,7 @@ static int dcn315_get_active_display_cnt_wa(
> return display_count;
>  }
>
> -bool should_disable_otg(struct pipe_ctx *pipe)
> +static bool should_disable_otg(struct pipe_ctx *pipe)
>  {
> bool ret = true;
>
> --
> 2.26.3
>

Re: [RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface

2023-02-09 Thread Melissa Wen

On 01/31, Pekka Paalanen wrote:
> On Mon, 9 Jan 2023 14:38:09 -0100
> Melissa Wen  wrote:
> 
> > On 01/09, Melissa Wen wrote:
> > > Hi,
> > > 
> > > After collecting comments in different places, here is a second version
> > > of the work on adding DRM CRTC 3D LUT support to the current DRM color
> > > mgmt interface. In comparison to previous proposals [1][2][3], here we
> > > add 3D LUT before gamma 1D LUT, but also a shaper 1D LUT before 3D LUT,
> > > that means the following DRM CRTC color correction pipeline:
> > > 
> > > Blend -> Degamma 1D LUT -> CTM -> Shaper 1D LUT -> 3D LUT -> Gamma 1D LUT
> 
> Hi Melissa,
> 
> that makes sense to me, for CRTCs. It would be really good to have that
> as a diagram in the KMS UAPI documentation.
> 

Hi Pekka,

Thanks for your feedbacks and your time reviewing this proposal.

> If someone wants to add a 3D LUT to KMS planes as well, then I'm not
> sure if it should be this order or swapped. I will probably have an
> opinion about that once Weston is fully HDR capable and has been tried
> in the wild for a while with the HDR color operations fine-tuned based
> on community feedback. IOW, not for a long time. The YUV to RGB
> conversion factors in there as well.
> 
I see, this is also the reason I reuse here Alex Hung's proposal for
pre-blending API. I'll work on better documentation.

> 
> > > 
> > > and we also add a DRM CRTC LUT3D_MODE property, based on Alex Hung
> > > proposal for pre-blending 3D LUT [4] (Thanks!), instead of just a
> > > LUT3D_SIZE, that allows userspace to use different supported settings of
> > > 3D LUT, fitting VA-API and new color API better. In this sense, I
> > > adjusted the pre-blending proposal for post-blending usage.
> > > 
> > > Patches 1-6 targets the addition of shaper LUT and 3D LUT properties to
> > > the current DRM CRTC color mgmt pipeline. Patch 6 can be considered an
> > > extra/optional patch to define a default value for LUT3D_MODE, inspired
> > > by what we do for the plane blend mode property (pre-multiplied).
> > > 
> > > Patches 7-18 targets AMD display code to enable shaper and 3D LUT usage
> > > on DCN 301 (our HW case). Patches 7-9 performs code cleanups on current
> > > AMD DM colors code, patch 10 updates AMD stream in case of user 3D LUT
> > > changes, patch 11/12 rework AMD MPC 3D LUT resource handling by context
> > > for DCN 301 (easily extendible to other DCN families). Finally, from
> > > 13-18, we wire up SHAPER LUT, LUT3D and LUT3D MODE to AMD display
> > > driver, exposing modes supported by HW and programming user shaper and
> > > 3D LUT accordingly.
> > > 
> > > Our target userspace is Gamescope/SteamOS.
> > > 
> > > Basic IGT tests were based on [5][6] and are available here (in-progress):
> > > https://gitlab.freedesktop.org/mwen/igt-gpu-tools/-/commits/crtc-lut3d-api
> > > 
> > > [1] 
> > > https://lore.kernel.org/all/20201221015730.28333-1-laurent.pinchart+rene...@ideasonboard.com/
> > > [2] 
> > > https://github.com/vsyrjala/linux/commit/4d28e8ddf2a076f30f9e5bdc17cbb4656fe23e69
> > > [3] 
> > > https://lore.kernel.org/amd-gfx/20220619223104.667413-1-m...@igalia.com/
> > > [4] 
> > > https://lore.kernel.org/dri-devel/20221004211451.1475215-1-alex.h...@amd.com/
> > > [5] https://patchwork.freedesktop.org/series/90165/
> > > [6] https://patchwork.freedesktop.org/series/109402/
> > > [VA_API] 
> > > http://intel.github.io/libva/structVAProcFilterParameterBuffer3DLUT.html
> > > [KMS_pipe_API] https://gitlab.freedesktop.org/pq/color-and-hdr/-/issues/11
> > > 
> > > Let me know your thoughts.  
> > 
> > +Simon Ser, +Pekka Paalanen who might also be interested in this series.
> 
> Unfortunately I don't have the patch emails to reply to, so here's a
> messy bunch of comments. I'll concentrate on the UAPI design as always.

Sorry, the patchset is here: 
https://lore.kernel.org/dri-devel/20230109143846.1966301-1-m...@igalia.com/
In the next version, I won't forget cc'ing you at first.
> 
> +/*
> + * struct drm_mode_lut3d_mode - 3D LUT mode information.
> + * @lut_size: number of valid points on every dimension of 3D LUT.
> + * @lut_stride: number of points on every dimension of 3D LUT.
> + * @bit_depth: number of bits of RGB. If color_mode defines entries with 
> higher
> + * bit_depth the least significant bits will be truncated.
> + * @color_format: fourcc values, ex. DRM_FORMAT_XRGB16161616 or 
> DRM_FORMAT_XBGR16161616.
> + * @flags: flags for hardware-sepcific features
> + */
> +struct drm_mode_lut3d_mode {
> + __u16 lut_size;
> + __u16 lut_stride[3];
> + __u16 bit_depth;
> + __u32 color_format;
> + __u32 flags;
> +};
> 
> Why is lut_stride an array of 3, but lut_size is not?

It cames from VA-API:
https://intel.github.io/libva/structVAProcFilterParameterBuffer3DLUT.html#a682756be15d09327ba725b74a863cbcc

In short, the reason is that lut_size is the valid points and is
the same for every dimensions, but lut_stride may vary.
> 
> What is the color_mode the comment is

[PATCH 4/4] Revert "drm/amd/display: disable S/G display on DCN 3.1.5"

2023-02-09 Thread Alex Deucher

This reverts commit 3cc67fe1b3aa1ac4720e002f2aa2d08c9199a584.

Some users have reported flickerng with S/G display.  We've
tried extensively to reproduce and debug the issue on a wide
variety of platform configurations (DRAM bandwidth, etc.) and
a variety of monitors, but so far have not been able to.  We
disabled S/G display on a number of platforms to address this
but that leads to failure to pin framebuffers errors and
blank displays when there is memory pressure or no displays
at all on systems with limited carveout (e.g., Chromebooks).
We have a parameter to disable this as a debugging option as a
way for users to disable this, depending on their use case,
and for us to help debug this further.  Having this enabled
seems like the lesser of to evils.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f7ba65fd8f48..7f16be84f3b1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1571,6 +1571,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 4):
+   case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
init_data.flags.gpu_vm_support = true;
break;
-- 
2.39.1

[PATCH 3/4] Revert "drm/amd/display: disable S/G display on DCN 2.1.0"

2023-02-09 Thread Alex Deucher

This reverts commit 2404f9b0ea0153c3fddb0c4d7a43869dc8608f6f.

Some users have reported flickerng with S/G display.  We've
tried extensively to reproduce and debug the issue on a wide
variety of platform configurations (DRAM bandwidth, etc.) and
a variety of monitors, but so far have not been able to.  We
disabled S/G display on a number of platforms to address this
but that leads to failure to pin framebuffers errors and
blank displays when there is memory pressure or no displays
at all on systems with limited carveout (e.g., Chromebooks).
We have a parameter to disable this as a debugging option as a
way for users to disable this, depending on their use case,
and for us to help debug this further.  Having this enabled
seems like the lesser of to evils.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d22bbd6d8ba5..f7ba65fd8f48 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1566,6 +1566,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
(adev->apu_flags & AMD_APU_IS_PICASSO))
init_data.flags.gpu_vm_support = true;
break;
+   case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
-- 
2.39.1

[PATCH 2/4] Revert "drm/amd/display: disable S/G display on DCN 3.1.2/3"

2023-02-09 Thread Alex Deucher

This reverts commit f081cd4ca2658752a8c0e2353d50aec80d07c65f.

Some users have reported flickerng with S/G display.  We've
tried extensively to reproduce and debug the issue on a wide
variety of platform configurations (DRAM bandwidth, etc.) and
a variety of monitors, but so far have not been able to.  We
disabled S/G display on a number of platforms to address this
but that leads to failure to pin framebuffers errors and
blank displays when there is memory pressure or no displays
at all on systems with limited carveout (e.g., Chromebooks).
We have a parameter to disable this as a debugging option as a
way for users to disable this, depending on their use case,
and for us to help debug this further.  Having this enabled
seems like the lesser of to evils.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1babdfaa789a..d22bbd6d8ba5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1567,6 +1567,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.flags.gpu_vm_support = true;
break;
case IP_VERSION(3, 0, 1):
+   case IP_VERSION(3, 1, 2):
+   case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 6):
init_data.flags.gpu_vm_support = true;
-- 
2.39.1

[PATCH 1/4] drm/amdgpu: add S/G display parameter

2023-02-09 Thread Alex Deucher

Some users have reported flickerng with S/G display.  We've
tried extensively to reproduce and debug the issue on a wide
variety of platform configurations (DRAM bandwidth, etc.) and
a variety of monitors, but so far have not been able to.  We
disabled S/G display on a number of platforms to address this
but that leads to failure to pin framebuffers errors and
blank displays when there is memory pressure or no displays
at all on systems with limited carveout (e.g., Chromebooks).
Add a option to disable this as a debugging option as a
way for users to disable this, depending on their use case,
and for us to help debug this further.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 11 +++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
 3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 64f9cc6fbbf0..187597024c1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -242,6 +242,7 @@ extern int amdgpu_num_kcq;
 
 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
 extern int amdgpu_vcnfw_log;
+extern int amdgpu_sg_display;
 
 extern int amdgpu_force_sg_display;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index fa3788bb6a2c..afa5c39c9c74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -188,6 +188,7 @@ int amdgpu_num_kcq = -1;
 int amdgpu_smartshift_bias;
 int amdgpu_use_xgmi_p2p = 1;
 int amdgpu_vcnfw_log;
+int amdgpu_sg_display = -1; /* auto */
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
 
@@ -933,6 +934,16 @@ module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = 
enable)");
 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
 
+/**
+ * DOC: sg_display (int)
+ * Disable S/G (scatter/gather) display (i.e., display from system memory).
+ * This option is only relevant on APUs.  Set this option to 0 to disable
+ * S/G display if you experience flickering or other issues under memory
+ * pressure and report the issue.
+ */
+MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
+module_param_named(sg_display, amdgpu_sg_display, int, 0444);
+
 /**
  * DOC: smu_pptable_id (int)
  * Used to override pptable id. id = 0 use VBIOS pptable.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bf06875e6a01..1babdfaa789a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1576,6 +1576,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
}
break;
}
+   if (init_data.flags.gpu_vm_support &&
+   (amdgpu_sg_display == 0))
+   adev->mode_info.gpu_vm_support = false;
 
if (init_data.flags.gpu_vm_support)
adev->mode_info.gpu_vm_support = true;
-- 
2.39.1

Re: [PATCH 1/2] drm/amdgpu/gmc11: fix system aperture set when AGP is enabled

2023-02-09 Thread Zhang, Hawking

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
From: amd-gfx  on behalf of Alex Deucher 

Date: Thursday, February 9, 2023 at 21:43
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander 
Subject: [PATCH 1/2] drm/amdgpu/gmc11: fix system aperture set when AGP is 
enabled
Need to cover both FB and AGP apertures.

v2: fix missed gfxhub_v3_0_3.c

Fixes: c6eafee038ed ("Revert "Revert "drm/amdgpu/gmc11: enable AGP aperture""")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c   | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 8 
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c| 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c  | 4 ++--
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
index 7c069010ca9a..be0d0f47415e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
@@ -159,9 +159,9 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)

 /* Program the system aperture low logical page number. */
 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

 /* Set default page address. */
 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
index 3dc17a3deedb..6e0bd628c889 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
@@ -159,14 +159,14 @@ static void 
gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)

 /* Disable AGP. */
 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FF);
+   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

 /* Program the system aperture low logical page number. */
 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

 /* Set default page address. */
 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index 923fc09bc8fc..164948c50ac3 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -184,9 +184,9 @@ static void mmhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)

 /* Program the system aperture low logical page number. */
 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

 /* Set default page address. */
 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
index c8d478f2afdc..26509b6b8c24 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
@@ -183,9 +183,9 @@ static void mmhub_v3_0_1_init_system_aperture_regs(struct 
amdgpu_device *adev)
  */
 /* Program the system aperture low logical page number. */
 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

 /* Set default page address. */
 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
index 51580302ec42..26abbc6a47ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
@@ -175,9 +175,9 @@

[PATCH] drm/amd/display: set should_disable_otg storage-class-specifier to static

2023-02-09 Thread Tom Rix

smatch reports
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:90:6:
  warning: symbol 'should_disable_otg' was not declared. Should it be static?

should_disable_otg() is only used in dcn315_clk_mgr.c, so it should be static

Signed-off-by: Tom Rix 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 8c368bcc8e7e..a737782b2840 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -87,7 +87,7 @@ static int dcn315_get_active_display_cnt_wa(
return display_count;
 }
 
-bool should_disable_otg(struct pipe_ctx *pipe)
+static bool should_disable_otg(struct pipe_ctx *pipe)
 {
bool ret = true;
 
-- 
2.26.3

[PATCH 1/2] drm/amdgpu/gmc11: fix system aperture set when AGP is enabled

2023-02-09 Thread Alex Deucher

Need to cover both FB and AGP apertures.

v2: fix missed gfxhub_v3_0_3.c

Fixes: c6eafee038ed ("Revert "Revert "drm/amdgpu/gmc11: enable AGP aperture""")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c   | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 8 
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c| 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c  | 4 ++--
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
index 7c069010ca9a..be0d0f47415e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
@@ -159,9 +159,9 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
 
/* Program the system aperture low logical page number. */
WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
index 3dc17a3deedb..6e0bd628c889 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
@@ -159,14 +159,14 @@ static void 
gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)
 
/* Disable AGP. */
WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FF);
+   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+   WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
/* Program the system aperture low logical page number. */
WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index 923fc09bc8fc..164948c50ac3 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -184,9 +184,9 @@ static void mmhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
 
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
index c8d478f2afdc..26509b6b8c24 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
@@ -183,9 +183,9 @@ static void mmhub_v3_0_1_init_system_aperture_regs(struct 
amdgpu_device *adev)
 */
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
index 51580302ec42..26abbc6a47ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
@@ -175,9 +175,9 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct 
amdgpu_device *adev)
 */
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+

[PATCH 2/2] drm/amd/display: minor cleanup of vm_setup

2023-02-09 Thread Alex Deucher

Use fb_start/end for consistency with gmc code for non-
XGMI systems, they are equivalent to vram_start/end.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8ba4a57d8e6f..bf06875e6a01 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1191,7 +1191,7 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
 
/* AGP aperture is disabled */
if (agp_bot == agp_top) {
-   logical_addr_low  = adev->gmc.vram_start >> 18;
+   logical_addr_low = adev->gmc.fb_start >> 18;
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which
@@ -1201,9 +1201,9 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
 */
logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
else
-   logical_addr_high = adev->gmc.vram_end >> 18;
+   logical_addr_high = adev->gmc.fb_end >> 18;
} else {
-   logical_addr_low  = min(adev->gmc.fb_start, 
adev->gmc.agp_start) >> 18;
+   logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) 
>> 18;
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which
-- 
2.39.1

[PATCH][next] drm/amd/display: Fix spelling mistakes of function name in error message

2023-02-09 Thread Colin Ian King

The function name is being reported as dc_link_contruct when it is
actually dc_link_construct_phy. Fix this by using %s and the __func__
for the function name.

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/display/dc/link/link_factory.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c 
b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 13a766273755..3fc93fc593fb 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -452,7 +452,7 @@ static bool dc_link_construct_phy(struct dc_link *link,
link->psr_settings.psr_vtotal_control_support = false;
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
-   DC_LOG_DC("BIOS object table - dc_link_contruct finished 
successfully.\n");
+   DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
return true;
 device_tag_fail:
link->link_enc->funcs->destroy(>link_enc);
@@ -469,7 +469,7 @@ static bool dc_link_construct_phy(struct dc_link *link,
link->hpd_gpio = NULL;
}
 
-   DC_LOG_DC("BIOS object table - dc_link_contruct failed.\n");
+   DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
return false;
 }
 
-- 
2.30.2

[PATCH v2] drm/amd/display: remove duplicate include header

2023-02-09 Thread ye.xingchen

From: Ye Xingchen 

link_hwss.h is included more than once in link_dpms.c .

Signed-off-by: Ye Xingchen 
---
v1 -> v2
Fix the U+00A0 non-breaking space in the subject line.
 drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c 
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 9cdfa7f7dc77..0c26b3589608 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -51,7 +51,6 @@
 #include "link_enc_cfg.h"
 #include "resource.h"
 #include "dsc.h"
-#include "link_hwss.h"
 #include "dccg.h"
 #include "clk_mgr.h"
 #include "atomfirmware.h"
-- 
2.25.1

[PATCH] drm/amd/display: fix link_validation build failure

2023-02-09 Thread Arnd Bergmann

From: Arnd Bergmann 

When CONFIG_DRM_AMD_DC_DCN is disabled, the is_frl member
is not defined:

drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c: In function 
'dp_active_dongle_validate_timing':
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:126:66: error: 
'const struct dc_dsc_config' has no member named 'is_frl'
  126 | if (timing->flags.DSC && 
!timing->dsc_cfg.is_frl)
  |  ^

Use the same #ifdef as the other references to this.

Fixes: 5461d1ea ("drm/amd/display: break down dc_link.c")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/link/link_validation.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c 
b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index cd821d077d73..8ddebf3bdd46 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -123,9 +123,11 @@ static bool dp_active_dongle_validate_timing(
if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP 
to HDMI FRL converter
struct dc_crtc_timing outputTiming = *timing;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
/* DP input has DSC, HDMI FRL output doesn't 
have DSC, remove DSC from output timing */
outputTiming.flags.DSC = 0;
+#endif
if (dc_bandwidth_in_kbps_from_timing() > 
dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
return false;
} else { // DP to HDMI TMDS converter
-- 
2.39.1

[PATCH AUTOSEL 5.15 16/17] drm/amd/display: Properly handle additional cases where DCN is not supported

2023-02-09 Thread Sasha Levin

From: Alex Deucher 

[ Upstream commit 6fc547a5a2ef5ce05b16924106663ab92f8f87a7 ]

There could be boards with DCN listed in IP discovery, but no
display hardware actually wired up.  In this case the vbios
display table will not be populated.  Detect this case and
skip loading DM when we detect it.

v2: Mark DCN as harvested as well so other display checks
elsewhere in the driver are handled properly.

Cc: Aurabindo Pillai 
Reviewed-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a2d9e0af06544..1f7f424331e40 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4428,6 +4428,17 @@ DEVICE_ATTR_WO(s3_debug);
 static int dm_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   struct amdgpu_mode_info *mode_info = >mode_info;
+   struct atom_context *ctx = mode_info->atom_context;
+   int index = GetIndexIntoMasterTable(DATA, Object_Header);
+   u16 data_offset;
+
+   /* if there is no object header, skip DM */
+   if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
_offset)) {
+   adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
+   dev_info(adev->dev, "No object header, skipping DM\n");
+   return -ENOENT;
+   }
 
switch (adev->asic_type) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
-- 
2.39.0

[PATCH AUTOSEL 6.1 35/38] drm/amd/display: Properly handle additional cases where DCN is not supported

2023-02-09 Thread Sasha Levin

From: Alex Deucher 

[ Upstream commit 6fc547a5a2ef5ce05b16924106663ab92f8f87a7 ]

There could be boards with DCN listed in IP discovery, but no
display hardware actually wired up.  In this case the vbios
display table will not be populated.  Detect this case and
skip loading DM when we detect it.

v2: Mark DCN as harvested as well so other display checks
elsewhere in the driver are handled properly.

Cc: Aurabindo Pillai 
Reviewed-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 85bd1f18259c7..c92aaf5c36ef5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4512,6 +4512,17 @@ DEVICE_ATTR_WO(s3_debug);
 static int dm_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   struct amdgpu_mode_info *mode_info = >mode_info;
+   struct atom_context *ctx = mode_info->atom_context;
+   int index = GetIndexIntoMasterTable(DATA, Object_Header);
+   u16 data_offset;
+
+   /* if there is no object header, skip DM */
+   if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
_offset)) {
+   adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
+   dev_info(adev->dev, "No object header, skipping DM\n");
+   return -ENOENT;
+   }
 
switch (adev->asic_type) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
-- 
2.39.0

[PATCH AUTOSEL 6.1 34/38] drm/amdgpu: Enable vclk dclk node for gc11.0.3

2023-02-09 Thread Sasha Levin

From: Yiqing Yao 

[ Upstream commit ac7170082c0e140663f0853d3de733a5341ce7b0 ]

These sysfs nodes are tested supported, so enable them.

Signed-off-by: Yiqing Yao 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 236657eece477..a9170360d7e85 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2007,14 +2007,16 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
  gc_ver == IP_VERSION(10, 3, 0) ||
  gc_ver == IP_VERSION(10, 1, 2) ||
  gc_ver == IP_VERSION(11, 0, 0) ||
- gc_ver == IP_VERSION(11, 0, 2)))
+ gc_ver == IP_VERSION(11, 0, 2) ||
+ gc_ver == IP_VERSION(11, 0, 3)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
  gc_ver == IP_VERSION(10, 3, 0) ||
  gc_ver == IP_VERSION(10, 1, 2) ||
  gc_ver == IP_VERSION(11, 0, 0) ||
- gc_ver == IP_VERSION(11, 0, 2)))
+ gc_ver == IP_VERSION(11, 0, 2) ||
+ gc_ver == IP_VERSION(11, 0, 3)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == 
-EOPNOTSUPP)
-- 
2.39.0

[PATCH AUTOSEL 6.1 33/38] drm/amdgpu: enable HDP SD for gfx 11.0.3

2023-02-09 Thread Sasha Levin

From: Evan Quan 

[ Upstream commit bb25849c0fa550b26cecc9c476c519a927c66898 ]

Enable HDP clock gating control for gfx 11.0.3.

Signed-off-by: Evan Quan 
Reviewed-by: Feifei Xu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 9bc9852b9cda9..230e15fed755c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -643,7 +643,8 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_REPEATER_FGCG |
-   AMD_CG_SUPPORT_GFX_MGCG;
+   AMD_CG_SUPPORT_GFX_MGCG |
+   AMD_CG_SUPPORT_HDP_SD;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
-- 
2.39.0

[PATCH AUTOSEL 6.1 32/38] drm/amd/display: Reset DMUB mailbox SW state after HW reset

2023-02-09 Thread Sasha Levin

From: Nicholas Kazlauskas 

[ Upstream commit 154711aa5759ef9b45903124fa813c4c29ee681c ]

[Why]
Otherwise we can be out of sync with what's in the hardware, leading
to us rerunning every command that's presently in the ringbuffer.

[How]
Reset software state for the mailboxes in hw_reset callback.
This is already done as part of the mailbox init in hw_init, but we
do need to remember to reset the last cached wptr value as well here.

Reviewed-by: Hansen Dsouza 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 4a122925c3ae9..92c18bfb98b3b 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
if (dmub->hw_funcs.reset)
dmub->hw_funcs.reset(dmub);
 
+   /* reset the cache of the last wptr as well now that hw is reset */
+   dmub->inbox1_last_wptr = 0;
+
cw0.offset.quad_part = inst_fb->gpu_addr;
cw0.region.base = DMUB_CW0_BASE;
cw0.region.top = cw0.region.base + inst_fb->size - 1;
@@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
if (dmub->hw_funcs.reset)
dmub->hw_funcs.reset(dmub);
 
+   /* mailboxes have been reset in hw, so reset the sw state as well */
+   dmub->inbox1_last_wptr = 0;
+   dmub->inbox1_rb.wrpt = 0;
+   dmub->inbox1_rb.rptr = 0;
+   dmub->outbox0_rb.wrpt = 0;
+   dmub->outbox0_rb.rptr = 0;
+   dmub->outbox1_rb.wrpt = 0;
+   dmub->outbox1_rb.rptr = 0;
+
dmub->hw_init = false;
 
return DMUB_STATUS_OK;
-- 
2.39.0

[PATCH AUTOSEL 6.1 31/38] drm/amd/display: Unassign does_plane_fit_in_mall function from dcn3.2

2023-02-09 Thread Sasha Levin

From: George Shen 

[ Upstream commit 275d8a1db261a1272a818d40ebc61b3b865b60e5 ]

[Why]
The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics.
Using it with dcn3.2 can result in undefined behaviour.

[How]
Assign the function pointer to NULL.

Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: George Shen 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 45a949ba6f3f3..7b7f0e6b2a2ff 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -94,7 +94,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = dcn10_calc_vupdate_position,
.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
-   .does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall,
+   .does_plane_fit_in_mall = NULL,
.set_backlight_level = dcn21_set_backlight_level,
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
.hardware_release = dcn30_hardware_release,
-- 
2.39.0

[PATCH AUTOSEL 6.1 30/38] drm/amd/display: Adjust downscaling limits for dcn314

2023-02-09 Thread Sasha Levin

From: Daniel Miess 

[ Upstream commit dd2db2dc4bd298f33dea50c80c3c11bee4e3b0a4 ]

[Why]
Lower max_downscale_ratio and ARGB888 downscale factor
to prevent cases where underflow may occur on dcn314

[How]
Set max_downscale_ratio to 400 and ARGB downscale factor
to 250 for dcn314

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Alex Hung 
Signed-off-by: Daniel Miess 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 9066c511a0529..c80c8c8f51e97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -871,8 +871,9 @@ static const struct dc_plane_cap plane_cap = {
},
 
// 6:1 downscaling ratio: 1000/6 = 166.666
+   // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 
playback: 1000/4 = 250
.max_downscale_factor = {
-   .argb = 167,
+   .argb = 250,
.nv12 = 167,
.fp16 = 167
},
@@ -1755,7 +1756,7 @@ static bool dcn314_resource_construct(
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
-   dc->caps.max_downscale_ratio = 600;
+   dc->caps.max_downscale_ratio = 400;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.i2c_speed_in_khz_hdcp = 100;
dc->caps.max_cursor_size = 256;
-- 
2.39.0

[PATCH AUTOSEL 6.1 29/38] drm/amd/display: Add missing brackets in calculation

2023-02-09 Thread Sasha Levin

From: Daniel Miess 

[ Upstream commit ea062fd28f922cb118bfb33229f405b81aff7781 ]

[Why]
Brackets missing in the calculation for MIN_DST_Y_NEXT_START

[How]
Add missing brackets for this calculation

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Alex Hung 
Signed-off-by: Daniel Miess 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 0d12fd079cd61..3afd3c80e6da8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -3184,7 +3184,7 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
} else {
v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - 
v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k];
}
-   v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / 
(double)v->HTotal[k] / v->PixelClock[k], 1.0) / 4.0;
+   v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / 
((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + 
v->VReadyOffsetPix[k]) / v->HTotal[k])
<= (isInterlaceTiming ?
dml_floor((v->VTotal[k] - 
v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
-- 
2.39.0

Re: [PATCH] drm/amdgpu/display: remove duplicate include header in link_dpms.c

2023-02-09 Thread Jani Nikula

On Thu, 09 Feb 2023,  wrote:
> From: Ye Xingchen 
>
> link_hwss.h is included more than once.

You've got U+00A0 non-breaking space in the subject line.

BR,
Jani.

>
> Signed-off-by: Ye Xingchen 
> ---
>  drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c 
> b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> index 9cdfa7f7dc77..0c26b3589608 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> @@ -51,7 +51,6 @@
>  #include "link_enc_cfg.h"
>  #include "resource.h"
>  #include "dsc.h"
> -#include "link_hwss.h"
>  #include "dccg.h"
>  #include "clk_mgr.h"
>  #include "atomfirmware.h"

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH 3/3] drm/connector: Deprecate split for BT.2020 in drm_colorspace enum

2023-02-09 Thread Pekka Paalanen

On Wed, 8 Feb 2023 16:49:31 +0200
Ville Syrjälä  wrote:

> On Wed, Feb 08, 2023 at 11:18:42AM +0200, Pekka Paalanen wrote:
> > On Fri, 3 Feb 2023 16:02:51 +0200
> > Ville Syrjälä  wrote:
> >   
> > > On Fri, Feb 03, 2023 at 02:52:50PM +0100, Sebastian Wick wrote:  
> > > > On Fri, Feb 3, 2023 at 2:35 PM Ville Syrjälä
> > > >  wrote:
> > > > >
> > > > > On Fri, Feb 03, 2023 at 01:59:07PM +0100, Sebastian Wick wrote:
> > > > > > On Fri, Feb 3, 2023 at 11:40 AM Ville Syrjälä
> > > > > >  wrote:
> > > > > > >
> > > > > > > On Fri, Feb 03, 2023 at 02:07:44AM +, Joshua Ashton wrote:
> > > > > > > > Userspace has no way of controlling or knowing the pixel 
> > > > > > > > encoding
> > > > > > > > currently, so there is no way for it to ever get the right 
> > > > > > > > values here.
> > > > > > >
> > > > > > > That applies to a lot of the other values as well (they are
> > > > > > > explicitly RGB or YCC). The idea was that this property sets the
> > > > > > > infoframe/MSA/SDP value exactly, and other properties should be
> > > > > > > added to for use userspace to control the pixel 
> > > > > > > encoding/colorspace
> > > > > > > conversion(if desired, or userspace just makes sure to
> > > > > > > directly feed in correct kind of data).
> > > > > >
> > > > > > I'm all for getting userspace control over pixel encoding but even
> > > > > > then the kernel always knows which pixel encoding is selected and
> > > > > > which InfoFrame has to be sent. Is there a reason why userspace 
> > > > > > would
> > > > > > want to control the variant explicitly to the wrong value?
> > > > >
> > > > > What do you mean wrong value? Userspace sets it based on what
> > > > > kind of data it has generated (or asked the display hardware
> > > > > to generate if/when we get explicit control over that part).
> > > > 
> > > > Wrong in the sense of sending the YCC variant when the pixel encoding
> > > > is RGB for example.
> > > > 
> > > > Maybe I'm missing something here but my assumption is that the kernel
> > > > always has to know the pixel encoding anyway. The color pipeline also
> > > > assumes that the pixel values are RGB. User space might be able to
> > > > generate YCC content but for subsampling etc the pixel encoding still
> > > > has to be explicitly set.
> > > 
> > > The kernel doesn't really know much atm. In theory you can just
> > > configure the thing to do a straight passthough and put anything you
> > > want into your pixels.  
> > 
> > But it's impossible to use a YCbCr framebuffer and have that *not*
> > converted to RGB for the KMS color pipeline even if userspace wanted it
> > to be strictly pass-through, only to be converted again to YCbCr for
> > the cable, is it not?
> > 
> > Even more so with 4:2:0.
> > 
> > How could it be possible to stop the driver from doing those two
> > YUV-to-RGB and RGB-to-YCbCr conversions at the beginning and at the end
> > of the KMS color pipeline?  
> 
> You can stop the conversion at the start of the pipeline by
> using a "RGB" framebuffer. At the end of the pipe it's not
> possible with the current props.

But there is no such thing as a 4:2:0 sub-sampled RGB framebuffer to be
abused for YUV content. It would be possible for some kind of xYUV
4:4:4 content though, but then the pipeline wouldn't work.

Joshua had the excellent point that disabling the conversion at the end
of the pipeline is not possible for a non-RGB output signal, period.
The KMS color pipeline is defined in terms of RGB channels, that's the
only(?) way alpha-blending could work, and the LUT-like elements cannot
handle negative values.

On one hand I very much agree that the definition of "Broadcast RGB"
property was a mistake by combining pixel operations with infoframe
settings. OTOH, since the pipeline end conversion is today chosen by
the driver, then the KMS color pipeline output must be known to the
driver so that the driver can pick the right conversion. That's what
"Broadcast RGB" did: it assumed the pipeline produces full range
values, so that it is able to insert the right conversion and the right
infoframe data. It rules out possible use cases, but the infoframe
matches.

As for the pipe-end RGB-to-YCbCr conversion, the situation is partly
similar. There is the assumption that the pipeline produces RGB model
values. However, this assumption is likely never going to change,
because the pipeline is inherently RGB, always.

A better question is, does it need other assumptions as well?

Quantization range?

RGB (electrical encoding) transfer function?

Most RGB-to-YCbCr conversions are just a matrix applied to the
electrical RGB values, but not all. Particularly the constant luminance
encoding requires optical, not electrical, RGB values, and it also
needs the transfer function since it emits electrical values. I haven't
looked if e.g. BT.2100 has more cases making the RGB-to-something
conversion complex.

Even having a doubt about that really does point towards

Re: [regression][6.0] After commit b261509952bc19d1012cf732f853659be6ebc61e I see WARNING message at drivers/gpu/drm/drm_modeset_lock.c:276 drm_modeset_drop_locks+0x63/0x70

2023-02-09 Thread Mikhail Gavrilov

Harry, please don't ignore me.
This issue still happens in 6.1 and 6.2
Leo you are the author of the problematic commit please don't stand aside.
Really nobody is interested in clean logs without warnings and errors?
I am 100% sure that reverting commit
b261509952bc19d1012cf732f853659be6ebc61e will stop these warnings. I
also attached fresh logs from 6.2.0-0.rc6.
6.2-rc7 I started to build without commit
b261509952bc19d1012cf732f853659be6ebc61e to avoid these warnings.


On Thu, Oct 13, 2022 at 6:36 PM Mikhail Gavrilov
>
> Hi!
> I bisected an issue of the 6.0 kernel which started happening after
> 6.0-rc7 on all my machines.
>
> Backtrace of this issue looks like as:
>
> [ 2807.339439] [ cut here ]
> [ 2807.339445] WARNING: CPU: 11 PID: 2061 at
> drivers/gpu/drm/drm_modeset_lock.c:276
> drm_modeset_drop_locks+0x63/0x70
> [ 2807.339453] Modules linked in: tls uinput rfcomm snd_seq_dummy
> snd_hrtimer nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast
> nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet
> nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat nf_nat
> nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip_set nf_tables nfnetlink
> qrtr bnep intel_rapl_msr intel_rapl_common snd_sof_amd_renoir
> snd_sof_amd_acp snd_sof_pci snd_hda_codec_realtek sunrpc snd_sof
> snd_hda_codec_hdmi snd_hda_codec_generic snd_sof_utils snd_hda_intel
> snd_intel_dspcfg mt7921e snd_intel_sdw_acpi binfmt_misc snd_soc_core
> mt7921_common snd_hda_codec snd_compress vfat ac97_bus edac_mce_amd
> mt76_connac_lib snd_pcm_dmaengine fat snd_hda_core snd_rpl_pci_acp6x
> snd_pci_acp6x mt76 btusb snd_hwdep kvm_amd btrtl snd_seq btbcm
> mac80211 snd_seq_device kvm btintel btmtk libarc4 snd_pcm
> snd_pci_acp5x bluetooth snd_timer snd_rn_pci_acp3x irqbypass
> snd_acp_config snd_soc_acpi cfg80211 rapl snd joydev pcspkr
> asus_nb_wmi wmi_bmof
> [ 2807.339519]  snd_pci_acp3x soundcore i2c_piix4 k10temp amd_pmc
> asus_wireless zram amdgpu drm_ttm_helper ttm hid_asus asus_wmi
> crct10dif_pclmul iommu_v2 crc32_pclmul ledtrig_audio crc32c_intel
> gpu_sched sparse_keymap platform_profile hid_multitouch
> polyval_clmulni nvme ucsi_acpi drm_buddy polyval_generic
> drm_display_helper ghash_clmulni_intel serio_raw nvme_core ccp
> typec_ucsi rfkill sp5100_tco r8169 cec nvme_common typec wmi video
> i2c_hid_acpi i2c_hid ip6_tables ip_tables fuse
> [ 2807.339540] Unloaded tainted modules: acpi_cpufreq():1
> acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1
> acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1 acpi_cpufreq():1
> amd64_edac():1 acpi_cpufreq():1 acpi_cpufreq():1 amd64_edac():1
> amd64_edac():1 acpi_cpufreq():1 pcc_cpufreq():1 fjes():1
> amd64_edac():1 acpi_cpufreq():1 amd64_edac():1 acpi_cpufreq():1
> fjes():1 pcc_cpufreq():1 amd64_edac():1 acpi_cpufreq():1 fjes():1
> amd64_edac():1 acpi_cpufreq():1 pcc_cpufreq():1 amd64_edac():1
> fjes():1 acpi_cpufreq():1 acpi_cpufreq():1 pcc_cpufreq():1
> amd64_edac():1 fjes():1 acpi_cpufreq():1 amd64_edac():1
> pcc_cpufreq():1 acpi_cpufreq():1 fjes():1 amd64_edac():1
> pcc_cpufreq():1 pcc_cpufreq():1 amd64_edac():1 acpi_cpufreq():1
> fjes():1 pcc_cpufreq():1 amd64_edac():1 acpi_cpufreq():1
> acpi_cpufreq():1 amd64_edac():1 pcc_cpufreq():1 fjes():1
> acpi_cpufreq():1 amd64_edac():1 pcc_cpufreq():1 amd64_edac():1
> acpi_cpufreq():1 fjes():1 pcc_cpufreq():1 acpi_cpufreq():1
> pcc_cpufreq():1 fjes():1
> [ 2807.339579]  acpi_cpufreq():1 fjes():1 pcc_cpufreq():1
> acpi_cpufreq():1 pcc_cpufreq():1 acpi_cpufreq():1 fjes():1
> acpi_cpufreq():1 pcc_cpufreq():1 fjes():1 pcc_cpufreq():1
> acpi_cpufreq():1 fjes():1 acpi_cpufreq():1 fjes():1 fjes():1 fjes():1
> fjes():1 fjes():1 fjes():1 fjes():1 fjes():1 fjes():1 fjes():1
> fjes():1 fjes():1 fjes():1 fjes():1
> [ 2807.339596] CPU: 11 PID: 2061 Comm: gnome-shell Tainted: GW
>L 6.0.0-rc4-07-cb0eca01ad9756e853efec3301203c2b5b45aa9f+ #16
> [ 2807.339598] Hardware name: ASUSTeK COMPUTER INC. ROG Strix
> G513QY_G513QY/G513QY, BIOS G513QY.318 03/29/2022
> [ 2807.339600] RIP: 0010:drm_modeset_drop_locks+0x63/0x70
> [ 2807.339602] Code: 42 08 48 89 10 48 89 1b 48 8d bb 50 ff ff ff 48
> 89 5b 08 e8 3f 41 55 00 48 8b 45 78 49 39 c4 75 c6 5b 5d 41 5c c3 cc
> cc cc cc <0f> 0b eb ac 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 55
> 41 54
> [ 2807.339604] RSP: 0018:b6ad46e07b80 EFLAGS: 00010282
> [ 2807.339606] RAX: 0001 RBX:  RCX: 
> 0002
> [ 2807.339607] RDX: 0001 RSI: a6a118b1 RDI: 
> b6ad46e07c00
> [ 2807.339608] RBP: b6ad46e07c00 R08:  R09: 
> 
> [ 2807.339609] R10:  R11: 0001 R12: 
> 
> [ 2807.339610] R13: 9801ca24bb00 R14: 9801ca24bb00 R15: 
> 
> [ 2807.339611] FS:  7f57445b0600() GS:981198e0()
> knlGS:
> [ 2807.339613] CS:  0010 DS:  ES:  CR0: 80050033
> [ 2807.339614]

[PATCH] drm/amdgpu/display: remove duplicate include header in link_dpms.c

2023-02-09 Thread ye.xingchen

From: Ye Xingchen 

link_hwss.h is included more than once.

Signed-off-by: Ye Xingchen 
---
 drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c 
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 9cdfa7f7dc77..0c26b3589608 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -51,7 +51,6 @@
 #include "link_enc_cfg.h"
 #include "resource.h"
 #include "dsc.h"
-#include "link_hwss.h"
 #include "dccg.h"
 #include "clk_mgr.h"
 #include "atomfirmware.h"
-- 
2.25.1

Re: [PATCH 2/2] drm/amd/display: minor cleanup of vm_setup

2023-02-09 Thread Christian König


Am 09.02.23 um 05:46 schrieb Alex Deucher:

Use fb_start/end for consistency with gmc code for non-
XGMI systems, they are equivalent to vram_start/end.

Signed-off-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8ba4a57d8e6f..bf06875e6a01 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1191,7 +1191,7 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
  
  	/* AGP aperture is disabled */

if (agp_bot == agp_top) {
-   logical_addr_low  = adev->gmc.vram_start >> 18;
+   logical_addr_low = adev->gmc.fb_start >> 18;
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which
@@ -1201,9 +1201,9 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
 */
logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
else
-   logical_addr_high = adev->gmc.vram_end >> 18;
+   logical_addr_high = adev->gmc.fb_end >> 18;
} else {
-   logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) 
>> 18;
+   logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) 
>> 18;
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which

Re: [PATCH 1/2] drm/amdgpu/gmc11: fix system aperture set when AGP is enabled

2023-02-09 Thread Christian König


Am 09.02.23 um 05:46 schrieb Alex Deucher:

Need to cover both FB and AGP apertures.

Fixes: c6eafee038ed ("Revert "Revert "drm/amdgpu/gmc11: enable AGP aperture""")
Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c  | 4 ++--
  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c   | 4 ++--
  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 4 ++--
  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 4 ++--
  4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
index 7c069010ca9a..be0d0f47415e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
@@ -159,9 +159,9 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
  
  	/* Program the system aperture low logical page number. */

WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
  
  	/* Set default page address. */

value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index 923fc09bc8fc..164948c50ac3 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -184,9 +184,9 @@ static void mmhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
  
  	/* Program the system aperture low logical page number. */

WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
  
  	/* Set default page address. */

value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
index c8d478f2afdc..26509b6b8c24 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
@@ -183,9 +183,9 @@ static void mmhub_v3_0_1_init_system_aperture_regs(struct 
amdgpu_device *adev)
 */
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
  
  	/* Set default page address. */

value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
index 51580302ec42..26abbc6a47ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
@@ -175,9 +175,9 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct 
amdgpu_device *adev)
 */
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.fb_start, adev->gmc.agp_start) >> 
18);
WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
}
  
  	/* Set default page address. */

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