[PATCH v3] drm/amdgpu: Fix missing comment for mb() in 'amdgpu_device_aper_access'
This patch adds the missing code comment for memory barrier
WARNING: memory barrier without comment
+ mb();
WARNING: memory barrier without comment
+ mb();
Cc: Guchun Chen
Cc: Christian König
Cc: Alex Deucher
Cc: "Pan, Xinhui"
Signed-off-by: Srinivasan Shanmugam
---
v3:
Corrected title message
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4f818f13dc9d..bb65e12ed027 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -305,10 +305,17 @@ size_t amdgpu_device_aper_access(struct amdgpu_device
*adev, loff_t pos,
if (write) {
memcpy_toio(addr, buf, count);
+ /* Make sure contents of system memory are
copied/flushed
+* without messing up order of writes to PCI device I/O
memory
+*/
mb();
amdgpu_device_flush_hdp(adev, NULL);
} else {
amdgpu_device_invalidate_hdp(adev, NULL);
+ /* Make sure contents of system memory
drained/invalidated
+* before copying contents from PCI device I/O memory
+* to system memory
+*/
mb();
memcpy_fromio(buf, addr, count);
}
--
2.25.1
[PATCH v2] drm/amdgpu: Fix missing comment for wmb() in 'amdgpu_device_aper_access'
This patch adds the missing code comment for memory barrier
WARNING: memory barrier without comment
+ mb();
WARNING: memory barrier without comment
+ mb();
Cc: Guchun Chen
Cc: Christian König
Cc: Alex Deucher
Cc: "Pan, Xinhui"
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Fixed indendation issues.
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4f818f13dc9d..bb65e12ed027 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -305,10 +305,17 @@ size_t amdgpu_device_aper_access(struct amdgpu_device
*adev, loff_t pos,
if (write) {
memcpy_toio(addr, buf, count);
+ /* Make sure contents of system memory are
copied/flushed
+* without messing up order of writes to PCI device I/O
memory
+*/
mb();
amdgpu_device_flush_hdp(adev, NULL);
} else {
amdgpu_device_invalidate_hdp(adev, NULL);
+ /* Make sure contents of system memory
drained/invalidated
+* before copying contents from PCI device I/O memory
+* to system memory
+*/
mb();
memcpy_fromio(buf, addr, count);
}
--
2.25.1
[PATCH] drm/amdgpu: Fix missing comment for wmb() in 'amdgpu_device_aper_access'
This patch adds the missing code comment for memory barrier
WARNING: memory barrier without comment
+ mb();
WARNING: memory barrier without comment
+ mb();
Cc: Guchun Chen
Cc: Christian König
Cc: Alex Deucher
Cc: "Pan, Xinhui"
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4f818f13dc9d..a1c214f86e4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -305,10 +305,17 @@ size_t amdgpu_device_aper_access(struct amdgpu_device
*adev, loff_t pos,
if (write) {
memcpy_toio(addr, buf, count);
+ /* Make sure contents of system memory are copied/flushed
+ * without messing up order of writes to PCI device I/O
memory
+ */
mb();
amdgpu_device_flush_hdp(adev, NULL);
} else {
amdgpu_device_invalidate_hdp(adev, NULL);
+ /* Make sure contents of system memory
drained/invalidated
+ * before copying contents from PCI device I/O memory
+ * to system memory
+ */
mb();
memcpy_fromio(buf, addr, count);
}
--
2.25.1
[PATCH] drm/amdgpu: disable mcbp if parameter zero is set
From: Jiadong Zhu
The parameter amdgpu_mcbp shall have priority against the default value
calculated from the chip version.
User could disable mcbp by setting the parameter mcbp as zero.
v2: do not trigger preemption in sw ring muxer when mcbp is disabled.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7314529553f6..615669dcabc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3699,10 +3699,11 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device
*adev)
{
if (amdgpu_mcbp == 1)
adev->gfx.mcbp = true;
-
- if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
- (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
- adev->gfx.num_gfx_rings)
+ else if (amdgpu_mcbp == 0)
+ adev->gfx.mcbp = false;
+ else if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
+(adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
+adev->gfx.num_gfx_rings)
adev->gfx.mcbp = true;
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
index b779ee4bbaa7..e1ee1c7117fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -397,7 +397,7 @@ void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring)
struct amdgpu_ring_mux *mux = >gfx.muxer;
WARN_ON(!ring->is_sw_ring);
- if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) {
+ if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) {
if (amdgpu_mcbp_scan(mux) > 0)
amdgpu_mcbp_trigger_preempt(mux);
return;
--
2.25.1
Re: drm/amdkfd: Use memdup_user() rather than duplicating its
Hello Felix, I appreciate the code review. Will correct the typo (seems to have appeared during patch creation following compilation). Shortly as the compilation is successful, V2 will be sent. -Atul On 8/8/23 15:47, Felix Kuehling wrote: On 2023-08-08 16:57, Atul Raut wrote: To prevent its redundant implementation and streamline code, use memdup_user. This fixes warnings reported by Coccinelle: ./drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:2811:13-20: WARNING opportunity for memdup_user Signed-off-by: Atul Raut --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 2df153828ff4..51740e007e89 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2808,12 +2808,9 @@ static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array if (!usr_queue_id_array) return NULL; - queue_ids = kzalloc(array_size, GFP_KERNEL); - if (!queue_ids) - return ERR_PTR(-ENOMEM); - - if (copy_from_user(queue_ids, usr_queue_id_array, array_size)) - return ERR_PTR(-EFAULT); + queue_ids = memdup_user(usr_queue_id_array, array_size); + if (IS_ERR(Iqueue_ids)) You have a typo in the variable name here. Did you at least compile-test the patch? + return ERR_PTR(queue_ids); I think it should just return queue_ids here. That's already an ERR_PTR in case of errors. So you don't even need the "if". Just this should do the job: return memdup_user(usr_queue_id_array, array_size); The error checking is done by the caller. Regards, Felix return queue_ids; }
[PATCH] drm/amd/display: dmub_replay: don't use kernel-doc markers
These functions don't use kernel-doc notation for comments so
don't begin each comment block with the "/**" kernel-doc marker.
This prevents a bunch of kernel-doc warnings:
dmub_replay.c:37: warning: This comment starts with '/**', but isn't a
kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
dmub_replay.c:37: warning: missing initial short description on line:
* Get Replay state from firmware.
dmub_replay.c:66: warning: This comment starts with '/**', but isn't a
kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
dmub_replay.c:66: warning: missing initial short description on line:
* Enable/Disable Replay.
dmub_replay.c:116: warning: This comment starts with '/**', but isn't a
kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
dmub_replay.c:116: warning: missing initial short description on line:
* Set REPLAY power optimization flags.
dmub_replay.c:134: warning: This comment starts with '/**', but isn't a
kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
dmub_replay.c:134: warning: missing initial short description on line:
* Setup Replay by programming phy registers and sending replay hw context
values to firmware.
and 10 more similar warnings.
Fixes: c7ddc0a800bc ("drm/amd/display: Add Functions to enable Freesync Panel
Replay")
Signed-off-by: Randy Dunlap
Reported-by: kernel test robot
Link: lore.kernel.org/r/202308081459.us5rlyay-...@intel.com
Cc: Bhawanpreet Lakha
Cc: Harry Wentland
Cc: Alex Deucher
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-gfx@lists.freedesktop.org
Cc: Christian König
Cc: "Pan, Xinhui"
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 18 ++---
1 file changed, 9 insertions(+), 9 deletions(-)
diff -- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -33,7 +33,7 @@
#define MAX_PIPES 6
-/**
+/*
* Get Replay state from firmware.
*/
static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state
*state, uint8_t panel_inst)
@@ -62,7 +62,7 @@ static void dmub_replay_get_state(struct
}
}
-/**
+/*
* Enable/Disable Replay.
*/
static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool
wait, uint8_t panel_inst)
@@ -112,7 +112,7 @@ static void dmub_replay_enable(struct dm
}
-/**
+/*
* Set REPLAY power optimization flags.
*/
static void dmub_replay_set_power_opt(struct dmub_replay *dmub, unsigned int
power_opt, uint8_t panel_inst)
@@ -130,7 +130,7 @@ static void dmub_replay_set_power_opt(st
dm_execute_dmub_cmd(dc, , DM_DMUB_WAIT_TYPE_WAIT);
}
-/**
+/*
* Setup Replay by programming phy registers and sending replay hw context
values to firmware.
*/
static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
@@ -215,7 +215,7 @@ static bool dmub_replay_copy_settings(st
return true;
}
-/**
+/*
* Set coasting vtotal.
*/
static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
@@ -234,7 +234,7 @@ static void dmub_replay_set_coasting_vto
dm_execute_dmub_cmd(dc, , DM_DMUB_WAIT_TYPE_WAIT);
}
-/**
+/*
* Get Replay residency from firmware.
*/
static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,
@@ -267,7 +267,7 @@ static const struct dmub_replay_funcs re
.replay_residency = dmub_replay_residency,
};
-/**
+/*
* Construct Replay object.
*/
static void dmub_replay_construct(struct dmub_replay *replay, struct
dc_context *ctx)
@@ -276,7 +276,7 @@ static void dmub_replay_construct(struct
replay->funcs = _funcs;
}
-/**
+/*
* Allocate and initialize Replay object.
*/
struct dmub_replay *dmub_replay_create(struct dc_context *ctx)
@@ -293,7 +293,7 @@ struct dmub_replay *dmub_replay_create(s
return replay;
}
-/**
+/*
* Deallocate Replay object.
*/
void dmub_replay_destroy(struct dmub_replay **dmub)
Re: drm/amdkfd: Use memdup_user() rather than duplicating its
On 2023-08-08 16:57, Atul Raut wrote: To prevent its redundant implementation and streamline code, use memdup_user. This fixes warnings reported by Coccinelle: ./drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:2811:13-20: WARNING opportunity for memdup_user Signed-off-by: Atul Raut --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 2df153828ff4..51740e007e89 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2808,12 +2808,9 @@ static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array if (!usr_queue_id_array) return NULL; - queue_ids = kzalloc(array_size, GFP_KERNEL); - if (!queue_ids) - return ERR_PTR(-ENOMEM); - - if (copy_from_user(queue_ids, usr_queue_id_array, array_size)) - return ERR_PTR(-EFAULT); + queue_ids = memdup_user(usr_queue_id_array, array_size); + if (IS_ERR(Iqueue_ids)) You have a typo in the variable name here. Did you at least compile-test the patch? + return ERR_PTR(queue_ids); I think it should just return queue_ids here. That's already an ERR_PTR in case of errors. So you don't even need the "if". Just this should do the job: return memdup_user(usr_queue_id_array, array_size); The error checking is done by the caller. Regards, Felix return queue_ids; }
drm/amdkfd: Use memdup_user() rather than duplicating its
To prevent its redundant implementation and streamline code, use memdup_user. This fixes warnings reported by Coccinelle: ./drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:2811:13-20: WARNING opportunity for memdup_user Signed-off-by: Atul Raut --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 2df153828ff4..51740e007e89 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2808,12 +2808,9 @@ static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array if (!usr_queue_id_array) return NULL; - queue_ids = kzalloc(array_size, GFP_KERNEL); - if (!queue_ids) - return ERR_PTR(-ENOMEM); - - if (copy_from_user(queue_ids, usr_queue_id_array, array_size)) - return ERR_PTR(-EFAULT); + queue_ids = memdup_user(usr_queue_id_array, array_size); + if (IS_ERR(Iqueue_ids)) + return ERR_PTR(queue_ids); return queue_ids; } -- 2.34.1
[PATCH 2/2] drm/amdgpu: Use *REG32_RLC in gfx_v9_4_3.c
gfx_v9_4_3_xcc_set_compute_eop_interrupt_state should use *REG32_RLC
so CP_ME1_PIPE0_INT_CNTL registers can be accessed with SRIOV.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 370660b2f843..8b779a103400 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2742,16 +2742,16 @@ static void
gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
- mec_int_cntl = RREG32(mec_int_cntl_reg);
+ mec_int_cntl = RREG32_RLC(mec_int_cntl_reg, xcc_id);
mec_int_cntl = REG_SET_FIELD(mec_int_cntl,
CP_ME1_PIPE0_INT_CNTL,
TIME_STAMP_INT_ENABLE, 0);
- WREG32(mec_int_cntl_reg, mec_int_cntl);
+ WREG32_RLC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
break;
case AMDGPU_IRQ_STATE_ENABLE:
- mec_int_cntl = RREG32(mec_int_cntl_reg);
+ mec_int_cntl = RREG32_RLC(mec_int_cntl_reg, xcc_id);
mec_int_cntl = REG_SET_FIELD(mec_int_cntl,
CP_ME1_PIPE0_INT_CNTL,
TIME_STAMP_INT_ENABLE, 1);
- WREG32(mec_int_cntl_reg, mec_int_cntl);
+ WREG32_RLC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
break;
default:
break;
--
2.34.1
[PATCH 1/2] drm/amdgpu: Add xcc instance parameter to *REG32_RLC
WREG32/RREG32_RLC should specify the instance so the correct XCC's RLCG
interface can be used.
Signed-off-by: Victor Lu
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 4 +--
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 25 +++
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 4 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 32 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/soc15.c| 2 +-
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 8 ++---
7 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
index e2fed6edbdd0..4b6007de24ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
@@ -154,11 +154,11 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch(
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
(watch_id * TCP_WATCH_STRIDE)),
- watch_address_high);
+ watch_address_high, 0);
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
(watch_id * TCP_WATCH_STRIDE)),
- watch_address_low);
+ watch_address_low, 0);
return watch_address_cntl;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
index 490c8f5ddb60..218226c10b93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
@@ -300,14 +300,14 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device
*adev, void *mqd,
hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_HQD_AQL_DISPATCH_ID_HI);
for (reg = hqd_base; reg <= hqd_end; reg++)
- WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
+ WREG32_RLC(reg, mqd_hqd[reg - hqd_base], inst);
/* Activate doorbell logic before triggering WPTR poll. */
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_HQD_PQ_DOORBELL_CONTROL),
- data);
+ data, inst);
if (wptr) {
/* Don't read wptr with get_user because the user
@@ -337,26 +337,25 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device
*adev, void *mqd,
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_HQD_PQ_WPTR_LO),
- lower_32_bits(guessed_wptr));
+ lower_32_bits(guessed_wptr), inst);
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_HQD_PQ_WPTR_HI),
- upper_32_bits(guessed_wptr));
+ upper_32_bits(guessed_wptr), inst);
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_HQD_PQ_WPTR_POLL_ADDR),
- lower_32_bits((uintptr_t)wptr));
+ lower_32_bits((uintptr_t)wptr), inst);
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
- upper_32_bits((uintptr_t)wptr));
- WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_PQ_WPTR_POLL_CNTL1),
- (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id,
- queue_id));
+ upper_32_bits((uintptr_t)wptr), inst);
+ WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regCP_PQ_WPTR_POLL_CNTL1),
+ (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id,
queue_id), inst);
}
/* Start the EOP fetcher */
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR),
REG_SET_FIELD(m->cp_hqd_eop_rptr,
-CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
+CP_HQD_EOP_RPTR, INIT_FETCHER, 1), inst);
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
- WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE),
data);
+ WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE),
data, inst);
kgd_gfx_v9_release_queue(adev, inst);
@@ -497,12 +496,12 @@ static uint32_t kgd_gfx_v9_4_3_set_address_watch(
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
regTCP_WATCH0_ADDR_H) +
(watch_id * TCP_WATCH_STRIDE)),
- watch_address_high);
+ watch_address_high, inst);
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
[PATCH 3/3] drm/amdgpu: Add flag to enable indirect RLCG access for gfx v9.4.3
The "rlcg_reg_access_supported" flag is missing. Add it back in. Signed-off-by: Victor Lu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index a8178d871795..8b779a103400 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1096,6 +1096,7 @@ static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); } + adev->gfx.rlc.rlcg_reg_access_supported = true; } static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) -- 2.34.1
[PATCH 2/3] drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait
amdgpu_virt_kiq_reg_write_reg_wait is hardcoded to use MEC engine 0.
Add xcc_inst as a parameter to allow it to use different MEC engines.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 10 +++---
5 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 96857ae7fb5b..105a1fdff2f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -73,9 +73,10 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
uint32_t reg0, uint32_t reg1,
- uint32_t ref, uint32_t mask)
+ uint32_t ref, uint32_t mask,
+ uint32_t xcc_inst)
{
- struct amdgpu_kiq *kiq = >gfx.kiq[0];
+ struct amdgpu_kiq *kiq = >gfx.kiq[xcc_inst];
struct amdgpu_ring *ring = >ring;
signed long r, cnt = 0;
unsigned long flags;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index fabb83e9d9ae..e9eb64e11c9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -330,7 +330,8 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
uint32_t reg0, uint32_t rreg1,
- uint32_t ref, uint32_t mask);
+ uint32_t ref, uint32_t mask,
+ uint32_t xcc_id);
int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index fa87a85e1017..56f50abcf9e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -346,7 +346,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
- 1 << vmid);
+ 1 << vmid, 0);
up_read(>reset_domain->sem);
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index e3b76fd28d15..3f6626f8c298 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -303,7 +303,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
- 1 << vmid);
+ 1 << vmid, 0);
return;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 11bad5475b31..5b040011bb92 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -815,7 +815,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
{
bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
const unsigned int eng = 17;
- u32 j, inv_req, inv_req2, tmp;
+ u32 j, inv_req, inv_req2, tmp, inst;
struct amdgpu_vmhub *hub;
BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
@@ -844,14 +844,18 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
/* This is necessary for a HW workaround under SRIOV as well
* as GFXOFF under bare metal
*/
- if (adev->gfx.kiq[0].ring.sched.ready &&
+ if (vmhub >= AMDGPU_MMHUB0(0))
+ inst = vmhub - AMDGPU_MMHUB0(0);
+ else
+ inst = vmhub;
+ if (adev->gfx.kiq[inst].ring.sched.ready &&
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
down_read_trylock(>reset_domain->sem)) {
uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
- 1 << vmid);
+
[PATCH 1/3] drm/amdgpu: Add xcc instance parameter to *REG32_SOC15_IP_NO_KIQ
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.
Add inst parameter to them.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 6 +++---
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 880460cd3239..11bad5475b31 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -870,9 +870,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acquire */
if (vmhub >= AMDGPU_MMHUB0(0))
- tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB,
hub->vm_inv_eng0_sem + hub->eng_distance * eng);
+ tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB,
hub->vm_inv_eng0_sem + hub->eng_distance * eng, vmhub - AMDGPU_MMHUB0(0));
else
- tmp = RREG32_SOC15_IP_NO_KIQ(GC,
hub->vm_inv_eng0_sem + hub->eng_distance * eng);
+ tmp = RREG32_SOC15_IP_NO_KIQ(GC,
hub->vm_inv_eng0_sem + hub->eng_distance * eng, vmhub);
if (tmp & 0x1)
break;
udelay(1);
@@ -884,9 +884,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
do {
if (vmhub >= AMDGPU_MMHUB0(0))
- WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req +
hub->eng_distance * eng, inv_req);
+ WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req +
hub->eng_distance * eng, inv_req, vmhub - AMDGPU_MMHUB0(0));
else
- WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req +
hub->eng_distance * eng, inv_req);
+ WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req +
hub->eng_distance * eng, inv_req, vmhub);
/*
* Issue a dummy read to wait for the ACK register to
@@ -900,9 +900,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
for (j = 0; j < adev->usec_timeout; j++) {
if (vmhub >= AMDGPU_MMHUB0(0))
- tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB,
hub->vm_inv_eng0_ack + hub->eng_distance * eng);
+ tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB,
hub->vm_inv_eng0_ack + hub->eng_distance * eng, vmhub - AMDGPU_MMHUB0(0));
else
- tmp = RREG32_SOC15_IP_NO_KIQ(GC,
hub->vm_inv_eng0_ack + hub->eng_distance * eng);
+ tmp = RREG32_SOC15_IP_NO_KIQ(GC,
hub->vm_inv_eng0_ack + hub->eng_distance * eng, vmhub);
if (tmp & (1 << vmid))
break;
udelay(1);
@@ -919,9 +919,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
* write with 0 means semaphore release
*/
if (vmhub >= AMDGPU_MMHUB0(0))
- WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem +
hub->eng_distance * eng, 0);
+ WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem +
hub->eng_distance * eng, 0, vmhub - AMDGPU_MMHUB0(0));
else
- WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem +
hub->eng_distance * eng, 0);
+ WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem +
hub->eng_distance * eng, 0, vmhub);
}
spin_unlock(>gmc.invalidate_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index b99244a53d6d..148eb2603b9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -69,7 +69,7 @@
#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)
-#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg,
AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
+#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg,
AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
+ reg, \
@@ -86,8 +86,8 @@
#define WREG32_SOC15_IP(ip, reg, value) \
__WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
-#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
-__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
+#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \
+__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
Re: [PATCH V2 1/5] drm/amdkfd: ignore crat by default
On 2023-08-07 18:05, Alex Deucher wrote: We are dropping the IOMMUv2 path, so no need to enable this. It's often buggy on consumer platforms anyway. Signed-off-by: Alex Deucher The series is Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 49f40d9f16e86..f5a6f562e2a80 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1543,11 +1543,7 @@ static bool kfd_ignore_crat(void) if (ignore_crat) return true; -#ifndef KFD_SUPPORT_IOMMU_V2 ret = true; -#else - ret = false; -#endif return ret; }
[linux-next:master] BUILD REGRESSION 71cd4fc492ec41e4acd85e98bbf7a13753fc1e03
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 71cd4fc492ec41e4acd85e98bbf7a13753fc1e03 Add linux-next specific
files for 20230808
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202307251531.p8zlftmz-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202308081459.us5rlyay-...@intel.com
Error/Warning: (recently discovered and may have been fixed)
../lib/gcc/loongarch64-linux/12.3.0/plugin/include/config/loongarch/loongarch-opts.h:31:10:
fatal error: loongarch-def.h: No such file or directory
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_replay.c:37: warning: This
comment starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
sound/soc/codecs/aw88261.c:651:7: warning: variable 'ret' is used uninitialized
whenever 'if' condition is false [-Wsometimes-uninitialized]
Unverified Error/Warning (likely false positive, please contact us if
interested):
drivers/gpu/drm/tests/drm_exec_test.c:166 test_prepare_array() error:
uninitialized symbol 'ret'.
drivers/mtd/nand/raw/qcom_nandc.c:2590 qcom_op_cmd_mapping() error:
uninitialized symbol 'ret'.
drivers/mtd/nand/raw/qcom_nandc.c:3017 qcom_check_op() warn: was && intended
here instead of ||?
kernel/futex/waitwake.c:422 futex_wait_multiple_setup() warn: bitwise AND
condition is false here
sh4-linux-gcc: internal compiler error: Segmentation fault signal terminated
program cc1
{standard input}: Warning: end of file not at end of a line; newline inserted
{standard input}:927: Error: pcrel too far
Error/Warning ids grouped by kconfigs:
gcc_recent_errors
|-- alpha-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arc-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arm-allmodconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arm-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arm64-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- csky-randconfig-m041-20230808
| `--
drivers-gpu-drm-tests-drm_exec_test.c-test_prepare_array()-error:uninitialized-symbol-ret-.
|-- i386-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- loongarch-allmodconfig
| `--
lib-gcc-loongarch64-linux-..-plugin-include-config-loongarch-loongarch-opts.h:fatal-error:loongarch-def.h:No-such-file-or-directory
|-- mips-allmodconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- mips-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- parisc-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- powerpc-allmodconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- riscv-allmodconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- riscv-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- riscv-randconfig-m031-20230808
| |--
drivers-gpu-drm-tests-drm_exec_test.c-test_prepare_array()-error:uninitialized-symbol-ret-.
| |--
drivers-mtd-nand-raw-qcom_nandc.c-qcom_check_op()-warn:was-intended-here-instead-of
| |--
drivers-mtd-nand-raw-qcom_nandc.c-qcom_op_cmd_mapping()-error:uninitialized-symbol-ret-.
| `--
kernel-futex-waitwake.c-futex_wait_multiple_setup()-warn:bitwise-AND-condition-is-false-here
|-- s390-allyesconfig
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-dce-dmub_replay.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
[PATCH] drm/radeon: check return value of radeon_ring_lock()
In the unlikely event of radeon_ring_lock() failing, its errno return
value should be processed. This patch checks said return value and
prints a debug message in case of an error.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: 48c0c902e2e6 ("drm/radeon/kms: add support for CP setup on SI")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/radeon/si.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 8d5e4b25609d..df1b2ebc37c2 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3611,6 +3611,10 @@ static int si_cp_start(struct radeon_device *rdev)
for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX;
++i) {
ring = >ring[i];
r = radeon_ring_lock(rdev, ring, 2);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ return r;
+ }
/* clear the compute context state */
radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE,
0));
--
2.25.1
[PATCH] video/hdmi: convert *_infoframe_init() functions to void
Four hdmi_*_infoframe_init() functions that initialize different
types of hdmi infoframes only return the default 0 value, contrary to
their descriptions. Yet these functions are still unnecessarily checked
against possible errors in case of failure.
Remove redundant error checks in calls to following functions:
- hdmi_spd_infoframe_init
- hdmi_audio_infoframe_init
- hdmi_vendor_infoframe_init
- hdmi_drm_infoframe_init
Also, convert these functions to 'void' and fix their descriptions.
Fixes: 2c676f378edb ("[media] hdmi: added unpack and logging functions for
InfoFrames")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/display/drm_hdmi_helper.c | 5 +---
drivers/gpu/drm/drm_edid.c| 5 +---
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ++---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 14 ++
drivers/gpu/drm/radeon/r600_hdmi.c| 6 +---
drivers/gpu/drm/sti/sti_hdmi.c| 6 +---
drivers/gpu/drm/tegra/hdmi.c | 7 +
drivers/gpu/drm/tegra/sor.c | 6 +---
drivers/gpu/drm/vc4/vc4_hdmi.c| 7 +
drivers/video/hdmi.c | 46 ++-
include/linux/hdmi.h | 10 +++
11 files changed, 25 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c
b/drivers/gpu/drm/display/drm_hdmi_helper.c
index faf5e9efa7d3..ce7038a3a183 100644
--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ -27,7 +27,6 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
{
struct drm_connector *connector;
struct hdr_output_metadata *hdr_metadata;
- int err;
if (!frame || !conn_state)
return -EINVAL;
@@ -47,9 +46,7 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
connector->hdr_sink_metadata.hdmi_type1.eotf))
DRM_DEBUG_KMS("Unknown EOTF %d\n",
hdr_metadata->hdmi_metadata_type1.eotf);
- err = hdmi_drm_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_drm_infoframe_init(frame);
frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e0dbd9140726..d4933f215675 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -7235,7 +7235,6 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
*/
bool has_hdmi_infoframe = connector ?
connector->display_info.has_hdmi_infoframe : false;
- int err;
if (!frame || !mode)
return -EINVAL;
@@ -7243,9 +7242,7 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
if (!has_hdmi_infoframe)
return -EINVAL;
- err = hdmi_vendor_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_vendor_infoframe_init(frame);
/*
* Even if it's not absolutely necessary to send the infoframe
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7ac5e6c5e00d..8b58127bca37 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -763,12 +763,9 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder,
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
if (IS_DGFX(i915))
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
+ hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
else
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
-
- if (drm_WARN_ON(encoder->base.dev, ret))
- return false;
+ hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
frame->sdi = HDMI_SPD_SDI_PC;
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0a8e0a13f516..75899e4a011f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -995,12 +995,7 @@ static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi
*hdmi,
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
ssize_t err;
- err = hdmi_spd_infoframe_init(, vendor, product);
- if (err < 0) {
- dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
- err);
- return err;
- }
+ hdmi_spd_infoframe_init(, vendor, product);
err = hdmi_spd_infoframe_pack(, buffer, sizeof(buffer));
if (err < 0) {
@@ -1018,12 +1013,7 @@ static int mtk_hdmi_setup_audio_infoframe(struct
mtk_hdmi *hdmi)
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE +
Re: [PATCH] drm/amd: Use pci_dev_id() to simplify the code
Applied. Thanks! Alex On Mon, Aug 7, 2023 at 9:22 AM Xiongfeng Wang wrote: > > PCI core API pci_dev_id() can be used to get the BDF number for a pci > device. We don't need to compose it mannually. Use pci_dev_id() to > simplify the code a little bit. > > Signed-off-by: Xiongfeng Wang > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > index 385c6acb5728..aee0cfdc6da3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > @@ -706,7 +706,7 @@ int amdgpu_acpi_pcie_performance_request(struct > amdgpu_device *adev, > > atcs_input.size = sizeof(struct atcs_pref_req_input); > /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ > - atcs_input.client_id = adev->pdev->devfn | (adev->pdev->bus->number > << 8); > + atcs_input.client_id = pci_dev_id(adev->pdev); > atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK; > atcs_input.flags = ATCS_WAIT_FOR_COMPLETION; > if (advertise) > @@ -776,7 +776,7 @@ int amdgpu_acpi_power_shift_control(struct amdgpu_device > *adev, > > atcs_input.size = sizeof(struct atcs_pwr_shift_input); > /* dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ > - atcs_input.dgpu_id = adev->pdev->devfn | (adev->pdev->bus->number << > 8); > + atcs_input.dgpu_id = pci_dev_id(adev->pdev); > atcs_input.dev_acpi_state = dev_state; > atcs_input.drv_state = drv_state; > > @@ -1141,7 +1141,7 @@ int amdgpu_acpi_get_tmr_info(struct amdgpu_device > *adev, u64 *tmr_offset, > if (!tmr_offset || !tmr_size) > return -EINVAL; > > - bdf = (adev->pdev->bus->number << 8) | adev->pdev->devfn; > + bdf = pci_dev_id(adev->pdev); > dev_info = amdgpu_acpi_get_dev(bdf); > if (!dev_info) > return -ENOENT; > @@ -1162,7 +1162,7 @@ int amdgpu_acpi_get_mem_info(struct amdgpu_device > *adev, int xcc_id, > if (!numa_info) > return -EINVAL; > > - bdf = (adev->pdev->bus->number << 8) | adev->pdev->devfn; > + bdf = pci_dev_id(adev->pdev); > dev_info = amdgpu_acpi_get_dev(bdf); > if (!dev_info) > return -ENOENT; > -- > 2.20.1 >
Re: [PATCH v4 1/7] drm/amdgpu/vcn: Add MMSCH v4_0_3 support for sriov
The series is:
Acked-by: Leo Liu .
On 2023-08-08 12:26, Samir Dhume wrote:
The structures are the same as v4_0 except for the
init header
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h | 37 +++
1 file changed, 37 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
new file mode 100644
index ..db7eb5260295
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MMSCH_V4_0_3_H__
+#define __MMSCH_V4_0_3_H__
+
+#include "amdgpu_vcn.h"
+#include "mmsch_v4_0.h"
+
+struct mmsch_v4_0_3_init_header {
+ uint32_t version;
+ uint32_t total_size;
+ struct mmsch_v4_0_table_info vcn0;
+ struct mmsch_v4_0_table_info mjpegdec0[4];
+ struct mmsch_v4_0_table_info mjpegdec1[4];
+};
+#endif
Re: [PATCH v5 1/1] drm/doc: Document DRM device reset expectations
It's the same situation as SIGSEGV. A process can catch the signal, but if it doesn't, it gets killed. GL and Vulkan APIs give you a way to catch the GPU error and prevent the process termination. If you don't use the API, you'll get undefined behavior, which means anything can happen, including process termination. Marek On Tue, Aug 8, 2023 at 8:14 AM Sebastian Wick wrote: > > On Fri, Aug 4, 2023 at 3:03 PM Daniel Vetter wrote: > > > > On Tue, Jun 27, 2023 at 10:23:23AM -0300, André Almeida wrote: > > > Create a section that specifies how to deal with DRM device resets for > > > kernel and userspace drivers. > > > > > > Acked-by: Pekka Paalanen > > > Signed-off-by: André Almeida > > > --- > > > > > > v4: > > > https://lore.kernel.org/lkml/20230626183347.55118-1-andrealm...@igalia.com/ > > > > > > Changes: > > > - Grammar fixes (Randy) > > > > > > Documentation/gpu/drm-uapi.rst | 68 ++ > > > 1 file changed, 68 insertions(+) > > > > > > diff --git a/Documentation/gpu/drm-uapi.rst > > > b/Documentation/gpu/drm-uapi.rst > > > index 65fb3036a580..3cbffa25ed93 100644 > > > --- a/Documentation/gpu/drm-uapi.rst > > > +++ b/Documentation/gpu/drm-uapi.rst > > > @@ -285,6 +285,74 @@ for GPU1 and GPU2 from different vendors, and a > > > third handler for > > > mmapped regular files. Threads cause additional pain with signal > > > handling as well. > > > > > > +Device reset > > > + > > > + > > > +The GPU stack is really complex and is prone to errors, from hardware > > > bugs, > > > +faulty applications and everything in between the many layers. Some > > > errors > > > +require resetting the device in order to make the device usable again. > > > This > > > +sections describes the expectations for DRM and usermode drivers when a > > > +device resets and how to propagate the reset status. > > > + > > > +Kernel Mode Driver > > > +-- > > > + > > > +The KMD is responsible for checking if the device needs a reset, and to > > > perform > > > +it as needed. Usually a hang is detected when a job gets stuck > > > executing. KMD > > > +should keep track of resets, because userspace can query any time about > > > the > > > +reset stats for an specific context. This is needed to propagate to the > > > rest of > > > +the stack that a reset has happened. Currently, this is implemented by > > > each > > > +driver separately, with no common DRM interface. > > > + > > > +User Mode Driver > > > + > > > + > > > +The UMD should check before submitting new commands to the KMD if the > > > device has > > > +been reset, and this can be checked more often if the UMD requires it. > > > After > > > +detecting a reset, UMD will then proceed to report it to the application > > > using > > > +the appropriate API error code, as explained in the section below about > > > +robustness. > > > + > > > +Robustness > > > +-- > > > + > > > +The only way to try to keep an application working after a reset is if it > > > +complies with the robustness aspects of the graphical API that it is > > > using. > > > + > > > +Graphical APIs provide ways to applications to deal with device resets. > > > However, > > > +there is no guarantee that the app will use such features correctly, and > > > the > > > +UMD can implement policies to close the app if it is a repeating > > > offender, > > > > Not sure whether this one here is due to my input, but s/UMD/KMD. Repeat > > offender killing is more a policy where the kernel enforces policy, and no > > longer up to userspace to dtrt (because very clearly userspace is not > > really doing the right thing anymore when it's just hanging the gpu in an > > endless loop). Also maybe tune it down further to something like "the > > kernel driver may implemnent ..." > > > > In my opinion the umd shouldn't implement these kind of magic guesses, the > > entire point of robustness apis is to delegate responsibility for > > correctly recovering to the application. And the kernel is left with > > enforcing fair resource usage policies (which eventually might be a > > cgroups limit on how much gpu time you're allowed to waste with gpu > > resets). > > Killing apps that the kernel thinks are misbehaving really doesn't > seem like a good idea to me. What if the process is a service getting > restarted after getting killed? What if killing that process leaves > the system in a bad state? > > Can't the kernel provide some information to user space so that e.g. > systemd can handle those situations? > > > > +likely in a broken loop. This is done to ensure that it does not keep > > > blocking > > > +the user interface from being correctly displayed. This should be done > > > even if > > > +the app is correct but happens to trigger some bug in the > > > hardware/driver. > > > + > > > +OpenGL > > > +~~ > > > + > > > +Apps using OpenGL should use the available robust interfaces, like the > > > +extension ``GL_ARB_robustness``
Re: [PATCH] fix throttle_status for other than MP0 11.0.7
Applied. Thanks!
Alex
On Tue, Aug 8, 2023 at 4:38 AM Quan, Evan wrote:
>
> [AMD Official Use Only - General]
>
> Reviewed-by: Evan Quan
>
> > -Original Message-
> > From: Umio Yasuno
> > Sent: Tuesday, August 8, 2023 2:41 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Quan, Evan
> > ; Limonciello, Mario
> > Subject: [PATCH] fix throttle_status for other than MP0 11.0.7
> >
> > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2720
> > Signed-off-by: Umio Yasuno
> > ---
> > .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 14 +++---
> > 1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 85d53597e..548d25cf3 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -578,7 +578,9 @@ static int sienna_cichlid_tables_init(struct
> > smu_context *smu)
> > return -ENOMEM;
> > }
> >
> > -static uint32_t sienna_cichlid_get_throttler_status_locked(struct
> > smu_context *smu)
> > +static uint32_t sienna_cichlid_get_throttler_status_locked(struct
> > smu_context *smu,
> > +bool
> > use_metrics_v3,
> > +bool
> > use_metrics_v2)
> > {
> > struct smu_table_context *smu_table= >smu_table;
> > SmuMetricsExternal_t *metrics_ext =
> > @@ -586,13 +588,11 @@ static uint32_t
> > sienna_cichlid_get_throttler_status_locked(struct smu_context *s
> > uint32_t throttler_status = 0;
> > int i;
> >
> > - if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))
> > &&
> > - (smu->smc_fw_version >= 0x3A4900)) {
> > + if (use_metrics_v3) {
> > for (i = 0; i < THROTTLER_COUNT; i++)
> > throttler_status |=
> > (metrics_ext-
> > >SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
> > - } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11,
> > 0, 7)) &&
> > - (smu->smc_fw_version >= 0x3A4300)) {
> > + } else if (use_metrics_v2) {
> > for (i = 0; i < THROTTLER_COUNT; i++)
> > throttler_status |=
> > (metrics_ext-
> > >SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
> > @@ -854,7 +854,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct
> > smu_context *smu,
> > metrics->TemperatureVrSoc) *
> > SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> > break;
> > case METRICS_THROTTLER_STATUS:
> > - *value = sienna_cichlid_get_throttler_status_locked(smu);
> > + *value = sienna_cichlid_get_throttler_status_locked(smu,
> > use_metrics_v3, use_metrics_v2);
> > break;
> > case METRICS_CURR_FANSPEED:
> > *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
> > @@ -4056,7 +4056,7 @@ static ssize_t
> > sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> > gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3-
> > >CurrClock[PPCLK_DCLK_1] :
> > use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
> > metrics->CurrClock[PPCLK_DCLK_1];
> >
> > - gpu_metrics->throttle_status =
> > sienna_cichlid_get_throttler_status_locked(smu);
> > + gpu_metrics->throttle_status =
> > sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3,
> > use_metrics_v2);
> > gpu_metrics->indep_throttle_status =
> > smu_cmn_get_indep_throttler_status(gpu_metrics-
> > >throttle_status,
> >
> > sienna_cichlid_throttler_map);
> > --
> > 2.40.1
> >
>
RE: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
[AMD Official Use Only - General]
Thanks Leo. I'll restore the check for sriov before calling
amdgpu_virt_alloc_mm_table(). That will make it consistent with other vcn ip
versions. I'll retain the check for sriov inside amdgpu_virt_alloc_mm_table()
as well, as a conservative check.
Thanks,
Samir
-Original Message-
From: Liu, Leo
Sent: Tuesday, August 8, 2023 8:29 AM
To: Dhume, Samir ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang ; Chen, Guchun ;
Wan, Gavin ; Lazar, Lijo ; Min, Frank
; Zhang, Hawking
Subject: Re: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
On 2023-07-28 15:15, Samir Dhume wrote:
> initialization table handshake with mmsch
>
> Signed-off-by: Samir Dhume
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 257 +---
> 1 file changed, 233 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 411c1d802823..b978265b2d77 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -31,6 +31,7 @@
> #include "soc15d.h"
> #include "soc15_hw_ip.h"
> #include "vcn_v2_0.h"
> +#include "mmsch_v4_0_3.h"
>
> #include "vcn/vcn_4_0_3_offset.h"
> #include "vcn/vcn_4_0_3_sh_mask.h"
> @@ -44,6 +45,7 @@
> #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_00x48300
>
> +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
> static int vcn_v4_0_3_set_powergating_state(void *handle, @@ -130,6
> +132,10 @@ static int vcn_v4_0_3_sw_init(void *handle)
> amdgpu_vcn_fwlog_init(>vcn.inst[i]);
> }
>
> + r = amdgpu_virt_alloc_mm_table(adev);
Since this function is not for bare-metal, please move amdgpu_sriov_vf() check
from inside of the function to here, to avoid confusion.
> + if (r)
> + return r;
> +
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
>
> @@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
> drm_dev_exit(idx);
> }
>
> + amdgpu_virt_free_mm_table(adev);
Same as above.
Regards,
Leo
> +
> r = amdgpu_vcn_suspend(adev);
> if (r)
> return r;
> @@ -189,33 +197,47 @@ static int vcn_v4_0_3_hw_init(void *handle)
> struct amdgpu_ring *ring;
> int i, r, vcn_inst;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - vcn_inst = GET_INST(VCN, i);
> - ring = >vcn.inst[i].ring_enc[0];
> + if (amdgpu_sriov_vf(adev)) {
> + r = vcn_v4_0_3_start_sriov(adev);
> + if (r)
> + goto done;
>
> - if (ring->use_doorbell) {
> - adev->nbio.funcs->vcn_doorbell_range(
> - adev, ring->use_doorbell,
> - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> - 9 * vcn_inst,
> - adev->vcn.inst[i].aid_id);
> -
> - WREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL,
> - ring->doorbell_index
> - <<
> VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> - VCN_RB1_DB_CTRL__EN_MASK);
> -
> - /* Read DB_CTRL to flush the write DB_CTRL command. */
> - RREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL);
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + ring = >vcn.inst[i].ring_enc[0];
> + ring->wptr = 0;
> + ring->wptr_old = 0;
> + vcn_v4_0_3_unified_ring_set_wptr(ring);
> + ring->sched.ready = true;
> }
> + } else {
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + vcn_inst = GET_INST(VCN, i);
> + ring = >vcn.inst[i].ring_enc[0];
> +
> + if (ring->use_doorbell) {
> + adev->nbio.funcs->vcn_doorbell_range(
> + adev, ring->use_doorbell,
> + (adev->doorbell_index.vcn.vcn_ring0_1
> << 1) +
> + 9 * vcn_inst,
> + adev->vcn.inst[i].aid_id);
> +
> + WREG32_SOC15(
> + VCN, GET_INST(VCN, ring->me),
> + regVCN_RB1_DB_CTRL,
> +
[PATCH v4 6/7] drm/amdgpu/jpeg: mmsch_v3_0_4 requires doorbell on 32 byte boundary
BASE: VCN0 unified (32 byte boundary)
BASE+4: MJPEG0
BASE+5: MJPEG1
BASE+6: MJPEG2
BASE+7: MJPEG3
BASE+12: MJPEG4
BASE+13: MJPEG5
BASE+14: MJPEG6
BASE+15: MJPEG7
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 33f04ea8549f..f745eeef442f 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -111,9 +111,20 @@ static int jpeg_v4_0_3_sw_init(void *handle)
ring = >jpeg.inst[i].ring_dec[j];
ring->use_doorbell = true;
ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 1 + j + 9 * jpeg_inst;
+ if (!amdgpu_sriov_vf(adev)) {
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1
<< 1) +
+ 1 + j + 9 * jpeg_inst;
+ } else {
+ if (j < 4)
+ ring->doorbell_index =
+
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 4 + j + 32 * jpeg_inst;
+ else
+ ring->doorbell_index =
+
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 8 + j + 32 * jpeg_inst;
+ }
sprintf(ring->name, "jpeg_dec_%d.%d",
adev->jpeg.inst[i].aid_id, j);
r = amdgpu_ring_init(adev, ring, 512,
>jpeg.inst->irq, 0,
AMDGPU_RING_PRIO_DEFAULT, NULL);
--
2.34.1
[PATCH v4 7/7] drm/amdgpu/vcn: change end doorbell index for vcn_v4_0_3
For sriov, doorbell index for vcn0 for AID needs to be on
32 byte boundary so we need to move the vcn end doorbell
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index f637574644c0..4a279960cd21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -330,14 +330,14 @@ typedef enum _AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 {
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F,
/* IH: 0x1A0 ~ 0x1AF */
AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0,
- /* VCN: 0x1B0 ~ 0x1D4 */
+ /* VCN: 0x1B0 ~ 0x1E8 */
AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0,
- AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1D4,
+ AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1E8,
AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP=
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START,
AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP =
AMDGPU_DOORBELL_LAYOUT1_VCN_END,
- AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1D4,
+ AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1E8,
AMDGPU_DOORBELL_LAYOUT1_INVALID = 0x
} AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1;
--
2.34.1
[PATCH v4 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
initialization table handshake with mmsch
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 260 +---
1 file changed, 236 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 411c1d802823..66eb0c8e6f94 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -31,6 +31,7 @@
#include "soc15d.h"
#include "soc15_hw_ip.h"
#include "vcn_v2_0.h"
+#include "mmsch_v4_0_3.h"
#include "vcn/vcn_4_0_3_offset.h"
#include "vcn/vcn_4_0_3_sh_mask.h"
@@ -44,6 +45,7 @@
#define VCN_VID_SOC_ADDRESS_2_00x1fb00
#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
+static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_3_set_powergating_state(void *handle,
@@ -130,6 +132,12 @@ static int vcn_v4_0_3_sw_init(void *handle)
amdgpu_vcn_fwlog_init(>vcn.inst[i]);
}
+ if (amdgpu_sriov_vf(adev)) {
+ r = amdgpu_virt_alloc_mm_table(adev);
+ if (r)
+ return r;
+ }
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
@@ -167,6 +175,9 @@ static int vcn_v4_0_3_sw_fini(void *handle)
drm_dev_exit(idx);
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_free_mm_table(adev);
+
r = amdgpu_vcn_suspend(adev);
if (r)
return r;
@@ -189,33 +200,47 @@ static int vcn_v4_0_3_hw_init(void *handle)
struct amdgpu_ring *ring;
int i, r, vcn_inst;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- vcn_inst = GET_INST(VCN, i);
- ring = >vcn.inst[i].ring_enc[0];
+ if (amdgpu_sriov_vf(adev)) {
+ r = vcn_v4_0_3_start_sriov(adev);
+ if (r)
+ goto done;
- if (ring->use_doorbell) {
- adev->nbio.funcs->vcn_doorbell_range(
- adev, ring->use_doorbell,
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst,
- adev->vcn.inst[i].aid_id);
-
- WREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL,
- ring->doorbell_index
- <<
VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- /* Read DB_CTRL to flush the write DB_CTRL command. */
- RREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ ring = >vcn.inst[i].ring_enc[0];
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v4_0_3_unified_ring_set_wptr(ring);
+ ring->sched.ready = true;
}
+ } else {
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ vcn_inst = GET_INST(VCN, i);
+ ring = >vcn.inst[i].ring_enc[0];
+
+ if (ring->use_doorbell) {
+ adev->nbio.funcs->vcn_doorbell_range(
+ adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1
<< 1) +
+ 9 * vcn_inst,
+ adev->vcn.inst[i].aid_id);
+
+ WREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL,
+ ring->doorbell_index
+ <<
VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ /* Read DB_CTRL to flush the write DB_CTRL
command. */
+ RREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL);
+ }
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+ }
}
done:
@@ -813,6
[PATCH v4 5/7] drm/amdgpu/jpeg: sriov support for jpeg_v4_0_3
initialization table handshake with mmsch
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 174 ---
1 file changed, 153 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index ce2b22f7e4e4..33f04ea8549f 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -26,6 +26,7 @@
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v4_0_3.h"
+#include "mmsch_v4_0_3.h"
#include "vcn/vcn_4_0_3_offset.h"
#include "vcn/vcn_4_0_3_sh_mask.h"
@@ -41,6 +42,7 @@ static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device
*adev);
static int jpeg_v4_0_3_set_powergating_state(void *handle,
enum amd_powergating_state state);
static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
+static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
static int amdgpu_ih_srcid_jpeg[] = {
VCN_4_0__SRCID__JPEG_DECODE,
@@ -160,6 +162,120 @@ static int jpeg_v4_0_3_sw_fini(void *handle)
return r;
}
+static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring;
+ uint64_t ctx_addr;
+ uint32_t param, resp, expected;
+ uint32_t tmp, timeout;
+
+ struct amdgpu_mm_table *table = >virt.mm_table;
+ uint32_t *table_loc;
+ uint32_t table_size;
+ uint32_t size, size_dw, item_offset;
+ uint32_t init_status;
+ int i, j, jpeg_inst;
+
+ struct mmsch_v4_0_cmd_direct_write
+ direct_wt = { {0} };
+ struct mmsch_v4_0_cmd_end end = { {0} };
+ struct mmsch_v4_0_3_init_header header;
+
+ direct_wt.cmd_header.command_type =
+ MMSCH_COMMAND__DIRECT_REG_WRITE;
+ end.cmd_header.command_type =
+ MMSCH_COMMAND__END;
+
+ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
+ jpeg_inst = GET_INST(JPEG, i);
+
+ memset(, 0, sizeof(struct mmsch_v4_0_3_init_header));
+ header.version = MMSCH_VERSION;
+ header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >>
2;
+
+ table_loc = (uint32_t *)table->cpu_addr;
+ table_loc += header.total_size;
+
+ item_offset = header.total_size;
+
+
+ for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) {
+ ring = >jpeg.inst[i].ring_dec[j];
+ table_size = 0;
+
+ tmp = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);
+ MMSCH_V4_0_INSERT_DIRECT_WT(tmp,
lower_32_bits(ring->gpu_addr));
+ tmp = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
+ MMSCH_V4_0_INSERT_DIRECT_WT(tmp,
upper_32_bits(ring->gpu_addr));
+ tmp = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JRBC0_UVD_JRBC_RB_SIZE);
+ MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
+
+ if (j <= 3) {
+ header.mjpegdec0[j].table_offset = item_offset;
+ header.mjpegdec0[j].init_status = 0;
+ header.mjpegdec0[j].table_size = table_size;
+ } else {
+ header.mjpegdec1[j-4].table_offset =
item_offset;
+ header.mjpegdec1[j-4].init_status = 0;
+ header.mjpegdec1[j-4].table_size = table_size;
+ }
+ header.total_size += table_size;
+ item_offset+= table_size;
+ }
+
+ MMSCH_V4_0_INSERT_END();
+
+ /* send init table to MMSCH */
+ size = sizeof(struct mmsch_v4_0_3_init_header);
+ table_loc = (uint32_t *)table->cpu_addr;
+ memcpy((void *)table_loc, , size);
+
+ ctx_addr = table->gpu_addr;
+ WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO,
lower_32_bits(ctx_addr));
+ WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI,
upper_32_bits(ctx_addr));
+
+ tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);
+ tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
+ tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
+ WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);
+
+ size = header.total_size;
+ WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size);
+
+ WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0);
+
+ param = 0x0001;
+ WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param);
+ tmp = 0;
+ timeout = 1000;
+ resp = 0;
+ expected = MMSCH_VF_MAILBOX_RESP__OK;
+
[PATCH v4 4/7] drm/amdgpu/vcn: mmsch_v3_0_4 requires doorbell on 32 byte boundary
Signed-off-by: Samir Dhume --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 66eb0c8e6f94..1e5aad207878 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -113,9 +113,16 @@ static int vcn_v4_0_3_sw_init(void *handle) ring = >vcn.inst[i].ring_enc[0]; ring->use_doorbell = true; - ring->doorbell_index = - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + - 9 * vcn_inst; + + if (!amdgpu_sriov_vf(adev)) + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 9 * vcn_inst; + else + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 32 * vcn_inst; + ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); r = amdgpu_ring_init(adev, ring, 512, >vcn.inst->irq, 0, -- 2.34.1
[PATCH v4 1/7] drm/amdgpu/vcn: Add MMSCH v4_0_3 support for sriov
The structures are the same as v4_0 except for the
init header
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h | 37 +++
1 file changed, 37 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
new file mode 100644
index ..db7eb5260295
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MMSCH_V4_0_3_H__
+#define __MMSCH_V4_0_3_H__
+
+#include "amdgpu_vcn.h"
+#include "mmsch_v4_0.h"
+
+struct mmsch_v4_0_3_init_header {
+ uint32_t version;
+ uint32_t total_size;
+ struct mmsch_v4_0_table_info vcn0;
+ struct mmsch_v4_0_table_info mjpegdec0[4];
+ struct mmsch_v4_0_table_info mjpegdec1[4];
+};
+#endif
--
2.34.1
[PATCH v4 2/7] drm/amdgpu/vcn : Skip vcn power-gating change for sriov
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 550ac040b4be..411c1d802823 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1317,6 +1317,15 @@ static int vcn_v4_0_3_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ /* for SRIOV, guest should not control VCN Power-gating
+* MMSCH FW should control Power-gating and clock-gating
+* guest should avoid touching CGC and PG
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if (state == adev->vcn.cur_state)
return 0;
--
2.34.1
Re: [PATCH] drm/amd: fix debugfs access for discovery blob
On 8/7/2023 10:20, Alex Deucher wrote:
On Tue, Aug 1, 2023 at 4:15 PM Mario Limonciello
wrote:
Accessing the blob for amdgpu discovery from debugfs triggers:
[ 1924.487667] kernel BUG at mm/usercopy.c:102!
usercopy_abort() explains that it needs to be solved by creating
a cache to store the data.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2748#note_2023519
Signed-off-by: Mario Limonciello
Reviewed-by: Alex Deucher
Although this avoids the issue; I've concluded it's an inappropriate fix
and will abandon it. It turns out to spit out 64k discovery blobs that
should have been 8k.
6.5-rc and ASDN already picked up a better solution.
db3b5cb64a9c ("drm/amdgpu: Use apt name for FW reserved region")
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 17 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a3b86b86dc477..66a2251bdeba4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -791,8 +791,11 @@ struct amdgpu_device {
boolaccel_working;
struct notifier_block acpi_nb;
struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
- struct debugfs_blob_wrapper debugfs_vbios_blob;
- struct debugfs_blob_wrapper debugfs_discovery_blob;
+#if defined(CONFIG_DEBUG_FS)
+ struct debugfs_blob_wrapper debugfs_vbios_blob;
+ struct debugfs_blob_wrapper debugfs_discovery_blob;
+ struct kmem_cache *discovery_blob_cache;
+#endif
struct mutexsrbm_mutex;
/* GRBM index mutex. Protects concurrent access to GRBM index */
struct mutexgrbm_idx_mutex;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 56e89e76ff179..55ea5be14b188 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -2180,7 +2180,15 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
debugfs_create_blob("amdgpu_vbios", 0444, root,
>debugfs_vbios_blob);
- adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
+
+ adev->discovery_blob_cache =
kmem_cache_create_usercopy("amdgpu_discovery",
+
adev->mman.discovery_tmr_size,
+ 0, 0, 0,
+
adev->mman.discovery_tmr_size,
+ NULL);
+ adev->debugfs_discovery_blob.data =
kmem_cache_alloc(adev->discovery_blob_cache, GFP_KERNEL);
+ memcpy(adev->debugfs_discovery_blob.data, adev->mman.discovery_bin,
+ adev->mman.discovery_tmr_size);
adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
debugfs_create_blob("amdgpu_discovery", 0444, root,
>debugfs_discovery_blob);
@@ -2188,6 +2196,12 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
return 0;
}
+void amdgpu_debugfs_fini(struct amdgpu_device *adev)
+{
+ kmem_cache_free(adev->discovery_blob_cache,
adev->debugfs_discovery_blob.data);
+ kmem_cache_destroy(adev->discovery_blob_cache);
+}
+
#else
int amdgpu_debugfs_init(struct amdgpu_device *adev)
{
@@ -2197,4 +2211,5 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
return 0;
}
+inline void amdgpu_debugfs_fini(struct amdgpu_device *adev) {}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0593ef8fe0a63..1a3b30dff5171 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2276,6 +2276,8 @@ amdgpu_pci_remove(struct pci_dev *pdev)
struct drm_device *dev = pci_get_drvdata(pdev);
struct amdgpu_device *adev = drm_to_adev(dev);
+ amdgpu_debugfs_fini(adev);
+
amdgpu_xcp_dev_unplug(adev);
drm_dev_unplug(dev);
--
2.34.1
Re: [PATCH V2 1/5] drm/amdkfd: ignore crat by default
On Tue, 8 Aug 2023 at 15:59, Christian König wrote: > > Am 08.08.23 um 00:05 schrieb Alex Deucher: > > We are dropping the IOMMUv2 path, so no need to enable this. > > It's often buggy on consumer platforms anyway. > > > > Signed-off-by: Alex Deucher > > Bye ATC, it wasn't really nice with you :) > > Acked-by: Christian König for the whole series. > Tested-by: Mike Lothian
Re: [PATCH V2 1/5] drm/amdkfd: ignore crat by default
Am 08.08.23 um 00:05 schrieb Alex Deucher: We are dropping the IOMMUv2 path, so no need to enable this. It's often buggy on consumer platforms anyway. Signed-off-by: Alex Deucher Bye ATC, it wasn't really nice with you :) Acked-by: Christian König for the whole series. --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 49f40d9f16e86..f5a6f562e2a80 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1543,11 +1543,7 @@ static bool kfd_ignore_crat(void) if (ignore_crat) return true; -#ifndef KFD_SUPPORT_IOMMU_V2 ret = true; -#else - ret = false; -#endif return ret; }
RE: [PATCH 00/22] DC Patches Aug 04 2023
[AMD Official Use Only - General] Hi all, This week this patchset was tested on the following systems: * Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U * MSI Gaming X Trio RX 6800 * Gigabyte Gaming OC RX 7900 XTX These systems were tested on the following display/connection types: * eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U]) * VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI]) * DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters]) * Thunderbolt (LG Ultrafine 5k) * MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays) * DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display) * USB 4 (Kensington SD5700T and 1x 4k 60Hz display) * PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports]) The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to): * Changing display configurations and settings * Benchmark testing * Feature testing (Freesync, etc.) Automated testing includes (but is not limited to): * Script testing (scripts to automate some of the manual checks) * IGT testing The patchset consists of the amd-staging-drm-next branch (Head commit - 389af3e7a5f7 drm/amd/display: Promote DC to 2.3.245) with new patches added on top of it. Tested on Ubuntu 22.04.2 Tested-by: Daniel Wheeler Thank you, Dan Wheeler Sr. Technologist | AMD SW Display -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 amd.com -Original Message- From: Tom Chung Sent: Wednesday, August 2, 2023 2:51 AM To: amd-gfx@lists.freedesktop.org Cc: Wentland, Harry ; Li, Sun peng (Leo) ; Lakha, Bhawanpreet ; Siqueira, Rodrigo ; Pillai, Aurabindo ; Zhuo, Qingqing (Lillian) ; Li, Roman ; Lin, Wayne ; Wang, Chao-kai (Stylon) ; Chiu, Solomon ; Kotarac, Pavle ; Gutierrez, Agustin ; Chung, ChiaHsuan (Tom) ; Wheeler, Daniel Subject: [PATCH 00/22] DC Patches Aug 04 2023 This DC patchset brings improvements in multiple areas. In summary, we have: - Fix a regression in blank pixel data caused by coding mistake - Fix a bug when searching for insert_above_mpcc - Fix backlight off cmd for OLED panel - Update add plane to context logic with a new algorithm - Adjust visual confirm dpp height offset to be 1/240 of v addressable - Add interface to enable DPIA trace - Support plane clip with zero recout size - Blocking invalid 420 modes on HDMI TMDS for DCN31 and DCN314 - Make mpc32 functions available to future DCNs - Change HDCP update sequence for DM Cc: Daniel Wheeler Alvin Lee (1): drm/amd/display: Use max memclk variable when setting max memclk Austin Zheng (2): drm/amd/display: Set Stream Update Flags in commit_state_no_check drm/amd/display: Use DTBCLK as refclk instead of DPREFCLK Bhawanpreet Lakha (1): drm/amd/display: Change HDCP update sequence for DM Leo Chen (3): drm/amd/display: Revert "dc: read down-spread percentage from lut to adjust dprefclk" drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN31 drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN314 Martin Leung (1): drm/amd/display: Promote DAL to 3.2.246 Mike Hsieh (1): drm/amd/display: Add vendor Id for reference Stylon Wang (2): drm/amd/display: Add interface to enable DPIA trace drm/amd/display: Enable DPIA trace with DC debug mask Swapnil Patel (1): drm/amd/display: Fix backlight off cmd for OLED panel Wenjing Liu (8): drm/amd/display: fix a regression in blank pixel data caused by coding mistake drm/amd/display: support plane clip with zero recout size drm/amd/display: always acquire MPO pipe for every blending tree drm/amd/display: update add plane to context logic with a new algorithm drm/amd/display: adjust visual confirm dpp height offset to be 1/240 of v addressable drm/amd/display: do not treat clip_rect size change as a scaling change drm/amd/display: move idle pipe allocation logic into dcn specific layer drm/amd/display: rename acquire_idle_pipe_for_layer to acquire_free_pipe_as_sec_dpp_pipe Wesley Chalmers (2): drm/amd/display: Fix a bug when searching for insert_above_mpcc drm/amd/display: Make mpc32 functions available to future DCNs .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +- .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 80 ++- .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c| 32 +- .../dc/clk_mgr/dcn314/dcn314_clk_mgr.h| 7 - .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 111 +--- .../gpu/drm/amd/display/dc/core/dc_resource.c | 589 --
Re: [PATCH] drm/amdgpu: disable mcbp if parameter zero is set
On Mon, Aug 7, 2023 at 11:18 PM wrote:
>
> From: Jiadong Zhu
>
> The parameter amdgpu_mcbp shall have priority against the default value
> calculated from the chip version.
> User could disable mcbp by setting the parameter mcbp as zero.
>
> Signed-off-by: Jiadong Zhu
I think this should be expanded to disable the sw rings as well since
they presumably won't work correctly without MCBP.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7314529553f6..615669dcabc2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3699,10 +3699,11 @@ static void amdgpu_device_set_mcbp(struct
> amdgpu_device *adev)
> {
> if (amdgpu_mcbp == 1)
> adev->gfx.mcbp = true;
> -
> - if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
> - (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
> - adev->gfx.num_gfx_rings)
> + else if (amdgpu_mcbp == 0)
> + adev->gfx.mcbp = false;
> + else if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
> +(adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
> +adev->gfx.num_gfx_rings)
> adev->gfx.mcbp = true;
>
> if (amdgpu_sriov_vf(adev))
> --
> 2.25.1
>
Re: [PATCH] drm/amdgpu/irq: Move irq resume to the beginning
Acked-by: Alex Deucher
On Tue, Aug 8, 2023 at 2:43 AM Deng, Emily wrote:
>
> [AMD Official Use Only - General]
>
> Ping.
>
> >-Original Message-
> >From: Emily Deng
> >Sent: Monday, August 7, 2023 1:11 PM
> >To: amd-gfx@lists.freedesktop.org
> >Cc: Deng, Emily
> >Subject: [PATCH] drm/amdgpu/irq: Move irq resume to the beginning
> >
> >Need to move irq resume to the beginning of reset sriov, or if one interrupt
> >occurs before irq resume, then the irq won't work anymore.
> >
> >Signed-off-by: Emily Deng
> >---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >index 1338489b0b2f..8b304fdfe6db 100644
> >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >@@ -4617,6 +4617,7 @@ static int amdgpu_device_reset_sriov(struct
> >amdgpu_device *adev,
> > r = amdgpu_virt_reset_gpu(adev);
> > if (r)
> > return r;
> >+ amdgpu_irq_gpu_reset_resume_helper(adev);
> >
> > /* some sw clean up VF needs to do before recover */
> > amdgpu_virt_post_reset(adev);
> >@@ -4646,7 +4647,6 @@ static int amdgpu_device_reset_sriov(struct
> >amdgpu_device *adev,
> > amdgpu_put_xgmi_hive(hive);
> >
> > if (!r) {
> >- amdgpu_irq_gpu_reset_resume_helper(adev);
> > r = amdgpu_ib_ring_tests(adev);
> >
> > amdgpu_amdkfd_post_reset(adev);
> >--
> >2.36.1
>
Re: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
On 2023-07-28 15:15, Samir Dhume wrote:
initialization table handshake with mmsch
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 257 +---
1 file changed, 233 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 411c1d802823..b978265b2d77 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -31,6 +31,7 @@
#include "soc15d.h"
#include "soc15_hw_ip.h"
#include "vcn_v2_0.h"
+#include "mmsch_v4_0_3.h"
#include "vcn/vcn_4_0_3_offset.h"
#include "vcn/vcn_4_0_3_sh_mask.h"
@@ -44,6 +45,7 @@
#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
+static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_3_set_powergating_state(void *handle,
@@ -130,6 +132,10 @@ static int vcn_v4_0_3_sw_init(void *handle)
amdgpu_vcn_fwlog_init(>vcn.inst[i]);
}
+ r = amdgpu_virt_alloc_mm_table(adev);
Since this function is not for bare-metal, please move amdgpu_sriov_vf()
check from inside of the function to here, to avoid confusion.
+ if (r)
+ return r;
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
@@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
drm_dev_exit(idx);
}
+ amdgpu_virt_free_mm_table(adev);
Same as above.
Regards,
Leo
+
r = amdgpu_vcn_suspend(adev);
if (r)
return r;
@@ -189,33 +197,47 @@ static int vcn_v4_0_3_hw_init(void *handle)
struct amdgpu_ring *ring;
int i, r, vcn_inst;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- vcn_inst = GET_INST(VCN, i);
- ring = >vcn.inst[i].ring_enc[0];
+ if (amdgpu_sriov_vf(adev)) {
+ r = vcn_v4_0_3_start_sriov(adev);
+ if (r)
+ goto done;
- if (ring->use_doorbell) {
- adev->nbio.funcs->vcn_doorbell_range(
- adev, ring->use_doorbell,
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst,
- adev->vcn.inst[i].aid_id);
-
- WREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL,
- ring->doorbell_index
- <<
VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- /* Read DB_CTRL to flush the write DB_CTRL command. */
- RREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ ring = >vcn.inst[i].ring_enc[0];
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v4_0_3_unified_ring_set_wptr(ring);
+ ring->sched.ready = true;
}
+ } else {
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ vcn_inst = GET_INST(VCN, i);
+ ring = >vcn.inst[i].ring_enc[0];
+
+ if (ring->use_doorbell) {
+ adev->nbio.funcs->vcn_doorbell_range(
+ adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1
<< 1) +
+ 9 * vcn_inst,
+ adev->vcn.inst[i].aid_id);
+
+ WREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL,
+ ring->doorbell_index
+ <<
VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ /* Read DB_CTRL to flush the write DB_CTRL
command. */
+ RREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL);
+ }
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
Re: [PATCH v5 1/1] drm/doc: Document DRM device reset expectations
On Fri, Aug 4, 2023 at 3:03 PM Daniel Vetter wrote: > > On Tue, Jun 27, 2023 at 10:23:23AM -0300, André Almeida wrote: > > Create a section that specifies how to deal with DRM device resets for > > kernel and userspace drivers. > > > > Acked-by: Pekka Paalanen > > Signed-off-by: André Almeida > > --- > > > > v4: > > https://lore.kernel.org/lkml/20230626183347.55118-1-andrealm...@igalia.com/ > > > > Changes: > > - Grammar fixes (Randy) > > > > Documentation/gpu/drm-uapi.rst | 68 ++ > > 1 file changed, 68 insertions(+) > > > > diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst > > index 65fb3036a580..3cbffa25ed93 100644 > > --- a/Documentation/gpu/drm-uapi.rst > > +++ b/Documentation/gpu/drm-uapi.rst > > @@ -285,6 +285,74 @@ for GPU1 and GPU2 from different vendors, and a third > > handler for > > mmapped regular files. Threads cause additional pain with signal > > handling as well. > > > > +Device reset > > + > > + > > +The GPU stack is really complex and is prone to errors, from hardware bugs, > > +faulty applications and everything in between the many layers. Some errors > > +require resetting the device in order to make the device usable again. This > > +sections describes the expectations for DRM and usermode drivers when a > > +device resets and how to propagate the reset status. > > + > > +Kernel Mode Driver > > +-- > > + > > +The KMD is responsible for checking if the device needs a reset, and to > > perform > > +it as needed. Usually a hang is detected when a job gets stuck executing. > > KMD > > +should keep track of resets, because userspace can query any time about the > > +reset stats for an specific context. This is needed to propagate to the > > rest of > > +the stack that a reset has happened. Currently, this is implemented by each > > +driver separately, with no common DRM interface. > > + > > +User Mode Driver > > + > > + > > +The UMD should check before submitting new commands to the KMD if the > > device has > > +been reset, and this can be checked more often if the UMD requires it. > > After > > +detecting a reset, UMD will then proceed to report it to the application > > using > > +the appropriate API error code, as explained in the section below about > > +robustness. > > + > > +Robustness > > +-- > > + > > +The only way to try to keep an application working after a reset is if it > > +complies with the robustness aspects of the graphical API that it is using. > > + > > +Graphical APIs provide ways to applications to deal with device resets. > > However, > > +there is no guarantee that the app will use such features correctly, and > > the > > +UMD can implement policies to close the app if it is a repeating offender, > > Not sure whether this one here is due to my input, but s/UMD/KMD. Repeat > offender killing is more a policy where the kernel enforces policy, and no > longer up to userspace to dtrt (because very clearly userspace is not > really doing the right thing anymore when it's just hanging the gpu in an > endless loop). Also maybe tune it down further to something like "the > kernel driver may implemnent ..." > > In my opinion the umd shouldn't implement these kind of magic guesses, the > entire point of robustness apis is to delegate responsibility for > correctly recovering to the application. And the kernel is left with > enforcing fair resource usage policies (which eventually might be a > cgroups limit on how much gpu time you're allowed to waste with gpu > resets). Killing apps that the kernel thinks are misbehaving really doesn't seem like a good idea to me. What if the process is a service getting restarted after getting killed? What if killing that process leaves the system in a bad state? Can't the kernel provide some information to user space so that e.g. systemd can handle those situations? > > +likely in a broken loop. This is done to ensure that it does not keep > > blocking > > +the user interface from being correctly displayed. This should be done > > even if > > +the app is correct but happens to trigger some bug in the hardware/driver. > > + > > +OpenGL > > +~~ > > + > > +Apps using OpenGL should use the available robust interfaces, like the > > +extension ``GL_ARB_robustness`` (or ``GL_EXT_robustness`` for OpenGL ES). > > This > > +interface tells if a reset has happened, and if so, all the context state > > is > > +considered lost and the app proceeds by creating new ones. If it is > > possible to > > +determine that robustness is not in use, the UMD will terminate the app > > when a > > +reset is detected, giving that the contexts are lost and the app won't be > > able > > +to figure this out and recreate the contexts. > > + > > +Vulkan > > +~~ > > + > > +Apps using Vulkan should check for ``VK_ERROR_DEVICE_LOST`` for > > submissions. > > +This error code means, among other things, that a device reset has > >
Re: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on smu13
On 8/8/2023 3:56 PM, Feng, Kenneth wrote:
[AMD Official Use Only - General]
Currently no_fan is determined in sw init.
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
This is the case that some boards have fans and some don't have.
smu->ppt_funcs->get_fan_control_mode still need to be defined.
!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT) is enough to
get the fan capability.
Not sure if it's better to depend on pm.no_fan.
What I meant is, based on fan control feature bit you could set
pm.no_fan flag.
When pm.no_fan is set, we won't create hwmon fan attributes for
get/set[1]. That way you could avoid the other checks also. Also when
PMFW is not controlling, it's not guaranteed that the fan controller is
initialized correctly for get to return correct speed/pwm.
[1]
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/pm/amdgpu_pm.c#L3338
Thanks,
Lijo
Thanks.
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, August 8, 2023 6:12 PM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Arif, Maisam
Subject: Re: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on
smu13
On 8/8/2023 1:21 PM, Kenneth Feng wrote:
disallow the fan setting if there is no fan on smu13
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 9b62b45ebb7f..09ef0a7e7679 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1131,7 +1131,9 @@ smu_v13_0_display_clock_voltage_request(struct
smu_context *smu,
uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
{
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ return AMD_FAN_CTRL_NONE;
If there is no PMFW fan control, isn't it better to set pm.no_fan?
Thanks,
Lijo
+ else if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
return AMD_FAN_CTRL_MANUAL;
else
return AMD_FAN_CTRL_AUTO;
@@ -1143,7 +1145,7 @@ smu_v13_0_auto_fan_control(struct smu_context *smu, bool
auto_fan_control)
int ret = 0;
if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
- return 0;
+ return -EINVAL;
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT,
auto_fan_control);
if (ret)
@@ -1204,7 +1206,8 @@ smu_v13_0_set_fan_control_mode(struct smu_context *smu,
switch (mode) {
case AMD_FAN_CTRL_NONE:
- ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
+ if (smu_cmn_feature_is_supported(smu,
SMU_FEATURE_FAN_CONTROL_BIT))
+ ret = -EINVAL;
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v13_0_auto_fan_control(smu, 0);
RE: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on smu13
[AMD Official Use Only - General]
Currently no_fan is determined in sw init.
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
This is the case that some boards have fans and some don't have.
smu->ppt_funcs->get_fan_control_mode still need to be defined.
!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT) is enough to
get the fan capability.
Not sure if it's better to depend on pm.no_fan.
Thanks.
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, August 8, 2023 6:12 PM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Arif, Maisam
Subject: Re: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on
smu13
On 8/8/2023 1:21 PM, Kenneth Feng wrote:
> disallow the fan setting if there is no fan on smu13
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 9b62b45ebb7f..09ef0a7e7679 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -1131,7 +1131,9 @@ smu_v13_0_display_clock_voltage_request(struct
> smu_context *smu,
>
> uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
> {
> - if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> + if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> + return AMD_FAN_CTRL_NONE;
If there is no PMFW fan control, isn't it better to set pm.no_fan?
Thanks,
Lijo
> + else if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> return AMD_FAN_CTRL_MANUAL;
> else
> return AMD_FAN_CTRL_AUTO;
> @@ -1143,7 +1145,7 @@ smu_v13_0_auto_fan_control(struct smu_context *smu,
> bool auto_fan_control)
> int ret = 0;
>
> if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> - return 0;
> + return -EINVAL;
>
> ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT,
> auto_fan_control);
> if (ret)
> @@ -1204,7 +1206,8 @@ smu_v13_0_set_fan_control_mode(struct smu_context *smu,
>
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
> + if (smu_cmn_feature_is_supported(smu,
> SMU_FEATURE_FAN_CONTROL_BIT))
> + ret = -EINVAL;
> break;
> case AMD_FAN_CTRL_MANUAL:
> ret = smu_v13_0_auto_fan_control(smu, 0);
Re: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on smu13
On 8/8/2023 1:21 PM, Kenneth Feng wrote:
disallow the fan setting if there is no fan on smu13
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 9b62b45ebb7f..09ef0a7e7679 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1131,7 +1131,9 @@ smu_v13_0_display_clock_voltage_request(struct
smu_context *smu,
uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
{
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ return AMD_FAN_CTRL_NONE;
If there is no PMFW fan control, isn't it better to set pm.no_fan?
Thanks,
Lijo
+ else if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
return AMD_FAN_CTRL_MANUAL;
else
return AMD_FAN_CTRL_AUTO;
@@ -1143,7 +1145,7 @@ smu_v13_0_auto_fan_control(struct smu_context *smu, bool
auto_fan_control)
int ret = 0;
if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
- return 0;
+ return -EINVAL;
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
if (ret)
@@ -1204,7 +1206,8 @@ smu_v13_0_set_fan_control_mode(struct smu_context *smu,
switch (mode) {
case AMD_FAN_CTRL_NONE:
- ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
+ if (smu_cmn_feature_is_supported(smu,
SMU_FEATURE_FAN_CONTROL_BIT))
+ ret = -EINVAL;
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v13_0_auto_fan_control(smu, 0);
RE: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0 v13_0_10
[AMD Official Use Only - General]
OK, will do
-
Best Regards,
Thomas
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, August 8, 2023 5:50 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chai, Thomas ; Yang,
Stanley ; Chai, Thomas ; Li, Candice
Subject: RE: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0
v13_0_10
[AMD Official Use Only - General]
Like other psp callback helper defined in amdgpu_psp.h, let's define a macro
called psp_fatal_error_recovery_quirk to wrap the psp function
(psp_v13_0_fatal_error_recovery_quirk)
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of YiPeng Chai
Sent: Tuesday, August 8, 2023 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chai, Thomas ; Yang,
Stanley ; Chai, Thomas ; Li, Candice
; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0 v13_0_10
Mode1 reset needs to recover mp1 in fatal error case for mp0 v13_0_10.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 24 +++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index e8cbfacb5ac1..763242d702c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -127,6 +127,7 @@ struct psp_funcs
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
+ int (*pre_mode1_reset)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
int (*mem_training)(struct psp_context *psp, uint32_t ops);
uint32_t (*ring_get_wptr)(struct psp_context *psp); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 50c38f75769c..f59f0cc2ab5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2066,6 +2066,9 @@ static void amdgpu_ras_do_recovery(struct work_struct
*work)
if (ras->gpu_reset_flags &
AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
ras->gpu_reset_flags &=
~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
set_bit(AMDGPU_NEED_FULL_RESET,
_context.flags);
+
+ if (adev->psp.funcs &&
adev->psp.funcs->pre_mode1_reset)
+
adev->psp.funcs->pre_mode1_reset(>psp);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 58db1ee631b3..65c44c7d2b12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -691,6 +691,27 @@ static int psp_v13_0_vbflash_status(struct psp_context
*psp)
return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); }
+static int psp_v13_0_pre_mode1_reset(struct psp_context *psp) {
+ struct amdgpu_device *adev = psp->adev;
+
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
+ uint32_t reg_data;
+ /* MP1 fatal error: trigger PSP dram read to unhalt PSP
+* during MP1 triggered sync flood.
+*/
+ reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
+
+ /* delay 1000ms for the mode1 reset for fatal error
+* to be recovered back.
+*/
+ msleep(1000);
+ }
+
+ return 0;
+}
+
static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, @@ -710,7 +731,8
@@ static const struct psp_funcs psp_v13_0_funcs = {
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
.update_spirom = psp_v13_0_update_spirom,
- .vbflash_stat = psp_v13_0_vbflash_status
+ .vbflash_stat = psp_v13_0_vbflash_status,
+ .pre_mode1_reset = psp_v13_0_pre_mode1_reset,
};
void psp_v13_0_set_psp_funcs(struct psp_context *psp)
--
2.34.1
RE: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0 v13_0_10
[AMD Official Use Only - General]
Like other psp callback helper defined in amdgpu_psp.h, let's define a macro
called psp_fatal_error_recovery_quirk to wrap the psp function
(psp_v13_0_fatal_error_recovery_quirk)
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of YiPeng Chai
Sent: Tuesday, August 8, 2023 16:02
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chai, Thomas ; Yang,
Stanley ; Chai, Thomas ; Li, Candice
; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0 v13_0_10
Mode1 reset needs to recover mp1 in fatal error case for mp0 v13_0_10.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 24 +++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index e8cbfacb5ac1..763242d702c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -127,6 +127,7 @@ struct psp_funcs
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
+ int (*pre_mode1_reset)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
int (*mem_training)(struct psp_context *psp, uint32_t ops);
uint32_t (*ring_get_wptr)(struct psp_context *psp); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 50c38f75769c..f59f0cc2ab5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2066,6 +2066,9 @@ static void amdgpu_ras_do_recovery(struct work_struct
*work)
if (ras->gpu_reset_flags &
AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
ras->gpu_reset_flags &=
~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
set_bit(AMDGPU_NEED_FULL_RESET,
_context.flags);
+
+ if (adev->psp.funcs &&
adev->psp.funcs->pre_mode1_reset)
+
adev->psp.funcs->pre_mode1_reset(>psp);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 58db1ee631b3..65c44c7d2b12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -691,6 +691,27 @@ static int psp_v13_0_vbflash_status(struct psp_context
*psp)
return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); }
+static int psp_v13_0_pre_mode1_reset(struct psp_context *psp) {
+ struct amdgpu_device *adev = psp->adev;
+
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
+ uint32_t reg_data;
+ /* MP1 fatal error: trigger PSP dram read to unhalt PSP
+* during MP1 triggered sync flood.
+*/
+ reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
+
+ /* delay 1000ms for the mode1 reset for fatal error
+* to be recovered back.
+*/
+ msleep(1000);
+ }
+
+ return 0;
+}
+
static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, @@ -710,7 +731,8
@@ static const struct psp_funcs psp_v13_0_funcs = {
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
.update_spirom = psp_v13_0_update_spirom,
- .vbflash_stat = psp_v13_0_vbflash_status
+ .vbflash_stat = psp_v13_0_vbflash_status,
+ .pre_mode1_reset = psp_v13_0_pre_mode1_reset,
};
void psp_v13_0_set_psp_funcs(struct psp_context *psp)
--
2.34.1
RE: [PATCH] drm/amdgpu: Extend poison mode check to SDMA/VCN/JPEG
[AMD Official Use Only - General] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Candice Li Sent: Tuesday, August 8, 2023 17:04 To: amd-gfx@lists.freedesktop.org Cc: Li, Candice Subject: [PATCH] drm/amdgpu: Extend poison mode check to SDMA/VCN/JPEG Treat SDMA/VCN/JPEG as RAS capable IP blocks in poison mode. Signed-off-by: Candice Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index bb29cb57add5a0..8e9cd05dee245a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3143,7 +3143,10 @@ int amdgpu_ras_is_supported(struct amdgpu_device *adev, * that the ras block supports ras function. */ if (!ret && - block == AMDGPU_RAS_BLOCK__GFX && + (block == AMDGPU_RAS_BLOCK__GFX || +block == AMDGPU_RAS_BLOCK__SDMA || +block == AMDGPU_RAS_BLOCK__VCN || +block == AMDGPU_RAS_BLOCK__JPEG) && amdgpu_ras_is_poison_mode_supported(adev) && amdgpu_ras_get_ras_block(adev, block, 0)) ret = 1; -- 2.25.1
[PATCH] drm/amdgpu: Extend poison mode check to SDMA/VCN/JPEG
Treat SDMA/VCN/JPEG as RAS capable IP blocks in poison mode. Signed-off-by: Candice Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index bb29cb57add5a0..8e9cd05dee245a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3143,7 +3143,10 @@ int amdgpu_ras_is_supported(struct amdgpu_device *adev, * that the ras block supports ras function. */ if (!ret && - block == AMDGPU_RAS_BLOCK__GFX && + (block == AMDGPU_RAS_BLOCK__GFX || +block == AMDGPU_RAS_BLOCK__SDMA || +block == AMDGPU_RAS_BLOCK__VCN || +block == AMDGPU_RAS_BLOCK__JPEG) && amdgpu_ras_is_poison_mode_supported(adev) && amdgpu_ras_get_ras_block(adev, block, 0)) ret = 1; -- 2.25.1
RE: [PATCH] fix throttle_status for other than MP0 11.0.7
[AMD Official Use Only - General]
Reviewed-by: Evan Quan
> -Original Message-
> From: Umio Yasuno
> Sent: Tuesday, August 8, 2023 2:41 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Quan, Evan
> ; Limonciello, Mario
> Subject: [PATCH] fix throttle_status for other than MP0 11.0.7
>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2720
> Signed-off-by: Umio Yasuno
> ---
> .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 85d53597e..548d25cf3 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -578,7 +578,9 @@ static int sienna_cichlid_tables_init(struct
> smu_context *smu)
> return -ENOMEM;
> }
>
> -static uint32_t sienna_cichlid_get_throttler_status_locked(struct
> smu_context *smu)
> +static uint32_t sienna_cichlid_get_throttler_status_locked(struct
> smu_context *smu,
> +bool
> use_metrics_v3,
> +bool
> use_metrics_v2)
> {
> struct smu_table_context *smu_table= >smu_table;
> SmuMetricsExternal_t *metrics_ext =
> @@ -586,13 +588,11 @@ static uint32_t
> sienna_cichlid_get_throttler_status_locked(struct smu_context *s
> uint32_t throttler_status = 0;
> int i;
>
> - if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))
> &&
> - (smu->smc_fw_version >= 0x3A4900)) {
> + if (use_metrics_v3) {
> for (i = 0; i < THROTTLER_COUNT; i++)
> throttler_status |=
> (metrics_ext-
> >SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
> - } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11,
> 0, 7)) &&
> - (smu->smc_fw_version >= 0x3A4300)) {
> + } else if (use_metrics_v2) {
> for (i = 0; i < THROTTLER_COUNT; i++)
> throttler_status |=
> (metrics_ext-
> >SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
> @@ -854,7 +854,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct
> smu_context *smu,
> metrics->TemperatureVrSoc) *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> break;
> case METRICS_THROTTLER_STATUS:
> - *value = sienna_cichlid_get_throttler_status_locked(smu);
> + *value = sienna_cichlid_get_throttler_status_locked(smu,
> use_metrics_v3, use_metrics_v2);
> break;
> case METRICS_CURR_FANSPEED:
> *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
> @@ -4056,7 +4056,7 @@ static ssize_t
> sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3-
> >CurrClock[PPCLK_DCLK_1] :
> use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
> metrics->CurrClock[PPCLK_DCLK_1];
>
> - gpu_metrics->throttle_status =
> sienna_cichlid_get_throttler_status_locked(smu);
> + gpu_metrics->throttle_status =
> sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3,
> use_metrics_v2);
> gpu_metrics->indep_throttle_status =
> smu_cmn_get_indep_throttler_status(gpu_metrics-
> >throttle_status,
>
> sienna_cichlid_throttler_map);
> --
> 2.40.1
>
[PATCH] drm/amdgpu: mode1 reset needs to recover mp1 for mp0 v13_0_10
Mode1 reset needs to recover mp1 in fatal error case
for mp0 v13_0_10.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 24 +++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index e8cbfacb5ac1..763242d702c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -127,6 +127,7 @@ struct psp_funcs
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
+ int (*pre_mode1_reset)(struct psp_context *psp);
int (*mode1_reset)(struct psp_context *psp);
int (*mem_training)(struct psp_context *psp, uint32_t ops);
uint32_t (*ring_get_wptr)(struct psp_context *psp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 50c38f75769c..f59f0cc2ab5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2066,6 +2066,9 @@ static void amdgpu_ras_do_recovery(struct work_struct
*work)
if (ras->gpu_reset_flags &
AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
ras->gpu_reset_flags &=
~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
set_bit(AMDGPU_NEED_FULL_RESET,
_context.flags);
+
+ if (adev->psp.funcs &&
adev->psp.funcs->pre_mode1_reset)
+
adev->psp.funcs->pre_mode1_reset(>psp);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 58db1ee631b3..65c44c7d2b12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -691,6 +691,27 @@ static int psp_v13_0_vbflash_status(struct psp_context
*psp)
return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
}
+static int psp_v13_0_pre_mode1_reset(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
+ uint32_t reg_data;
+ /* MP1 fatal error: trigger PSP dram read to unhalt PSP
+* during MP1 triggered sync flood.
+*/
+ reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
+
+ /* delay 1000ms for the mode1 reset for fatal error
+* to be recovered back.
+*/
+ msleep(1000);
+ }
+
+ return 0;
+}
+
static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
@@ -710,7 +731,8 @@ static const struct psp_funcs psp_v13_0_funcs = {
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
.update_spirom = psp_v13_0_update_spirom,
- .vbflash_stat = psp_v13_0_vbflash_status
+ .vbflash_stat = psp_v13_0_vbflash_status,
+ .pre_mode1_reset = psp_v13_0_pre_mode1_reset,
};
void psp_v13_0_set_psp_funcs(struct psp_context *psp)
--
2.34.1
[PATCH] drm/amd/pm: disallow the fan setting if there is no fan on smu13
disallow the fan setting if there is no fan on smu13
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 9b62b45ebb7f..09ef0a7e7679 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1131,7 +1131,9 @@ smu_v13_0_display_clock_voltage_request(struct
smu_context *smu,
uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
{
- if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ return AMD_FAN_CTRL_NONE;
+ else if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
return AMD_FAN_CTRL_MANUAL;
else
return AMD_FAN_CTRL_AUTO;
@@ -1143,7 +1145,7 @@ smu_v13_0_auto_fan_control(struct smu_context *smu, bool
auto_fan_control)
int ret = 0;
if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
- return 0;
+ return -EINVAL;
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT,
auto_fan_control);
if (ret)
@@ -1204,7 +1206,8 @@ smu_v13_0_set_fan_control_mode(struct smu_context *smu,
switch (mode) {
case AMD_FAN_CTRL_NONE:
- ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
+ if (smu_cmn_feature_is_supported(smu,
SMU_FEATURE_FAN_CONTROL_BIT))
+ ret = -EINVAL;
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v13_0_auto_fan_control(smu, 0);
--
2.34.1
[PATCH] fix throttle_status for other than MP0 11.0.7
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2720
Signed-off-by: Umio Yasuno
---
.../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 85d53597e..548d25cf3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -578,7 +578,9 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
return -ENOMEM;
}
-static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context
*smu)
+static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context
*smu,
+ bool use_metrics_v3,
+ bool use_metrics_v2)
{
struct smu_table_context *smu_table= >smu_table;
SmuMetricsExternal_t *metrics_ext =
@@ -586,13 +588,11 @@ static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *s
uint32_t throttler_status = 0;
int i;
- if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
-(smu->smc_fw_version >= 0x3A4900)) {
+ if (use_metrics_v3) {
for (i = 0; i < THROTTLER_COUNT; i++)
throttler_status |=
(metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
- } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0,
7)) &&
-(smu->smc_fw_version >= 0x3A4300)) {
+ } else if (use_metrics_v2) {
for (i = 0; i < THROTTLER_COUNT; i++)
throttler_status |=
(metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
@@ -854,7 +854,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct
smu_context *smu,
metrics->TemperatureVrSoc) *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
case METRICS_THROTTLER_STATUS:
- *value = sienna_cichlid_get_throttler_status_locked(smu);
+ *value = sienna_cichlid_get_throttler_status_locked(smu,
use_metrics_v3, use_metrics_v2);
break;
case METRICS_CURR_FANSPEED:
*value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
@@ -4056,7 +4056,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk1 = use_metrics_v3 ?
metrics_v3->CurrClock[PPCLK_DCLK_1] :
use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
metrics->CurrClock[PPCLK_DCLK_1];
- gpu_metrics->throttle_status =
sienna_cichlid_get_throttler_status_locked(smu);
+ gpu_metrics->throttle_status =
sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
gpu_metrics->indep_throttle_status =
smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
sienna_cichlid_throttler_map);
--
2.40.1
[PATCH] fix throttle_status for other than MP0 11.0.7
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2720
Signed-off-by: Umio Yasuno
---
.../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 85d53597e..548d25cf3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -578,7 +578,9 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
return -ENOMEM;
}
-static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context
*smu)
+static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context
*smu,
+ bool use_metrics_v3,
+ bool use_metrics_v2)
{
struct smu_table_context *smu_table= >smu_table;
SmuMetricsExternal_t *metrics_ext =
@@ -586,13 +588,11 @@ static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *s
uint32_t throttler_status = 0;
int i;
- if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
-(smu->smc_fw_version >= 0x3A4900)) {
+ if (use_metrics_v3) {
for (i = 0; i < THROTTLER_COUNT; i++)
throttler_status |=
(metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
- } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0,
7)) &&
-(smu->smc_fw_version >= 0x3A4300)) {
+ } else if (use_metrics_v2) {
for (i = 0; i < THROTTLER_COUNT; i++)
throttler_status |=
(metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
@@ -854,7 +854,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct
smu_context *smu,
metrics->TemperatureVrSoc) *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
case METRICS_THROTTLER_STATUS:
- *value = sienna_cichlid_get_throttler_status_locked(smu);
+ *value = sienna_cichlid_get_throttler_status_locked(smu,
use_metrics_v3, use_metrics_v2);
break;
case METRICS_CURR_FANSPEED:
*value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
@@ -4056,7 +4056,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk1 = use_metrics_v3 ?
metrics_v3->CurrClock[PPCLK_DCLK_1] :
use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
metrics->CurrClock[PPCLK_DCLK_1];
- gpu_metrics->throttle_status =
sienna_cichlid_get_throttler_status_locked(smu);
+ gpu_metrics->throttle_status =
sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
gpu_metrics->indep_throttle_status =
smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
sienna_cichlid_throttler_map);
--
2.40.1
RE: [PATCH] drm/amdgpu/irq: Move irq resume to the beginning
[AMD Official Use Only - General]
Ping.
>-Original Message-
>From: Emily Deng
>Sent: Monday, August 7, 2023 1:11 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH] drm/amdgpu/irq: Move irq resume to the beginning
>
>Need to move irq resume to the beginning of reset sriov, or if one interrupt
>occurs before irq resume, then the irq won't work anymore.
>
>Signed-off-by: Emily Deng
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 1338489b0b2f..8b304fdfe6db 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -4617,6 +4617,7 @@ static int amdgpu_device_reset_sriov(struct
>amdgpu_device *adev,
> r = amdgpu_virt_reset_gpu(adev);
> if (r)
> return r;
>+ amdgpu_irq_gpu_reset_resume_helper(adev);
>
> /* some sw clean up VF needs to do before recover */
> amdgpu_virt_post_reset(adev);
>@@ -4646,7 +4647,6 @@ static int amdgpu_device_reset_sriov(struct
>amdgpu_device *adev,
> amdgpu_put_xgmi_hive(hive);
>
> if (!r) {
>- amdgpu_irq_gpu_reset_resume_helper(adev);
> r = amdgpu_ib_ring_tests(adev);
>
> amdgpu_amdkfd_post_reset(adev);
>--
>2.36.1
Re: [PATCH 4/4] drm/amdgpu: use a macro to define no xcp partition case
Am 18.07.23 um 07:13 schrieb Guchun Chen:
~0 as no xcp partition is used in several places, so improve its
definition by a macro for code consistency.
Suggested-by: Christian König
Signed-off-by: Guchun Chen
Reviewed-by: Felix Kuehling
I guess you already pushed this, so just for the record: Reviewed-by:
Christian König .
I need to get faster catching up on mails,
Christian.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 ++
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 4 ++--
4 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index a7f314ddd173..d34c3ef8f3ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1709,7 +1709,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC)
?
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
}
- xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id;
+ xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
+ 0 : fpriv->xcp_id;
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_flags = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
index d175e862f222..9c9cca129498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -363,7 +363,7 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
if (!adev->xcp_mgr)
return 0;
- fpriv->xcp_id = ~0;
+ fpriv->xcp_id = AMDGPU_XCP_NO_PARTITION;
for (i = 0; i < MAX_XCP; ++i) {
if (!adev->xcp_mgr->xcp[i].ddev)
break;
@@ -381,7 +381,7 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
}
}
- fpriv->vm.mem_id = fpriv->xcp_id == ~0 ? -1 :
+ fpriv->vm.mem_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? -1 :
adev->xcp_mgr->xcp[fpriv->xcp_id].mem_id;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 0f8026d64ea5..9a1036aeec2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -37,6 +37,8 @@
#define AMDGPU_XCP_FL_NONE 0
#define AMDGPU_XCP_FL_LOCKED (1 << 0)
+#define AMDGPU_XCP_NO_PARTITION (~0)
+
struct amdgpu_fpriv;
enum AMDGPU_XCP_IP_BLOCK {
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 16471b81a1f5..72b629a78c62 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -68,7 +68,7 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device
*adev,
enum AMDGPU_XCP_IP_BLOCK ip_blk;
uint32_t inst_mask;
- ring->xcp_id = ~0;
+ ring->xcp_id = AMDGPU_XCP_NO_PARTITION;
if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE)
return;
@@ -177,7 +177,7 @@ static int aqua_vanjaram_select_scheds(
u32 sel_xcp_id;
int i;
- if (fpriv->xcp_id == ~0) {
+ if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) {
u32 least_ref_cnt = ~0;
fpriv->xcp_id = 0;
