Fixes the following W=1 kernel build warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_optc.c:46: warning: This
comment starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
* Enable CRTC
Cc: Qingqing Zhuo
Cc: Rodrigo Siqueira
Cc: Harry
Acked-by: Alex Deucher
On Fri, Aug 25, 2023 at 4:10 PM David Francis wrote:
>
> The code in kfd_mqd_manager_v11.c to support criu dump and
> restore of queue state was missing.
>
> Added it; should be equivalent to kfd_mqd_manager_v10.c.
>
> CC: Felix Kuehling
> Signed-off-by: David Francis
>
Acked-by: Alex Deucher
On Mon, Aug 28, 2023 at 2:50 AM ZhenGuo Yin wrote:
>
> Register RLC_SPM_MC_CNTL is not blocked by L1 policy, VF can
> directly access it through MMIO.
>
> Signed-off-by: ZhenGuo Yin
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++
>
On 2023-08-28 16:57, Chen, Xiaogang wrote:
On 8/28/2023 2:06 PM, Felix Kuehling wrote:
On 2023-08-24 18:08, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according
to migration
granularity(default 2MB) and not split svm range in cpu
On 8/28/2023 2:06 PM, Felix Kuehling wrote:
On 2023-08-24 18:08, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according
to migration
granularity(default 2MB) and not split svm range in cpu page fault
handling.
Now a svm range may
On 28/08/2023 17:14, Yadav, Arvind wrote:
On 8/28/2023 9:13 PM, Helen Mae Koike Fornazier wrote:
On Monday, August 28, 2023 09:26 -03, Arvind Yadav
wrote:
AMDGPU SOCs supports dynamic workload based power profiles, which can
provide fine-tuned performance for a particular type of
On 8/28/2023 9:13 PM, Helen Mae Koike Fornazier wrote:
On Monday, August 28, 2023 09:26 -03, Arvind Yadav wrote:
AMDGPU SOCs supports dynamic workload based power profiles, which can
provide fine-tuned performance for a particular type of workload.
This patch series adds an interface to
On 2023-08-24 18:08, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according to migration
granularity(default 2MB) and not split svm range in cpu page fault handling.
Now a svm range may have pages from both system ram and vram of one gpu.
[AMD Official Use Only - General]
Technically the AMD IOMMU uses direct mapping mode for any device which claims
to support ATS in order to support the IOMMUv2 functionality, but that was also
the case with Raven systems which were problematic when remapping mode was
enabled. That said, now
On 2023-08-25 17:30, Harish Kasiviswanathan wrote:
From: Jay Cornwall
mqd_stride function was introduced in commit 129c7b6a0217
("drm/amdkfd: Update MQD management on multi XCC setup")
but not assigned for gfx11. Fixes a NULL dereference in debugfs.
Signed-off-by: Jay Cornwall
Signed-off-by:
On 2023-08-28 11:35, Alex Sierra wrote:
Interrupt sq data bits were not taken properly from contextid0 and contextid1.
Use macro KFD_CONTEXT_ID_GET_SQ_INT_DATA instead.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 2 +-
On 2023-08-26 09:41, Asad Kamal wrote:
Replace pr_err with dev_err to show the bus-id of
failing device with kfd queue errors
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
Reviewed-by: Felix Kuehling
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 116 +++---
On 8/24/23 14:07, Lee Jones wrote:
> On Thu, 24 Aug 2023, Jani Nikula wrote:
>> On Thu, 24 Aug 2023, Lee Jones wrote:
>>> This set is part of a larger effort attempting to clean-up W=1
>>> kernel builds, which are currently overwhelmingly riddled with
>>> niggly little warnings.
>>
>> The next
On Monday, August 28, 2023 09:26 -03, Arvind Yadav wrote:
> AMDGPU SOCs supports dynamic workload based power profiles, which can
> provide fine-tuned performance for a particular type of workload.
> This patch series adds an interface to set/reset these power profiles
> based on the submitted
Interrupt sq data bits were not taken properly from contextid0 and contextid1.
Use macro KFD_CONTEXT_ID_GET_SQ_INT_DATA instead.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 2023-08-10 12:13, Harish
Kasiviswanathan wrote:
No functional change. Use ratelimited version of pr_ to avoid
overflowing of dmesg buffer
Signed-off-by: Harish Kasiviswanathan
Reviewed-by: Philip Yang
---
[AMD Official Use Only - General]
As mentioned with an older version of this series, this is an 'abuse' of power
profile interface.
This series is oversimplifying what PMFW algorithms are supposed to be doing.
Whatever this series is doing, FW can do it better.
To explain in simpler terms -
[AMD Official Use Only - General]
Reviewed-by: Harish Kasiviswanathan
-Original Message-
From: amd-gfx On Behalf Of David Francis
Sent: Friday, August 25, 2023 3:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Francis, David ; Kuehling, Felix
Subject: [PATCH] drm/amdkfd: Checkpoint and
On 08/28, Pekka Paalanen wrote:
> On Mon, 28 Aug 2023 09:45:44 +0100
> Joshua Ashton wrote:
>
> > Degamma has always been on the plane on AMD. CRTC DEGAMMA_LUT has actually
> > just been applying it to every plane pre-blend.
>
> I've never seen that documented anywhere.
>
> It has seemed
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Harish
Kasiviswanathan
Sent: Friday, August 25, 2023 5:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Cornwall, Jay ; Kasiviswanathan, Harish
Subject: [PATCH] drm/amdkfd: Add
On Fri, 25 Aug 2023 13:37:08 -0100
Melissa Wen wrote:
> On 08/22, Pekka Paalanen wrote:
> > On Thu, 10 Aug 2023 15:03:11 -0100
> > Melissa Wen wrote:
> >
> > > dc->caps.color.mpc.gamut_remap says there is a post-blending color block
> > > for gamut remap matrix for DCN3 HW family and newer
On Mon, 28 Aug 2023 09:45:44 +0100
Joshua Ashton wrote:
> Degamma has always been on the plane on AMD. CRTC DEGAMMA_LUT has actually
> just been applying it to every plane pre-blend.
I've never seen that documented anywhere.
It has seemed obvious, that since we have KMS objects for planes and
On Fri, 25 Aug 2023 13:29:44 -0100
Melissa Wen wrote:
> On 08/22, Pekka Paalanen wrote:
> > On Thu, 10 Aug 2023 15:02:59 -0100
> > Melissa Wen wrote:
> >
> > > The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
> > > pre-blending degamma caps (DPP) is currently in use
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
*
This reverts commit 5ce71f59bb9bd3d8a09b96afdbc92975cb6dc303.
Reason for revert: New amdgpu_workload_profile* api is added
to switch on/off profile mode. These new api will allow to
change the GPU power profile based on a submitted job.
Cc: Christian Koenig
Cc: Alex Deucher
Acked-by: Shashank
This patch switches the GPU workload mode to/from
compute mode, while submitting compute workload.
v3:
- Addressed the review comment about changing the
function name from *_set() to *_get().
Cc: Christian Koenig
Signed-off-by: Alex Deucher
Reviewed-by: Shashank Sharma
Signed-off-by: Arvind
This patch is to switch the GPU workload profile based
on the submitted job. The workload profile is reset to
default when the job is done.
v3:
- Addressed the review comment about changing the function
name from *_set() to *_get().
Cc: Christian Koenig
Cc: Alex Deucher
Reviewed-by: Shashank
This patch adds a suspend function that will clear the GPU
power profile before going into suspend state.
v2:
- Add the new suspend function based on review comment.
v3:
- Adressed the review comment.
- Now clearing all the profile in work handler.
Cc: Shashank Sharma
Cc: Christian Koenig
Cc:
This patch adds a function which will clear the GPU
power profile after job finished.
This is how it works:
- schedular will set the GPU power profile based on ring_type.
- Schedular will clear the GPU Power profile once job finished.
- Here, the *_workload_profile_set function will set the GPU
This patch adds a function which will change the GPU
power profile based on a submitted job. This can optimize
the power performance when the workload is on.
v2:
- Splitting workload_profile_set and workload_profile_put
into two separate patches.
- Addressed review comment.
v3:
- Adressed all
The'struct amdgpu_smu_workload' initialization/cleanup
functions is added by this patch.
v2:
- Splitting big patch into separate patches.
- Added new fini function.
v3:
- Addressed review comment to change 'power_profile_work'
instead of 'smu_delayed_work'.
Cc: Christian Koenig
Cc: Alex
AMDGPU SOCs supports dynamic workload based power profiles, which can
provide fine-tuned performance for a particular type of workload.
This patch series adds an interface to set/reset these power profiles
based on the submitted job. The driver can dynamically switch
the power profiles based on
Well, there seems to be a very basic misunderstood here: The IOMMU
isolation level is *not* ASIC dependent!
Try to set amd_iommu=force_isolation on the kernel command line.
This is a configuration option customers can use to harden their systems
and when this isn't properly tested we can't
[Public]
Not yet. It will be only enabled for gfx10.3.3 and later APU initially, IOMMU
is pass through in these ASIC.
-Original Message-
From: Christian König
Sent: Monday, August 28, 2023 5:41 PM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig,
Am 28.08.23 um 12:02 schrieb Ma Jun:
Simplify the code logic of size check function amdgpu_bo_validate_size
Signed-off-by: Ma Jun
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 29 +-
1 file changed, 12 insertions(+), 17 deletions(-)
Simplify the code logic of size check function amdgpu_bo_validate_size
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 29 +-
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
Is that now validated with IOMMU in non pass through mode?
Christian.
Am 28.08.23 um 10:58 schrieb Zhang, Yifan:
[AMD Official Use Only - General]
Ping
-Original Message-
From: Zhang, Yifan
Sent: Friday, August 25, 2023 8:34 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher,
Register RLC_SPM_MC_CNTL is not blocked by L1 policy, VF can
directly access it through MMIO during SRIOV runtime.
v2: use SOC15 interface to access registers
Signed-off-by: ZhenGuo Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13
[AMD Official Use Only - General]
Ping
-Original Message-
From: Zhang, Yifan
Sent: Friday, August 25, 2023 8:34 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Zhang, Yifan
Subject: [PATCH v3 2/2] drm/amdgpu: Put page tables to GTT memory for gfx10
Degamma has always been on the plane on AMD. CRTC DEGAMMA_LUT has actually
just been applying it to every plane pre-blend.
Degamma makes no sense after blending anyway.
The entire point is for it to happen before blending to blend in linear
space. Otherwise DEGAMMA_LUT and REGAMMA_LUT are the
Am 17.08.23 um 09:00 schrieb Yifan Zhang:
amdgpu_vm is not used in amdgpu_vmid_grab_idle.
Signed-off-by: Yifan Zhang
Sorry for the delay, Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
On 8/28/2023 2:00 PM, Christian König wrote:
> Am 28.08.23 um 07:09 schrieb Ma, Jun:
>> Hi Christian,
>>
>> On 8/25/2023 4:08 PM, Christian König wrote:
>>>
>>> Am 25.08.23 um 07:22 schrieb Ma Jun:
Simplify the code logic of size check function amdgpu_bo_validate_size
Register RLC_SPM_MC_CNTL is not blocked by L1 policy, VF can
directly access it through MMIO.
Signed-off-by: ZhenGuo Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 ++
2 files changed, 4 insertions(+), 16 deletions(-)
diff
Am 28.08.23 um 07:09 schrieb Ma, Jun:
Hi Christian,
On 8/25/2023 4:08 PM, Christian König wrote:
Am 25.08.23 um 07:22 schrieb Ma Jun:
Simplify the code logic of size check function amdgpu_bo_validate_size
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28
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