[AMD Official Use Only - General]
Hi Felix,
Yes, will correct the description. Will add another patch to handle the
return for sync wait.
Emily Deng
Best Wishes
>-Original Message-
>From: Kuehling, Felix
>Sent: Friday, October 20, 2023 12:05 AM
>To: Deng, Emily ;
Since the script that collected the list of the expectation files was
bogus and placing test to the flakes list incorrectly, restart the
expectation files with the correct script.
This reduces a lot the number of tests in the flakes list.
Signed-off-by: Helen Koike
Reviewed-by: David Heidelberg
Hi Dave, Sima,
Fixes for 6.6.
The following changes since commit 58720809f52779dc0f08e53e54b014209d13eebb:
Linux 6.6-rc6 (2023-10-15 13:34:39 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.6-2023-10-19
for you to fetch
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4230ea146b1e64628f11e44290bb4008e391bc24 Add linux-next specific
files for 20231019
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202309200103.grxwdktx-...@intel.com
https
On Thu, Oct 19, 2023 at 05:32:05PM +0200, Heiko Carstens wrote:
> On Thu, Oct 19, 2023 at 04:07:35AM +0800, kernel test robot wrote:
> > arch/s390/include/asm/ctlreg.h:129:9: warning: array subscript 0 is outside
> > array bounds of 'struct ctlreg[0]' [-Warray-bounds=]
> >
On 2023-10-19 16:51, Alex Sierra wrote:
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
On 2023-10-19 16:53, Philip Yang wrote:
On 2023-10-19 16:05, Felix Kuehling wrote:
On 2023-10-18 18:26, Alex Sierra wrote:
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition
On 2023-10-19 16:05, Felix Kuehling
wrote:
On 2023-10-18 18:26, Alex Sierra wrote:
Split SVM ranges that have been mapped
into 2MB page table entries,
require to be remap in case the split has happened in a
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 43
On 10/19/2023 2:40 PM, Philip Yang wrote:
On 2023-10-19 12:20, Chen, Xiaogang wrote:
On 10/19/2023 11:08 AM, Philip Yang wrote:
On 2023-10-19 10:24, Xiaogang.Chen wrote:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does
GPU vm
space mapping for
On 2023-10-18 18:26, Alex Sierra wrote:
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
---
On 2023-10-19 12:20, Chen, Xiaogang
wrote:
On 10/19/2023 11:08 AM, Philip Yang wrote:
On 2023-10-19 10:24, Xiaogang.Chen wrote:
From: Xiaogang
Chen
On 2023-10-18 21:56, Jesse Zhang wrote:
[ 567.613292] shift exponent 255 is too large for 64-bit type 'long unsigned int'
[ 567.614498] CPU: 5 PID: 238 Comm: kworker/5:1 Tainted: G OE 6.2.0-34-generic #34~22.04.1-Ubuntu
[ 567.614502] Hardware
On 10/19/2023 11:08 AM, Philip Yang wrote:
On 2023-10-19 10:24, Xiaogang.Chen wrote:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does GPU vm
space mapping for same page range that got migrated instead of mapping all
pages of svm range in which the page
On 2023-10-19 10:24, Xiaogang.Chen
wrote:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does GPU vm
space mapping for same page range that got migrated instead of mapping all
pages of svm range in which the page fault
On 2023-10-19 05:31, Emily Deng wrote:
Issue: Dead heappen during gpu recover
[56433.829492] amdgpu :04:00.0: amdgpu: GPU reset begin!
[56550.499625] INFO: task kworker/u80:0:10 blocked for more than 120 seconds.
[56550.520215] Tainted: G OE 6.2.0-34-generic
On 2023-10-19 09:32, David Francis wrote:
On gfx943 APU, EXT_COHERENT should give MTYPE_CC for local and
MTYPE_UC for nonlocal memory.
On NUMA systems, local memory gets the local mtype, set by an
override callback. If EXT_COHERENT is set, memory will be set as
MTYPE_UC by default, with local
On Thu, Oct 19, 2023 at 04:07:35AM +0800, kernel test robot wrote:
> arch/s390/include/asm/ctlreg.h:129:9: warning: array subscript 0 is outside
> array bounds of 'struct ctlreg[0]' [-Warray-bounds=]
> arch/s390/include/asm/ctlreg.h:80:9: warning: array subscript 0 is outside
> array bounds of
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Stanley.Yang
Sent: Thursday, October 19, 2023 22:52
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Stanley
Subject: [PATCH Review 1/1] drm/amdgpu: Enable RAS
Enable RAS feature by default for aqua vanjaram on apu
platform.
Change-Id: I02105d07d169d1356251c994249a134ca5dd2a7a
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git
Applied. Thanks!
Alex
On Wed, Oct 18, 2023 at 11:38 PM Jiapeng Chong
wrote:
>
> No functional modification involved.
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2902 dm_resume()
> warn: inconsistent indenting.
>
> Reported-by: Abaci Robot
> Closes:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does GPU vm
space mapping for same page range that got migrated instead of mapping all
pages of svm range in which the page fault happened.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c |
[AMD Official Use Only - General]
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld correctable hardware errors detected in
%s block\n",
+"new %lld correctable hardware errors detected
in %s block, "
+
From: Iswara Nagulendran
[HOW]
Reading the value from
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, DPCD 0x721
before setting the
BP_EDP_PANEL_LUMINANC_CONTROL_ENABLE bit
to ensure there are no accidental overwrites.
Reviewed-by: Sreeja Golui
Reviewed-by: Harry Vanzylldejong
Acked-by: Roman Li
From: Ilya Bakoulin
[Why]
LUT params are not cleared after setting blend TF, which can lead to
same params being used for the shaper, if the shaper func is bypassed.
[How]
Set lut_params to NULL after program_1dlut.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
From: Michael Strauss
[WHY]
Currently causes some DP link layer failures, backing out until
the failures are root caused.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1
From: Samson Tam
[Why]
In cases where number of pipes available is less
than num_opp, there will opp instances that are
null
[How]
Add null check to skip over these opp instances
Fixes: 9e241124fe13 ("drm/amd/display: Update OPP counter from new interface")
Reviewed-by: Alvin Lee
Acked-by:
From: Samson Tam
[Why]
Helper function calculates num_ways using 32-bit. But is
returned as 8-bit. If num_ways exceeds 8-bit, then it
reports back the incorrect num_ways and erroneously
uses MALL when it should not
[How]
Make returned value 32-bit and convert after it checks
against
From: Aurabindo Pillai
[Why]
To enable automated testing through IGT, expose an API that is
accessible through debugfs to query current status of SubVP feature.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Aurabindo Pillai
---
From: Aric Cyr
DC v3.2.256
Summary:
* Fixes null-deref regression after
"drm/amd/display: Update OPP counter from new interface"
* Fixes display flashing when VSR and HDR enabled on dcn32
* Fixes dcn3x intermittent hangs due to FPO
* Fixes MST Multi-Stream light up on dcn35
* Fixes green
From: Alvin Lee
Provide DCN32 specific sequence and update DCN30 sequence
Reviewed-by: Samson Tam
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 21 ++---
From: Rodrigo Siqueira
This commit adds the amdgpu_dm_plane_ prefix for all functions in the
amdgpu_dm_plane.c. This change enables an easy way to filter code paths
via ftrace.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
From: Rodrigo Siqueira
The ftrace debug feature allows filtering functions based on a prefix,
which can be helpful in some complex debug scenarios. The driver can
benefit more from this feature if the function name follows some
patterns; for this reason, this commit adds the prefix
From: Rodrigo Siqueira
This commit just replaces dc_interrupt_po*r*larity with its correct
name, which is dc_interrupt_polarity.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 6 +++---
1 file changed, 3
From: Sung Joon Kim
[why]
Bandwidth validation failure on framepack tests.
Need to double pixel clock when 3D format is
framepack. Also for HDMI displays, we need to
keep the ITC flag to 1 by default.
[how]
Double the pixel clock when using framepack 3D format.
Set hdmi ITC bit to 1.
On gfx943 APU, EXT_COHERENT should give MTYPE_CC for local and
MTYPE_UC for nonlocal memory.
On NUMA systems, local memory gets the local mtype, set by an
override callback. If EXT_COHERENT is set, memory will be set as
MTYPE_UC by default, with local memory MTYPE_CC.
Add an option in the
From: Alex Hung
[WHY & HOW]
Virtual sink is not audio-capable and this causes kms_hdmi_inject's
inject-audio to fail. Set it to HDMI according to EDID.
Reviewed-by: Chao-kai Wang
Acked-by: Roman Li
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
1
From: Alex Hung
This reverts commit 4ad3ee5ccc77aa3f9d702f7b9ad4d9cfeca6c443.
[WHY & HOW]
Virtual signal is not supported as audio capable by DC.
Reviewed-by: Chao-kai Wang
Acked-by: Roman Li
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/include/signal_types.h | 1 -
1 file
From: Nicholas Kazlauskas
[Why]
Intermittent reboot hangs are observed introduced by
"Improve x86 and dmub ips handshake".
[How]
Bring back the commit but fix the polling.
Avoid hanging in place forever by bounding the delay and ensure that
we still message DMCUB on IPS2 exit to notify driver
From: Wenjing Liu
[why]
Unify pipe resource management logic in dc resource layer.
V2:
Add default case for switch.
CC: Hamza Mahfooz
Reviewed-by: Chaitanya Dhere
Signed-off-by: Wenjing Liu
Reviewed-by: Rodrigo Siqueira
Reviewed-by: Jun Lei
Acked-by: Roman Li
Signed-off-by: Qingqing Zhuo
From: George Shen
[Why]
Certain test equipment vendors check the SDP VSC for colorimetry against
the value from the test request during certain DP link layer tests for
YCbCr test cases.
[How]
Update SDP VSC with colorimetry from test automation request.
Reviewed-by: Wenjing Liu
Acked-by:
From: Wenjing Liu
[why]
Need DML2 to support new pipe resource management APIs.
Reviewed-by: Chaitanya Dhere
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +
.../drm/amd/display/dc/dcn321/dcn321_resource.c | 5 +
From: Nicholas Kazlauskas
This reverts commit 8316378d272ed96f60177cc9a8beaadb8640f745.
Causes intermittent hangs during reboot stress testing.
Reviewed-by: Duncan Ma
Acked-by: Roman Li
Signed-off-by: Nicholas Kazlauskas
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 37
From: Swapnil Patel
[Why & How]
Currently set_default_brightness_aux function uses 5 nits as lower limit
to check for valid default_backlight setting. However some newer panels
can support even lower default settings
Reviewed-by: Agustin Gutierrez
Acked-by: Roman Li
Signed-off-by: Swapnil
From: Sung Joon Kim
[why]
Need a helper function to check idle power is allowed
so that dc doesn't access any registers that are power-gated.
[how]
Implement helper function to check idle power optimization.
Enable a hook to check if detection is allowed.
V2:
Add function hooks for set and get
From: Fangzhi Zuo
dcn35 misses .enable_symclk_se hook that makes MST DSC
not functional when having multiple FE clk to be enabled.
Reviewed-by: Rodrigo Siqueira
Acked-by: Roman Li
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 6 ++
1 file
From: Agustin Gutierrez
[Why]
Some ASICs keep backlight powered on after dpms off
command has been issued.
[How]
The check for no edp power sequencing was never going to pass.
The value is never changed from what it is set by design.
Cc: sta...@vger.kernel.org #
From: Hugo Hu
[Why]
During system boot in second screen only mode on a seamless boot system,
there is a chance that the pipe's det size might not be reset.
[How]
Reset the det size while resetting the pipe during seamless boot.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Roman Li
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes null-deref regression after
"drm/amd/display: Update OPP counter from new interface"
* Fixes display flashing when VSR and HDR enabled on dcn32
* Fixes dcn3x intermittent hangs due to FPO
[AMD Official Use Only - General]
As discussed, please add socket id and die id in the output message.
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Thursday, October 19, 2023 20:51
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ;
Chai, Thomas ;
refine ras error kernel log to avoid user-ridden ambiguity.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
Am 17.10.23 um 15:04 schrieb Alex Deucher:
On Tue, Oct 17, 2023 at 8:22 AM Christian König
wrote:
Looks like RADV is actually hitting this.
Signed-off-by: Christian König
Fixes: ca6c1e210aa7 ("drm/amdgpu: use the new drm_exec object for CS v3")
Acked-by: Alex Deucher
Pushed to
In SR-IOV environment, the value of pcie_table->num_of_link_levels will
be 0, and num_of_levels - 1 will cause array index out of bounds
Signed-off-by: Lin.Cao
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Issue: Dead heappen during gpu recover
[56433.829492] amdgpu :04:00.0: amdgpu: GPU reset begin!
[56550.499625] INFO: task kworker/u80:0:10 blocked for more than 120 seconds.
[56550.520215] Tainted: G OE 6.2.0-34-generic
#34~22.04.1-Ubuntu
[56550.542883] "echo 0 >
Am 18.10.23 um 19:05 schrieb Shyam Sundar S K:
On 10/18/2023 9:37 PM, Christian König wrote:
Am 18.10.23 um 17:47 schrieb Mario Limonciello:
On 10/18/2023 08:40, Christian König wrote:
Am 18.10.23 um 11:28 schrieb Shyam Sundar S K:
On 10/18/2023 2:50 PM, Ilpo Järvinen wrote:
On Wed, 18
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/display_mode_util.c:150 dml_max()
warn: inconsistent indenting
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6933
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c | 2 +-
1 file
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2902 dm_resume()
warn: inconsistent indenting.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6940
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_policy.c:206
dml2_policy_build_synthetic_soc_states() warn: inconsistent indenting
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6933
Signed-off-by: Yang Li
---
Fixes: d479ef0d5fbd ("drm/amdgpu: add ras_err_info to identify RAS error
source")
Please add above comment.
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Stanley.Yang
Sent: Thursday, October 19, 2023 3:00 PM
To:
[AMD Official Use Only - General]
Reviewed-by: Candice Li
Thanks,
Candice
-Original Message-
From: amd-gfx On Behalf Of Yang Wang
Sent: Thursday, October 19, 2023 3:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: fix typo
typo fix.
Fixes: d479ef0d5fbd ("drm/amdgpu: add ras_err_info to identify RAS error
source")
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
Fix delete nodes that it has been freed.
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index
ping...
Any other comments?
Regards,
Ma Jun
On 10/17/2023 10:53 AM, Ma Jun wrote:
> Due to electrical and mechanical constraints in certain platform designs there
> may be likely interference of relatively high-powered harmonics of the (G-)DDR
> memory clocks with local radio module frequency
[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang
发件人: amd-gfx 代表 jiadong@amd.com
发送时间: Thursday, October 19, 2023 11:38:45 AM
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Jiadong
主题: [PATCH] drm/amd/pm: drop unneeded dpm features
[AMD Official Use Only - General]
Reviewed-by: Yifan Zhang
发件人: amd-gfx 代表 jiadong@amd.com
发送时间: Thursday, October 19, 2023 11:40:25 AM
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Jiadong
主题: [PATCH] drm/amdgpu: add tmz support for GC IP v11.5.0
From:
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