[PATCH 2/2] drm/amd/display: drop unused dm_delay_in_microseconds

[Alex Deucher]

No longer used.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 2c3cd51..43bf829 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -59,13 +59,6 @@ bool dm_read_persistent_data(struct dc_context *ctx,
return false;
 }
 
-void dm_delay_in_microseconds(struct dc_context *ctx,
-   unsigned int microSeconds)
-{
-   /*TODO implement*/
-   return;
-}
-
 / power component interfaces /
 
 bool dm_pp_pre_dce_clock_change(
-- 
2.5.5

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Re: [PATCH] drm/amd/display: Add comment for NaN checks in DCN calcs

[Alex Deucher]

On Wed, Oct 11, 2017 at 10:55 AM, Harry Wentland <harry.wentl...@amd.com> wrote:
> This is confusing as-is and really needs a comment.
>
> Signed-off-by: Harry Wentland <harry.wentl...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> index b6abe0f3bb15..f95dc4ff9a23 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> @@ -27,6 +27,7 @@
>
>  float dcn_bw_mod(const float arg1, const float arg2)
>  {
> +   /* NaN checks */
> if (arg1 != arg1)
> return arg2;
> if (arg2 != arg2)
> @@ -36,6 +37,7 @@ float dcn_bw_mod(const float arg1, const float arg2)
>
>  float dcn_bw_min2(const float arg1, const float arg2)
>  {
> +   /* NaN checks */
> if (arg1 != arg1)
> return arg2;
> if (arg2 != arg2)
> @@ -45,6 +47,7 @@ float dcn_bw_min2(const float arg1, const float arg2)
>
>  unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
>  {
> +   /* NaN checks */
> if (arg1 != arg1)
> return arg2;
> if (arg2 != arg2)
> @@ -53,6 +56,7 @@ unsigned int dcn_bw_max(const unsigned int arg1, const 
> unsigned int arg2)
>  }
>  float dcn_bw_max2(const float arg1, const float arg2)
>  {
> +   /* NaN checks */
> if (arg1 != arg1)
> return arg2;
> if (arg2 != arg2)
> --
> 2.14.1
>
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[pull] amdgpu drm-fixes-4.14

[Alex Deucher]

Hi Dave,

One memory management regression fix.

The following changes since commit 545036a9944e9d6e50fed4ca03117147c880ff71:

  Merge tag 'drm-misc-fixes-2017-10-11' of 
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2017-10-12 10:38:09 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.14

for you to fetch changes up to 27b94b4f1386c3a8181f5a0277434a32e24e7dd7:

  drm/amdgpu: fix placement flags in amdgpu_ttm_bind (2017-10-12 10:34:42 -0400)


Christian König (1):
  drm/amdgpu: fix placement flags in amdgpu_ttm_bind

 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Re: [pull] amdgpu drm-fixes-4.14

[Alex Deucher]

On Thu, Oct 12, 2017 at 1:02 PM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Am 12.10.2017 um 18:20 schrieb Michel Dänzer:
>>
>> On 12/10/17 05:58 PM, Alex Deucher wrote:
>>>
>>> Hi Dave,
>>>
>>> One memory management regression fix.
>>>
>>> The following changes since commit
>>> 545036a9944e9d6e50fed4ca03117147c880ff71:
>>>
>>>Merge tag 'drm-misc-fixes-2017-10-11' of
>>> git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2017-10-12
>>> 10:38:09 +1000)
>>>
>>> are available in the git repository at:
>>>
>>>git://people.freedesktop.org/~agd5f/linux drm-fixes-4.14
>>>
>>> for you to fetch changes up to 27b94b4f1386c3a8181f5a0277434a32e24e7dd7:
>>>
>>>drm/amdgpu: fix placement flags in amdgpu_ttm_bind (2017-10-12
>>> 10:34:42 -0400)
>>>
>>> 
>>> Christian König (1):
>>>drm/amdgpu: fix placement flags in amdgpu_ttm_bind
>>
>> Thanks Alex, but there's another piglit hang regression in 4.14, caused
>> by commit 6af0883ed977 "drm/amdgpu: discard commands of killed
>> processes", fixed by five commits 6b37d03280a4..318d85de9c20 in
>> amd-staging-drm-next. Either the latter need to be backported to 4.14,
>> or the former needs to be reverted from it.
>
>
> The revert is probably easier to handle at this point.
>
> So to answer your question from the other thread I vote for that.

Nicolai's patches apply cleanly and I think they change about the same
amount of code and we don't have to worry about any problems down the
road when the revert gets merged into drm-next.

Alex
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[PATCH] drm/amdgpu: bump version for vram lost counter query

[Alex Deucher]

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b9a3258..38cd8bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -72,9 +72,10 @@
  * - 3.20.0 - Add support for local BOs
  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
+ * - 3.23.0 - Add query for vram lost counter
  */
 #define KMS_DRIVER_MAJOR   3
-#define KMS_DRIVER_MINOR   22
+#define KMS_DRIVER_MINOR   23
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit = 0;
-- 
2.5.5

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Re: [PATCH 2/3] drm/amdgpu:fix vf_error_put

[Alex Deucher]

On Wed, Oct 18, 2017 at 5:59 AM, Monk Liu  wrote:
> it should not work on non-SR-IOV case
>
> Change-Id: Icf34f88a0642e4b04c857a07b72df3bb772075d6
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 7 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c | 7 ++-
>  2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 8354af6..c43f8d4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2049,6 +2049,9 @@ static void amdgpu_device_detect_sriov_bios(struct 
> amdgpu_device *adev)
> if (amdgpu_atombios_has_gpu_virtualization_table(adev))
> adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
> }
> +
> +   if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
> +   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);

Shouldn't this be protected with amdgpu_sriov_vf()?  Other than that,
looks good to me.

Alex

>  }
>
>  bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
> @@ -2260,7 +2263,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> if (amdgpu_vpost_needed(adev)) {
> if (!adev->bios) {
> dev_err(adev->dev, "no vBIOS found\n");
> -   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 
> 0, 0);
> r = -EINVAL;
> goto failed;
> }
> @@ -2268,7 +2270,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
> if (r) {
> dev_err(adev->dev, "gpu post error!\n");
> -   amdgpu_vf_error_put(adev, 
> AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
> goto failed;
> }
> } else {
> @@ -3096,7 +3097,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
> }
> } else {
> dev_err(adev->dev, "asic resume failed (%d).\n", r);
> -   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 
> 0, r);
> for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
> if (adev->rings[i] && adev->rings[i]->sched.thread) {
> kthread_unpark(adev->rings[i]->sched.thread);
> @@ -3114,7 +3114,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
> if (r) {
> /* bad news, how to tell it to userspace ? */
> dev_info(adev->dev, "GPU reset failed\n");
> -   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, 
> r);
> }
> else {
> dev_info(adev->dev, "GPU reset successed!\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
> index 746b813..7f70979 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
> @@ -31,7 +31,12 @@ void amdgpu_vf_error_put(struct amdgpu_device *adev,
>  uint64_t error_data)
>  {
> int index;
> -   uint16_t error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, 
> sub_error_code);
> +   uint16_t error_code;
> +
> +   if (!amdgpu_sriov_vf(adev))
> +   return;
> +
> +   error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, 
> sub_error_code);
>
> mutex_lock(>virt.vf_errors.lock);
> index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
> --
> 2.7.4
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Re: [PATCH] drm/amdgpu: drm/amdgpu: always consider virualised device for checking post (v2)

[Alex Deucher]

On Wed, Oct 18, 2017 at 9:44 PM, Pixel Ding  wrote:
> From: pding 
>
> The post checking on scratch registers isn't reliable for virtual function.
>
> v2: only change in IGP reading bios.


Subject has "drm/amdgpu: drm/amdgpu: " drop one of them.


>
> Signed-off-by: pding 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c   | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 0280ae5..caabc5b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1840,6 +1840,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>  /* Common functions */
>  int amdgpu_gpu_reset(struct amdgpu_device *adev);
>  bool amdgpu_need_backup(struct amdgpu_device *adev);
> +bool amdgpu_vpost_needed(struct amdgpu_device *adev);
>  void amdgpu_pci_config_reset(struct amdgpu_device *adev);
>  bool amdgpu_need_post(struct amdgpu_device *adev);

amdgpu_need_post can be dropped now.

>  void amdgpu_update_display_priority(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> index c21adf6..25f43eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> @@ -99,7 +99,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device 
> *adev)
> resource_size_t size = 256 * 1024; /* ??? */
>
> if (!(adev->flags & AMD_IS_APU))
> -   if (amdgpu_need_post(adev))
> +   if (amdgpu_vpost_needed(adev))
> return false;
>
> adev->bios = NULL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a601d87..098cd44 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -764,7 +764,7 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
>
>  }
>
> -static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
> +bool amdgpu_vpost_needed(struct amdgpu_device *adev)

Please also make amdgpu_need_post() static now.

Is there a way we can just merge amdgpu_need_post() into
amdgpu_vpost_needed()?  For bare metal it should be fine.  Might need
some logic adjustments for sr-iov amdgpu_device_resume().  That can be
a follow on patch if you want.

Alex


>  {
> if (amdgpu_sriov_vf(adev))
> return false;
> --
> 2.9.5
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Re: [PATCH] drm/amdgpu: drm/amdgpu: always consider virualised device for checking post (v2)

[Alex Deucher]

On Wed, Oct 18, 2017 at 11:09 PM, Ding, Pixel <pixel.d...@amd.com> wrote:
> Thanks Alex. Some comments inline.
> —
> Sincerely Yours,
> Pixel
>
>
>
>
>
>
>
>
> On 19/10/2017, 10:34 AM, "Alex Deucher" <alexdeuc...@gmail.com> wrote:
>
>>On Wed, Oct 18, 2017 at 9:44 PM, Pixel Ding <pixel.d...@amd.com> wrote:
>>> From: pding <pixel.d...@amd.com>
>>>
>>> The post checking on scratch registers isn't reliable for virtual function.
>>>
>>> v2: only change in IGP reading bios.
>>
>>
>>Subject has "drm/amdgpu: drm/amdgpu: " drop one of them.
>>[Pixel] get it.
>>
>>
>>>
>>> Signed-off-by: pding <pixel.d...@amd.com>
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c   | 2 +-
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
>>>  3 files changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 0280ae5..caabc5b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -1840,6 +1840,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>>>  /* Common functions */
>>>  int amdgpu_gpu_reset(struct amdgpu_device *adev);
>>>  bool amdgpu_need_backup(struct amdgpu_device *adev);
>>> +bool amdgpu_vpost_needed(struct amdgpu_device *adev);
>>>  void amdgpu_pci_config_reset(struct amdgpu_device *adev);
>>>  bool amdgpu_need_post(struct amdgpu_device *adev);
>>
>>amdgpu_need_post can be dropped now.
> [Pixel] some other functions still invoke the amdgpu_need_post(). Only if we 
> change all to use amdgpu_vpost_needed(). that’s what the v1 patch did, 
> however it’s confused. the only difference is that original patch uses 
> amdgpu_need_post() function name instead of amdgpu_vpost_needed(), I thought 
> it’s more generic.
>>
>>>  void amdgpu_update_display_priority(struct amdgpu_device *adev);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
>>> index c21adf6..25f43eb 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
>>> @@ -99,7 +99,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device 
>>> *adev)
>>> resource_size_t size = 256 * 1024; /* ??? */
>>>
>>> if (!(adev->flags & AMD_IS_APU))
>>> -   if (amdgpu_need_post(adev))
>>> +   if (amdgpu_vpost_needed(adev))
>>> return false;
>>>
>>> adev->bios = NULL;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index a601d87..098cd44 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -764,7 +764,7 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
>>>
>>>  }
>>>
>>> -static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
>>> +bool amdgpu_vpost_needed(struct amdgpu_device *adev)
>>
>>Please also make amdgpu_need_post() static now.
>>
>>Is there a way we can just merge amdgpu_need_post() into
>>amdgpu_vpost_needed()?  For bare metal it should be fine.  Might need
>>some logic adjustments for sr-iov amdgpu_device_resume().  That can be
>>a follow on patch if you want.
> [Pixel] the original patch replaces all amdgpu_need_post() with 
> amdgpu_vpost_needed(), then rename the amdgpu_vpost_needed() to 
> amdgpu_need_post(), and amdgpu_need_post() to static amdgpu_check_post(). 
> After these transform it looks unclear. By now I think we can go back to that 
> one.

I'm fine with that as long as it doesn't break anything.  The only
difference between the two functions is for virtualization.  I'm not
sure why we use one in some places and other in other places.  I'd
prefer to just merge them to avoid any confusion about when to use
which one.

Alex

>
>>
>>Alex
>>
>>
>>>  {
>>> if (amdgpu_sriov_vf(adev))
>>> return false;
>>> --
>>> 2.9.5
>>>
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Re: [PATCH] drm/amdgpu/psp: prevent page fault by checking write_frame address(v2) -v2: update the ring_buffer_end address

[Alex Deucher]

On Mon, Oct 16, 2017 at 11:26 PM, Evan Quan  wrote:
> Change-Id: If3b79428b32ffab57b4e75f9c20c2b2d7e600223
> Signed-off-by: Evan Quan 

Please include a better commit message.  Something like:
Prevent a a possible buffer overflow when updating the ring buffer by
bounds checking the command frame against the available space in the
ring buffer.


> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 ++--
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 16 ++--
>  2 files changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 77cab1f..7d31c74 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -257,6 +257,9 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> unsigned int psp_write_ptr_reg = 0;
> struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> struct psp_ring *ring = >km_ring;
> +   struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
> +   struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
> +   ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
> struct amdgpu_device *adev = psp->adev;
> uint32_t ring_size_dw = ring->ring_size / 4;
> uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
> @@ -266,9 +269,18 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
>
> /* Update KM RB frame pointer to new frame */
> if ((psp_write_ptr_reg % ring_size_dw) == 0)
> -   write_frame = ring->ring_mem;
> +   write_frame = ring_buffer_start;
> else
> -   write_frame = ring->ring_mem + (psp_write_ptr_reg / 
> rb_frame_size_dw);
> +   write_frame = ring_buffer_start + (psp_write_ptr_reg / 
> rb_frame_size_dw);
> +   /* Check invalid write_frame ptr address */
> +   if ((write_frame < ring_buffer_start) || (ring_buffer_end < 
> write_frame)) {
> +   DRM_ERROR("ring_buffer_start = %x; ring_buffer_end = %x; 
> write_frame = %x\n",
> +   ring_buffer_start,
> +   ring_buffer_end,
> +   write_frame);
> +   DRM_ERROR("write_frame is pointing to address out of 
> bounds\n");
> +   return -EINVAL;
> +   }
>
> /* Initialize KM RB frame */
> memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index bcbe30d..3f0eecf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -367,6 +367,9 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
> unsigned int psp_write_ptr_reg = 0;
> struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> struct psp_ring *ring = >km_ring;
> +   struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
> +   struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
> +   ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
> struct amdgpu_device *adev = psp->adev;
> uint32_t ring_size_dw = ring->ring_size / 4;
> uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
> @@ -378,9 +381,18 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
> /* write_frame ptr increments by size of rb_frame in bytes */
> /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
> if ((psp_write_ptr_reg % ring_size_dw) == 0)
> -   write_frame = ring->ring_mem;
> +   write_frame = ring_buffer_start;
> else
> -   write_frame = ring->ring_mem + (psp_write_ptr_reg / 
> rb_frame_size_dw);
> +   write_frame = ring_buffer_start + (psp_write_ptr_reg / 
> rb_frame_size_dw);
> +   /* Check invalid write_frame ptr address */
> +   if ((write_frame < ring_buffer_start) || (ring_buffer_end < 
> write_frame)) {
> +   DRM_ERROR("ring_buffer_start = %x; ring_buffer_end = %x; 
> write_frame = %x\n",
> +   ring_buffer_start,
> +   ring_buffer_end,
> +   write_frame);
> +   DRM_ERROR("write_frame is pointing to address out of 
> bounds\n");
> +   return -EINVAL;
> +   }
>
> /* Initialize KM RB frame */
> memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/4] ASoC: AMD: DMA driver changes for Stoney Platform

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Added DMA driver changes for Stoney platform.
Below are the key differences between Stoney and CZ

In Stoney, Memory Gating is disabled.SRAM Banks won't
be turned off.No Of SRAM Banks reduced to 6.
DAGB Garlic Interface used and 16 bit resolution is supported.
SRAM bank 1 & SRAM bank 2 will be used for playback scenario.
SRAM Bank 3 & SRAM Bank 4 will be used for Capture scenario.

Acked-by: Mark Brown <broo...@kernel.org>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: Added switch cases for asic type.
v3: Add R-b, resend
v4: Add Mark's Ack

 sound/soc/amd/acp-pcm-dma.c | 87 +
 sound/soc/amd/acp.h |  2 ++
 2 files changed, 67 insertions(+), 22 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index f00b6b9..f16e0b8 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -137,8 +137,8 @@ static void config_dma_descriptor_in_sram(void __iomem 
*acp_mmio,
  * system memory <-> ACP SRAM
  */
 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
-  u32 size, int direction,
-  u32 pte_offset)
+   u32 size, int direction,
+   u32 pte_offset, u32 asic_type)
 {
u16 i;
u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
@@ -152,20 +152,42 @@ static void set_acp_sysmem_dma_descriptors(void __iomem 
*acp_mmio,
(size / 2) - (i * (size/2));
dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) + (i * (size/2));
-   dmadscr[i].xfer_val |=
-   (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) |
-   (size / 2);
+   switch (asic_type) {
+   case CHIP_STONEY:
+   dmadscr[i].xfer_val |=
+   (ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM  
<< 16) |
+   (size / 2);
+   break;
+   default:
+   dmadscr[i].xfer_val |=
+   (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM  << 
16) |
+   (size / 2);
+   }
} else {
dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
-   dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
-   (i * (size/2));
-   dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
-   + (pte_offset * SZ_4K) +
-   (i * (size/2));
-   dmadscr[i].xfer_val |=
-   BIT(22) |
-   (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
-   (size / 2);
+   switch (asic_type) {
+   case CHIP_STONEY:
+   dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS +
+   (i * (size/2));
+   dmadscr[i].dest =
+   ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+   (pte_offset * SZ_4K) + (i * (size/2));
+   dmadscr[i].xfer_val |=
+   BIT(22) |
+   (ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC 
<< 16) |
+   (size / 2);
+   break;
+   default:
+   dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
+   (i * (size/2));
+   dmadscr[i].dest =
+   ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+   (pte_offset * SZ_4K) + (i * (size/2));
+   dmadscr[i].xfer_val |=
+   BIT(22) |
+   (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 
16) |
+   (size / 2);
+   }
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
[i]);
@@ -186,7 +208,8 @@ static void set_acp_sysmem_dma_descriptors(void __iomem 
*acp_mmio,
  * ACP SRAM <-> I2S
  */
 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
- 

[PATCH 1/4] ASoC: AMD: disabling memory gating in stoney platform

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

For Stoney platform, Memory gating is disabled.i.e SRAM Banks
won't be turned off. By Default, SRAM Bank state set to ON.
Added condition checks to skip SRAM Bank state set logic for
Stoney platform.

Acked-by: Mark Brown <broo...@kernel.org>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: Added comments in code and removed locally defined macros
for STONEY and Carrizo.
v3: add R-b, resend
v4: add Mark's Ack

 sound/soc/amd/acp-pcm-dma.c | 79 +++--
 1 file changed, 55 insertions(+), 24 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index dcbf997..f00b6b9 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -20,7 +20,7 @@
 #include 
 
 #include 
-
+#include 
 #include "acp.h"
 
 #define PLAYBACK_MIN_NUM_PERIODS2
@@ -419,7 +419,7 @@ static void acp_set_sram_bank_state(void __iomem *acp_mmio, 
u16 bank,
 }
 
 /* Initialize and bring ACP hardware to default state. */
-static int acp_init(void __iomem *acp_mmio)
+static int acp_init(void __iomem *acp_mmio, u32 asic_type)
 {
u16 bank;
u32 val, count, sram_pte_offset;
@@ -493,9 +493,14 @@ static int acp_init(void __iomem *acp_mmio)
/* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
* Now, turn off all of them. This can't be done in 'poweron' of
* ACP pm domain, as this requires ACP to be initialized.
+   * For Stoney, Memory gating is disabled,i.e SRAM Banks
+   * won't be turned off. The default state for SRAM banks is ON.
+   * Setting SRAM bank state code skipped for STONEY platform.
*/
-   for (bank = 1; bank < 48; bank++)
-   acp_set_sram_bank_state(acp_mmio, bank, false);
+   if (asic_type != CHIP_STONEY) {
+   for (bank = 1; bank < 48; bank++)
+   acp_set_sram_bank_state(acp_mmio, bank, false);
+   }
 
return 0;
 }
@@ -646,14 +651,22 @@ static int acp_dma_open(struct snd_pcm_substream 
*substream)
 
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
intr_data->play_stream = substream;
-   for (bank = 1; bank <= 4; bank++)
-   acp_set_sram_bank_state(intr_data->acp_mmio, bank,
-   true);
+   /* For Stoney, Memory gating is disabled,i.e SRAM Banks
+* won't be turned off. The default state for SRAM banks is ON.
+* Setting SRAM bank state code skipped for STONEY platform.
+*/
+   if (intr_data->asic_type != CHIP_STONEY) {
+   for (bank = 1; bank <= 4; bank++)
+   acp_set_sram_bank_state(intr_data->acp_mmio,
+   bank, true);
+   }
} else {
intr_data->capture_stream = substream;
-   for (bank = 5; bank <= 8; bank++)
-   acp_set_sram_bank_state(intr_data->acp_mmio, bank,
-   true);
+   if (intr_data->asic_type != CHIP_STONEY) {
+   for (bank = 5; bank <= 8; bank++)
+   acp_set_sram_bank_state(intr_data->acp_mmio,
+   bank, true);
+   }
}
 
return 0;
@@ -869,14 +882,23 @@ static int acp_dma_close(struct snd_pcm_substream 
*substream)
 
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adata->play_stream = NULL;
-   for (bank = 1; bank <= 4; bank++)
-   acp_set_sram_bank_state(adata->acp_mmio, bank,
-   false);
-   } else {
+   /* For Stoney, Memory gating is disabled,i.e SRAM Banks
+* won't be turned off. The default state for SRAM banks is ON.
+* Setting SRAM bank state code skipped for STONEY platform.
+* added condition checks for Carrizo platform only
+*/
+   if (adata->asic_type != CHIP_STONEY) {
+   for (bank = 1; bank <= 4; bank++)
+   acp_set_sram_bank_state(adata->acp_mmio, bank,
+   false);
+   }
+   } else  {
adata->capture_stream = NULL;
-   for (bank = 5; bank <= 8; bank++)
-   acp_set_sram_bank_state(adata->acp_mmio, bank,
-   false);
+   if (adata->asic_type != CHIP_STONEY) {
+

[PATCH 4/4] ASoC: AMD: Add machine driver for cz rt5650

[Alex Deucher]

From: Akshu Agrawal <akshu.agra...@amd.com>

The driver is used for AMD board using rt5650 codec.

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Akshu Agrawal <akshu.agra...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Dylan Reid <dgr...@chromium.org>
---

v2: Change ACPI ID to AMDI1002
v3: add R-b, resend
v4: Fix audio jack issue (Dylan Reid)
Fix Kconfig
Use devm_snd_soc_register_card
Add MODULE_DEVICE_TABLE

 sound/soc/amd/Kconfig  |   7 ++
 sound/soc/amd/Makefile |   2 +
 sound/soc/amd/acp-rt5645.c | 199 +
 3 files changed, 208 insertions(+)
 create mode 100644 sound/soc/amd/acp-rt5645.c

diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig
index 78187eb..d583840 100644
--- a/sound/soc/amd/Kconfig
+++ b/sound/soc/amd/Kconfig
@@ -2,3 +2,10 @@ config SND_SOC_AMD_ACP
tristate "AMD Audio Coprocessor support"
help
 This option enables ACP DMA support on AMD platform.
+
+config SND_SOC_AMD_CZ_RT5645_MACH
+   tristate "AMD CZ support for RT5645"
+   select SND_SOC_RT5645
+   depends on SND_SOC_AMD_ACP && I2C
+   help
+This option enables machine driver for rt5645.
diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile
index 1a66ec0..eed64ff 100644
--- a/sound/soc/amd/Makefile
+++ b/sound/soc/amd/Makefile
@@ -1,3 +1,5 @@
 snd-soc-acp-pcm-objs   := acp-pcm-dma.o
+snd-soc-acp-rt5645-mach-objs := acp-rt5645.o
 
 obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o
+obj-$(CONFIG_SND_SOC_AMD_CZ_RT5645_MACH) += snd-soc-acp-rt5645-mach.o
diff --git a/sound/soc/amd/acp-rt5645.c b/sound/soc/amd/acp-rt5645.c
new file mode 100644
index 000..941aed6
--- /dev/null
+++ b/sound/soc/amd/acp-rt5645.c
@@ -0,0 +1,199 @@
+/*
+ * Machine driver for AMD ACP Audio engine using Realtek RT5645 codec
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * This file is modified from rt288 machine driver
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../codecs/rt5645.h"
+
+#define CZ_PLAT_CLK 2400
+
+static struct snd_soc_jack cz_jack;
+
+static int cz_aif1_hw_params(struct snd_pcm_substream *substream,
+struct snd_pcm_hw_params *params)
+{
+   int ret = 0;
+   struct snd_soc_pcm_runtime *rtd = substream->private_data;
+   struct snd_soc_dai *codec_dai = rtd->codec_dai;
+
+   ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
+ CZ_PLAT_CLK, params_rate(params) * 512);
+   if (ret < 0) {
+   dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
+   return ret;
+   }
+
+   ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
+   params_rate(params) * 512, SND_SOC_CLOCK_OUT);
+   if (ret < 0) {
+   dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int cz_init(struct snd_soc_pcm_runtime *rtd)
+{
+   int ret;
+   struct snd_soc_card *card;
+   struct snd_soc_codec *codec;
+
+   codec = rtd->codec;
+   card = rtd->card;
+
+   ret = snd_soc_card_jack_new(card, "Headset Jack",
+   SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
+   SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+   SND_JACK_BTN_2 | SND_JACK_BTN_3,
+   _jack, NULL, 0);
+   if (ret) {
+   dev_err(card->dev, "HP jack creation failed %d\n", ret);
+   return ret;
+   }
+
+   rt5

[PATCH 3/4] ASoC: AMD: Audio buffer related changes for Stoney

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Stoney uses 16kb SRAM memory for playback and 16Kb
for capture.Modified Max buffer size to have the
correct mapping between System Memory and SRAM.

Added snd_pcm_hardware structures for playback
and capture for Stoney.

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: Added switch cases for asic type.
v3: add R-b, resend
v4: use switch case for buffer allocation
Modify period size macros for Stoney
Whitespace fixes

 sound/soc/amd/acp-pcm-dma.c | 83 ++---
 1 file changed, 78 insertions(+), 5 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index f16e0b8..73b58ee 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -35,6 +35,11 @@
 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
 #define MIN_BUFFER MAX_BUFFER
 
+#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
+#define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
+#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
+#define ST_MIN_BUFFER ST_MAX_BUFFER
+
 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
@@ -73,6 +78,44 @@ static const struct snd_pcm_hardware 
acp_pcm_hardware_capture = {
.periods_max = CAPTURE_MAX_NUM_PERIODS,
 };
 
+static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
+   SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+   .formats = SNDRV_PCM_FMTBIT_S16_LE |
+   SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+   .channels_min = 1,
+   .channels_max = 8,
+   .rates = SNDRV_PCM_RATE_8000_96000,
+   .rate_min = 8000,
+   .rate_max = 96000,
+   .buffer_bytes_max = ST_MAX_BUFFER,
+   .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
+   .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
+   .periods_min = PLAYBACK_MIN_NUM_PERIODS,
+   .periods_max = PLAYBACK_MAX_NUM_PERIODS,
+};
+
+static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
+   SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+   .formats = SNDRV_PCM_FMTBIT_S16_LE |
+   SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+   .channels_min = 1,
+   .channels_max = 2,
+   .rates = SNDRV_PCM_RATE_8000_48000,
+   .rate_min = 8000,
+   .rate_max = 48000,
+   .buffer_bytes_max = ST_MAX_BUFFER,
+   .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
+   .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
+   .periods_min = CAPTURE_MIN_NUM_PERIODS,
+   .periods_max = CAPTURE_MAX_NUM_PERIODS,
+};
+
 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 {
return readl(acp_mmio + (reg * 4));
@@ -664,10 +707,23 @@ static int acp_dma_open(struct snd_pcm_substream 
*substream)
if (adata == NULL)
return -ENOMEM;
 
-   if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-   runtime->hw = acp_pcm_hardware_playback;
-   else
-   runtime->hw = acp_pcm_hardware_capture;
+   if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+   switch (intr_data->asic_type) {
+   case CHIP_STONEY:
+   runtime->hw = acp_st_pcm_hardware_playback;
+   break;
+   default:
+   runtime->hw = acp_pcm_hardware_playback;
+   }
+   } else {
+   switch (intr_data->asic_type) {
+   case CHIP_STONEY:
+   runtime->hw = acp_st_pcm_hardware_capture;
+   break;
+   default:
+   runtime->hw = acp_pcm_hardware_capture;
+   }
+   }
 
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
@@ -905,10 +961,27 @@ static int acp_dma_trigger(struct snd_pcm_substream 
*substream, int cmd)
 
 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
 {
-   return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
+   int ret;
+   struct audio_drv_data *adata = dev_get_drvdata(rtd->platform->dev);
+
+   switch (adata->asic_type) {
+   case CHIP_STONEY:
+ 

[PATCH 0/4 resend] Add ASoC support for AMD Stoney APUs

[Alex Deucher]

This patch set updates the AMD GPU and Audio CoProcessor (ACP)
audio drivers and the designware i2s driver for Stoney (ST).
ST is an APU similar to Carrizo (CZ) which already has ACP audio
support.  The i2s controller and ACP audio DMA engine are part of
the GPU and both need updating so I would like to upstream the
whole patch set via one tree if possible.

I just sent a pull request for the pre-requisite patches which are
available here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=linus-4.14-rc4-acp-prereq

This is a resend of just the non pre-requisite audio patches at Mark's request.

Thanks!

Alex

v2:
- Patch 1 is already applied to the audio tree, just including it for
  completeness since it's required for this patch set and it's not yet
  in the drm tree.
- New patch to share asic types between gpu and audio drivers
- ACPI ID changed for rt5650 machine driver
- Integrate feedback on other patches

v3:
- resend remaining patches that have not been applied yet

v4:
- Integrate feedback from v3
- Add Mark's acks from v3
- Integrate a machine driver fix from Dylan Reid

Akshu Agrawal (1):
  ASoC: AMD: Add machine driver for cz rt5650

Vijendar Mukunda (3):
  ASoC: AMD: disabling memory gating in stoney platform
  ASoC: AMD: DMA driver changes for Stoney Platform
  ASoC: AMD: Audio buffer related changes for Stoney

 sound/soc/amd/Kconfig   |   7 ++
 sound/soc/amd/Makefile  |   2 +
 sound/soc/amd/acp-pcm-dma.c | 249 +++-
 sound/soc/amd/acp-rt5645.c  | 199 +++
 sound/soc/amd/acp.h |   2 +
 5 files changed, 408 insertions(+), 51 deletions(-)
 create mode 100644 sound/soc/amd/acp-rt5645.c

-- 
2.5.5

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[pull] amdgpu drm-fixes-4.14

[Alex Deucher]

Hi Dave,

Just one revert to fix a stability regression.

The following changes since commit 2de0307323fc42c6395d0eafec9879d55e042c85:

  Merge tag 'exynos-drm-fixes-for-v4.14-rc5' of 
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes 
(2017-10-17 10:14:56 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.14

for you to fetch changes up to c94501279bb191ccf204f496e9576ce036f81bcd:

  Revert "drm/amdgpu: discard commands of killed processes" (2017-10-18 
12:57:47 -0400)

----
Alex Deucher (1):
  Revert "drm/amdgpu: discard commands of killed processes"

 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 23 ---
 1 file changed, 4 insertions(+), 19 deletions(-)
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Re: [PATCH] drm/amd/pp: Fix overflow when setup decf/pix/disp dpm table.

[Alex Deucher]

On Wed, Oct 18, 2017 at 5:45 AM, Rex Zhu <rex@amd.com> wrote:
> Change-Id: I9e72043ea619a86b2bcf14ce9d6386fee107bd19
> Signed-off-by: Rex Zhu <rex@amd.com>

Please include a better patch description.  E.g., Clear the count in
the single table setup function to avoid missing any tables.
or something like that.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 500f177..0519338 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -1161,6 +1161,8 @@ static void 
> vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
>  {
> int i;
>
> +   dpm_table->count = 0;
> +
> for (i = 0; i < dep_table->count; i++) {
> if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 
> 1].value <=
> dep_table->entries[i].clk) {
> @@ -1269,10 +1271,6 @@ static int vega10_setup_default_dpm_tables(struct 
> pp_hwmgr *hwmgr)
> return -EINVAL);
>
> /* Initialize Sclk DPM table based on allow Sclk values */
> -   data->dpm_table.soc_table.count = 0;
> -   data->dpm_table.gfx_table.count = 0;
> -   data->dpm_table.dcef_table.count = 0;
> -
> dpm_table = &(data->dpm_table.soc_table);
> vega10_setup_default_single_dpm_table(hwmgr,
> dpm_table,
> --
> 1.9.1
>
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Re: [PATCH] drm/amdgpu:fix wb_clear

[Alex Deucher]

On Wed, Oct 18, 2017 at 4:52 AM, Monk Liu <monk@amd.com> wrote:
> Change-Id: I6d50cc769ee29bf13524c83105d5004b0a2d85e3
> Signed-off-by: Monk Liu <monk@amd.com>

Please include a better patch description.  Something like:
Properly shift the index when clearing so we clear the right bit.

With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index ee3846c..23f946b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -551,7 +551,7 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
>
> if (offset < adev->wb.num_wb) {
> __set_bit(offset, adev->wb.used);
> -   *wb = offset * 8; /* convert to dw offset */
> +   *wb = offset << 3; /* convert to dw offset */
> return 0;
> } else {
> return -EINVAL;
> @@ -569,7 +569,7 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
>  void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
>  {
> if (wb < adev->wb.num_wb)
> -   __clear_bit(wb, adev->wb.used);
> +   __clear_bit(wb >> 3, adev->wb.used);
>  }
>
>  /**
> --
> 2.7.4
>
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Re: [PATCH] drm/amd/amdgpu: Remove workaround check for UVD6 on APUs

[Alex Deucher]

On Mon, Oct 23, 2017 at 1:03 PM, Tom St Denis <tom.stde...@amd.com> wrote:
> On APUs the uvd6 driver was skipping proper suspend/resume routines resulting
> in a broken state upon resume.
>
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 +---
>  1 file changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 71299c67c517..2581543b35a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -565,11 +565,7 @@ static int uvd_v6_0_suspend(void *handle)
> if (r)
> return r;
>
> -   /* Skip this for APU for now */
> -   if (!(adev->flags & AMD_IS_APU))
> -   r = amdgpu_uvd_suspend(adev);
> -
> -   return r;
> +   return amdgpu_uvd_suspend(adev);
>  }
>
>  static int uvd_v6_0_resume(void *handle)
> @@ -577,12 +573,10 @@ static int uvd_v6_0_resume(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   /* Skip this for APU for now */
> -   if (!(adev->flags & AMD_IS_APU)) {
> -   r = amdgpu_uvd_resume(adev);
> -   if (r)
> -   return r;
> -   }
> +   r = amdgpu_uvd_resume(adev);
> +   if (r)
> +   return r;
> +
> return uvd_v6_0_hw_init(adev);
>  }
>
> --
> 2.12.0
>
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[pull] amdgpu drm-next-4.15

[Alex Deucher]

Hi Dave,

Misc fixes for 4.15.

The following changes since commit a9386bb051931778436db3dd6e3a163f7db92b56:

  Merge tag 'drm-misc-next-fixes-2017-11-08' of 
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2017-11-09 11:59:30 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.15

for you to fetch changes up to 451cc55dd17fa5130f05629ac8d90e32facf27f6:

  drm/amd/pp: fix dpm randomly failed on Vega10 (2017-11-15 14:03:45 -0500)


Christian König (2):
  drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit
  drm/amdgpu: set f_mapping on exported DMA-bufs

Colin Ian King (1):
  drm/amd/powerplay: fix copy-n-paste error on vddci_buf index

Emily Deng (1):
  drm/amdgpu: Fix null pointer issue in amdgpu_cs_wait_any_fence

Ken Wang (2):
  drm/amdgpu: Remove check which is not valid for certain VBIOS
  drm/amdgpu: Add common golden settings for GFX9

Nicolai Hähnle (1):
  drm/amdgpu/gfx9: implement wave VGPR reading

Rex Zhu (1):
  drm/amd/pp: fix dpm randomly failed on Vega10

Roger He (1):
  drm/amd/amdgpu: if visible VRAM allocation fail, fall back to invisible 
try again

Tom St Denis (1):
  drm/amd/amdgpu: Fix wave mask in amdgpu_debugfs_wave_read() (v2)

ozeng (1):
  drm/amdgpu: Properly allocate VM invalidate eng v2

 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c   |  6 
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  7 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 40 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 10 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  |  6 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  3 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 19 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 15 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 29 
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 +
 11 files changed, 87 insertions(+), 51 deletions(-)
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[pull] amdgpu dc drm-next-4.15-dc

[Alex Deucher]

Hi Dave,

Various fixes for DC for 4.15.  It doesn't look like you pulled the
smatch fixes for DC that I sent out last week.  Those are also on this branch.

The following changes since commit f368d3bfde225199eef2216b03e0ba4944a3434a:

  amd/display: Fix potential null dereference in dce_calcs.c (2017-11-08 
17:30:11 -0500)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.15-dc

for you to fetch changes up to 00f713c6dc657397ba37b42d7f6887f526c730c6:

  drm/amd/display: fix MST link training fail division by 0 (2017-11-14 
11:32:46 -0500)


Bhawanpreet Lakha (1):
  drm/amd/display: add flip_immediate to commit update for stream

Charlene Liu (1):
  drm/amd/display: fix AZ clock not enabled before program AZ endpoint

Eric Yang (1):
  drm/amd/display: fix MST link training fail division by 0

Harry Wentland (1):
  drm/amd/display: Fix formatting for null pointer dereference fix

Jerry (Fangzhi) Zuo (1):
  drm/amd/display: Miss register MST encoder cbs

Ken Chalmers (1):
  drm/amd/display: use num_timing_generator instead of pipe_count

Leo (Sunpeng) Li (2):
  drm/amd/display: Fix warnings on S3 resume
  drm/amd/display: Remove dangling planes on dc commit state

Michel Dänzer (1):
  amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check

Roman Li (1):
  drm/amd/display: use configurable FBC option in dm

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 44 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  4 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 12 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 42 +++--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  6 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|  2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 31 ++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 +-
 8 files changed, 122 insertions(+), 21 deletions(-)
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[PATCH] Revert "drm/radeon: dont switch vt on suspend"

[Alex Deucher]

Fixes distorted colors on some cards on resume from suspend.

This reverts commit b9729b17a414f99c61f4db9ac9f9ed987fa0cbfe.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=98832
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/radeon/radeon_fb.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_fb.c 
b/drivers/gpu/drm/radeon/radeon_fb.c
index 2fcf805d3a16..33b821d6d018 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
}
 
info->par = rfbdev;
-   info->skip_vt_switch = true;
 
ret = radeon_framebuffer_init(rdev->ddev, >rfb, _cmd, 
gobj);
if (ret) {
-- 
2.13.6

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Re: [PATCH 03/13] drm/amdgpu: use simpler remove_conflicting_pci_framebuffers()

[Alex Deucher]

On Fri, Nov 24, 2017 at 12:53 PM, Michał Mirosław
<mirq-li...@rere.qmqm.pl> wrote:
> Signed-off-by: Michał Mirosław <mirq-li...@rere.qmqm.pl>

radeon and amdgpu patches (3 and 7) are:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 23 +--
>  1 file changed, 1 insertion(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index dd2f060d62a8..b726222b7dd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -537,27 +537,6 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
>
>  static struct drm_driver kms_driver;
>
> -static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
> -{
> -   struct apertures_struct *ap;
> -   bool primary = false;
> -
> -   ap = alloc_apertures(1);
> -   if (!ap)
> -   return -ENOMEM;
> -
> -   ap->ranges[0].base = pci_resource_start(pdev, 0);
> -   ap->ranges[0].size = pci_resource_len(pdev, 0);
> -
> -#ifdef CONFIG_X86
> -   primary = pdev->resource[PCI_ROM_RESOURCE].flags & 
> IORESOURCE_ROM_SHADOW;
> -#endif
> -   drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", 
> primary);
> -   kfree(ap);
> -
> -   return 0;
> -}
> -
>  static int amdgpu_pci_probe(struct pci_dev *pdev,
> const struct pci_device_id *ent)
>  {
> @@ -580,7 +559,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> return ret;
>
> /* Get rid of things like offb */
> -   ret = amdgpu_kick_out_firmware_fb(pdev);
> +   ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, 
> "amdgpudrmfb");
> if (ret)
> return ret;
>
> --
> 2.11.0
>
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Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file

[Alex Deucher]

On Mon, Nov 27, 2017 at 3:44 PM, Christian König
 wrote:
> Am 27.11.2017 um 21:01 schrieb Felix Kuehling:
>>
>> On 2017-11-27 02:37 PM, Koenig, Christian wrote:
>>>
>>> And that is a clear NAK to this approach.
>>
>> Hi Christian,
>>
>> Do you have other objections than the style issues? If so, please explain.
>
>
> No, the technical aspect actually looks rather reasonable.
>
>> Please clarify, why this file needs to be treated differently from other
>> files under include/asic_reg? All those files are auto-generated by HW
>> teams. Fixing the coding style adds no value and makes future updates
>> more complicated.
>
>
> We already got complains about that and most likely will need to fix the
> rest as well.

I'd like to stay as close as possible to the headers formats we are
using internally across teams for consistency.  Rather than rewriting
these now, how about we just rename soc15ip.h to vg10ip.h and use that
or even just drop patch 1 and use soc15ip.h as is for now.

Alex

>
> Nicolai looked into using a different auto generator for the header files,
> but not sure how far that already got along.
>
> The point is that the structures added with this won't be used by soc15
> alone, but rather be the base of the new register definition for future
> hardware generations as well.
>
>> Like Shaoyun pointed out for example, the existing file
>> include/asic_reg/vega10/soc15ip.h has the same style issues.
>
>
> That file actually doesn't exists any more. Please see the work from Feifei
> about that as well.
>
> Regards,
> Christian.
>
>>
>> Regards,
>>Felix
>>
>>> Please start by fixing at least the obvious style problems before
>>> resending.
>>>
>>> Thanks,
>>> Christian.
>>>
>>> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" :
>>>
>>>  I agree that this HW engineer generated file doesn't match the
>>>  coding style from linux  software engineer point  of view , but
>>>  since we already import other similar " HW engineer style"  files
>>>  under include/asic_reg/vega10/, I don't see a reason to specially
>>>  change this file without touch else . This file is actually almost
>>>  identical as soc15ip.h .  I think it's easier  for us to import
>>>  other offset  file in the future if we keep them un-touched .
>>>
>>>  Regards
>>>  Shaoyun.liu
>>>
>>>
>>>  -Original Message-
>>>  From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
>>>  Sent: Monday, November 27, 2017 2:17 PM
>>>  To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
>>>  Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file
>>>
>>>  First of let us fix the obvious style problems.
>>>
>>>  Am 27.11.2017 um 19:30 schrieb Shaoyun Liu:
>>>  > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c
>>>  > Signed-off-by: Shaoyun Liu 
>>>  > ---
>>>  >   .../drm/amd/include/asic_reg/vega10/ip_offset_1.h  | 1248
>>>  
>>>  >   1 file changed, 1248 insertions(+)
>>>  >   create mode 100644
>>>  drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
>>>  >
>>>  > diff --git
>>>  a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
>>>  b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
>>>  > new file mode 100644
>>>  > index 000..76cb748
>>>  > --- /dev/null
>>>  > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
>>>  > @@ -0,0 +1,1248 @@
>>>  > +#ifndef _ip_offset_1_HEADER
>>>  > +#define _ip_offset_1_HEADER
>>>  Names for preprocessor defines should be capitable.
>>>
>>>  > +
>>>  > +#define MAX_INSTANCE   5
>>>  > +#define MAX_SEGMENT5
>>>  > +
>>>  > +
>>>  > +struct IP_BASE_INSTANCE
>>>
>>>  Structure names should be lower case. And we need an amdgpu_ or at
>>>  least
>>>  amd_ prefix here.
>>>
>>>  Regards,
>>>  Christian.
>>>
>>>  > +{
>>>  > +unsigned int segment[MAX_SEGMENT];
>>>  > +};
>>>  > +
>>>  > +struct IP_BASE
>>>  > +{
>>>  > +struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
>>>  > +};
>>>  > +
>>>  > +
>>>  > +static const struct IP_BASE NBIF_BASE=
>>>  { { { { 0x, 0x0014, 0x0D20, 0x00010400, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } } } };
>>>  > +static const struct IP_BASE NBIO_BASE=
>>>  { { { { 0x, 0x0014, 0x0D20, 0x00010400, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } },
>>>  >
>>>  +
>>>  { { 0, 0, 0, 0, 0 } },
>>>  >

Re: [PATCH v2 2/2] drm/amd/display: Don't call dm_log_to_buffer directly in dc_conn_log

[Alex Deucher]

On Tue, Nov 28, 2017 at 6:09 AM, Michel Dänzer <mic...@daenzer.net> wrote:
>
> Ping on this series.
>
> This patch is v2 of a previously single patch, which was reviewed by Harry.
>
>

Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> On 2017-11-23 06:48 PM, Michel Dänzer wrote:
>> From: Michel Dänzer <michel.daen...@amd.com>
>>
>> dm_log_to_buffer logs unconditionally, so calling it directly resulted
>> in the main message being logged even when the event type isn't enabled
>> in the event mask.
>>
>> To fix this, use the new dm_logger_append_va API.
>>
>> Fixes spurious messages like
>>
>>  [drm] {1920x1200, 2080x1235@154000Khz}
>>
>> in dmesg when a mode is set.
>>
>> v2:
>> * Use new dm_logger_append_va API, fixes incorrect va_list usage in v1
>> * Just use and decrease entry.buf_offset to get rid of the trailing
>>   newline
>>
>> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
>> ---
>>  drivers/gpu/drm/amd/display/dc/basics/log_helpers.c | 10 +++---
>>  1 file changed, 3 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c 
>> b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
>> index 785b943b60ed..fe1648f81d71 100644
>> --- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
>> +++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
>> @@ -80,15 +80,11 @@ void dc_conn_log(struct dc_context *ctx,
>>   link->link_index);
>>
>>   va_start(args, msg);
>> - entry.buf_offset += dm_log_to_buffer(
>> - [entry.buf_offset],
>> - LOG_MAX_LINE_SIZE - entry.buf_offset,
>> - msg, args);
>> + dm_logger_append_va(, msg, args);
>>
>> - if (entry.buf[strlen(entry.buf) - 1] == '\n') {
>> - entry.buf[strlen(entry.buf) - 1] = '\0';
>> + if (entry.buf_offset > 0 &&
>> + entry.buf[entry.buf_offset - 1] == '\n')
>>   entry.buf_offset--;
>> - }
>>
>>   if (hex_data)
>>   for (i = 0; i < hex_data_count; i++)
>>
>
>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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[PATCH 1/2] drm/amdgpu: add license to Makefiles

[Alex Deucher]

Was missing license text.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/acp/Makefile   | 21 
 drivers/gpu/drm/amd/amdgpu/Makefile| 21 
 drivers/gpu/drm/amd/amdkfd/Makefile| 21 
 drivers/gpu/drm/amd/display/Makefile   | 21 
 drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 21 
 drivers/gpu/drm/amd/display/dc/Makefile| 21 
 drivers/gpu/drm/amd/display/dc/basics/Makefile | 21 
 drivers/gpu/drm/amd/display/dc/bios/Makefile   | 21 
 drivers/gpu/drm/amd/display/dc/calcs/Makefile  | 21 
 drivers/gpu/drm/amd/display/dc/dce/Makefile| 21 
 drivers/gpu/drm/amd/display/dc/dce100/Makefile | 21 
 drivers/gpu/drm/amd/display/dc/dce110/Makefile | 21 
 drivers/gpu/drm/amd/display/dc/dce112/Makefile | 21 
 drivers/gpu/drm/amd/display/dc/dce120/Makefile | 23 +-
 drivers/gpu/drm/amd/display/dc/dce80/Makefile  | 21 
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile  | 21 
 drivers/gpu/drm/amd/display/dc/dml/Makefile| 21 
 drivers/gpu/drm/amd/display/dc/gpio/Makefile   | 21 
 drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 21 
 drivers/gpu/drm/amd/display/dc/irq/Makefile| 21 
 drivers/gpu/drm/amd/display/dc/virtual/Makefile| 21 
 .../gpu/drm/amd/display/modules/freesync/Makefile  | 21 
 drivers/gpu/drm/amd/lib/Makefile   | 21 
 drivers/gpu/drm/amd/powerplay/Makefile | 21 
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   | 21 
 drivers/gpu/drm/amd/powerplay/smumgr/Makefile  | 21 
 26 files changed, 547 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/acp/Makefile b/drivers/gpu/drm/amd/acp/Makefile
index 8a08e81ee90d..d4176a3fb706 100644
--- a/drivers/gpu/drm/amd/acp/Makefile
+++ b/drivers/gpu/drm/amd/acp/Makefile
@@ -1,4 +1,25 @@
 #
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
 # Makefile for the ACP, which is a sub-component
 # of AMDSOC/AMDGPU drm driver.
 # It provides the HW control for ACP related functionalities.
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6a025c476b37..90202cf4cd1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -1,4 +1,25 @@
 #
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF

[PATCH 2/2] drm/amdgpu: add license to files where it was missing

[Alex Deucher]

These files were missing it before.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 23 ++
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 22 +
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_helper.c | 22 +
 .../drm/amd/display/dc/dce100/dce100_resource.c|  2 +-
 .../drm/amd/display/dc/dce100/dce100_resource.h| 23 ++
 .../drm/amd/display/dc/dce110/dce110_resource.c|  2 +-
 .../display/dc/dce110/dce110_timing_generator_v.c  | 23 ++
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 22 +
 .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 22 +
 .../gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c| 23 ++
 drivers/gpu/drm/amd/powerplay/inc/smu72.h  | 23 ++
 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h | 23 ++
 drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h| 23 ++
 15 files changed, 254 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6f56ff606e43..83205b93e62d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1,4 +1,6 @@
 /*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 213988f336ed..06525f2c36c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -1,3 +1,26 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
 #if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
 #define _AMDGPU_TRACE_H_
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 2e509382935f..1babac07bcc9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -1,4 +1,26 @@
 /*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+/*
  * dc_debug.c
  *
  *  Created on: Nov 3, 2016
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 80b131b4d3ae..27dcb

Re: [PATCH v2 xf86-video-amdgpu] Add amdgpu_dirty_src_drawable helper

[Alex Deucher]

On Thu, Nov 23, 2017 at 5:48 AM, Michel Dänzer <mic...@daenzer.net> wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> Allows tidying up amdgpu_dirty_src_equals and redisplay_dirty slightly.
>
> v2:
> * Different approach for amdgpu_dirty_master
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  src/amdgpu_drv.h | 18 +-
>  src/amdgpu_kms.c |  7 ++-
>  2 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/src/amdgpu_drv.h b/src/amdgpu_drv.h
> index 4ee13e12b..055c3c3e9 100644
> --- a/src/amdgpu_drv.h
> +++ b/src/amdgpu_drv.h
> @@ -177,24 +177,24 @@ amdgpu_master_screen(ScreenPtr screen)
>
>  static inline ScreenPtr
>  amdgpu_dirty_master(PixmapDirtyUpdatePtr dirty)
> +{
> +   return amdgpu_master_screen(dirty->slave_dst->drawable.pScreen);
> +}
> +
> +static inline DrawablePtr
> +amdgpu_dirty_src_drawable(PixmapDirtyUpdatePtr dirty)
>  {
>  #ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> -   ScreenPtr screen = dirty->src->pScreen;
> +   return dirty->src;
>  #else
> -   ScreenPtr screen = dirty->src->drawable.pScreen;
> +   return >src->drawable;
>  #endif
> -
> -   return amdgpu_master_screen(screen);
>  }
>
>  static inline Bool
>  amdgpu_dirty_src_equals(PixmapDirtyUpdatePtr dirty, PixmapPtr pixmap)
>  {
> -#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> -   return dirty->src == >drawable;
> -#else
> -   return dirty->src == pixmap;
> -#endif
> +   return amdgpu_dirty_src_drawable(dirty) == >drawable;
>  }
>
>
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index a5f2040a8..c15711224 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -479,11 +479,8 @@ dirty_region(PixmapDirtyUpdatePtr dirty)
>  static void
>  redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region)
>  {
> -#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> -   ScrnInfoPtr src_scrn = xf86ScreenToScrn(dirty->src->pScreen);
> -#else
> -   ScrnInfoPtr src_scrn = xf86ScreenToScrn(dirty->src->drawable.pScreen);
> -#endif
> +   ScrnInfoPtr src_scrn =
> +   xf86ScreenToScrn(amdgpu_dirty_src_drawable(dirty)->pScreen);
>
> if (RegionNil(region))
> goto out;
> --
> 2.15.0
>
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Re: [PATCH] Revert "drm/amdgpu: fix rmmod KCQ disable failed error"

[Alex Deucher]

On Sun, Nov 26, 2017 at 10:53 PM, Liu, Monk <monk@amd.com> wrote:
> Anyone review this one ?

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
> Monk Liu
> Sent: 2017年11月24日 15:07
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <monk@amd.com>
> Subject: [PATCH] Revert "drm/amdgpu: fix rmmod KCQ disable failed error"
>
> This reverts commit ff8a0428d1b0e55db6b6e0462e2dc51c4d6724a8.
>
> this patch is incorrrect, amdgpu_ucode_bo_fini always called after gfx_hw_fini
>
> Change-Id: I7246ea0d2c7c843c14e9923c4d2efde4d90a9ef5
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 3 ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 3 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 2 ++
>  3 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 285daa8..48e892e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1914,9 +1914,6 @@ static int amdgpu_fini(struct amdgpu_device *adev)
> adev->ip_blocks[i].status.hw = false;
> }
>
> -   if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> -   amdgpu_ucode_fini_bo(adev);
> -
> for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> if (!adev->ip_blocks[i].status.sw)
> continue;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index 033fba2..5f5aa5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -164,6 +164,9 @@ static int amdgpu_pp_hw_fini(void *handle)
> ret = adev->powerplay.ip_funcs->hw_fini(
> adev->powerplay.pp_handle);
>
> +   if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> +   amdgpu_ucode_fini_bo(adev);
> +
> return ret;
>  }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index f95a200..2157d45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -446,6 +446,8 @@ static int psp_hw_fini(void *handle)
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> return 0;
>
> +   amdgpu_ucode_fini_bo(adev);
> +
> psp_ring_destroy(psp, PSP_RING_TYPE__KM);
>
> amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
> --
> 2.7.4
>
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Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file

[Alex Deucher]

On Mon, Nov 27, 2017 at 4:28 PM, Christian König
<christian.koe...@amd.com> wrote:
> Am 27.11.2017 um 21:56 schrieb Alex Deucher:
>>
>> On Mon, Nov 27, 2017 at 3:44 PM, Christian König
>> <christian.koe...@amd.com> wrote:
>>>
>>> Am 27.11.2017 um 21:01 schrieb Felix Kuehling:
>>>>
>>>> On 2017-11-27 02:37 PM, Koenig, Christian wrote:
>>>>>
>>>>> And that is a clear NAK to this approach.
>>>>
>>>> Hi Christian,
>>>>
>>>> Do you have other objections than the style issues? If so, please
>>>> explain.
>>>
>>>
>>> No, the technical aspect actually looks rather reasonable.
>>>
>>>> Please clarify, why this file needs to be treated differently from other
>>>> files under include/asic_reg? All those files are auto-generated by HW
>>>> teams. Fixing the coding style adds no value and makes future updates
>>>> more complicated.
>>>
>>>
>>> We already got complains about that and most likely will need to fix the
>>> rest as well.
>>
>> I'd like to stay as close as possible to the headers formats we are
>> using internally across teams for consistency.
>
>
> To be honest I strongly disagree on that. The bad quality of the internal
> AMD headers is the reason we had to basically have the VMHUB code for Vega10
> twice for example.
>
> We should either massively push back on that (already done and with the next
> hardware generation a bunch of things will be fixed, but unfortunately not
> for Vega10 any more).
>
> Or we start to cleanup and/or generate the headers ourself.
>
> Or at least do the manual cleanup for Vega10 and hope that the next chunk
> will be better.

I don't disagree, but I'd rather we talk to the other teams and try
and get some consensus and figure out what teams will use or maintain
the tools going forward and have a plan in place rather than just
going off on our own in the short term.

Alex

>
>> Rather than rewriting these now, how about we just rename soc15ip.h to
>> vg10ip.h and use that
>
>
> That sounds like a good idea to me, but the structure defines still need to
> be asic independent and applicable for all hardware generations, not just
> Vega10.
>
> Otherwise we will need to create translation functions for each ASIC
> generation to our internal format which is neither clean nor looks very
> good.
>
> Christian.
>
>
>> or even just drop patch 1 and use soc15ip.h as is for now.
>>
>> Alex
>>
>>> Nicolai looked into using a different auto generator for the header
>>> files,
>>> but not sure how far that already got along.
>>>
>>> The point is that the structures added with this won't be used by soc15
>>> alone, but rather be the base of the new register definition for future
>>> hardware generations as well.
>>>
>>>> Like Shaoyun pointed out for example, the existing file
>>>> include/asic_reg/vega10/soc15ip.h has the same style issues.
>>>
>>>
>>> That file actually doesn't exists any more. Please see the work from
>>> Feifei
>>> about that as well.
>>>
>>> Regards,
>>> Christian.
>>>
>>>> Regards,
>>>> Felix
>>>>
>>>>> Please start by fixing at least the obvious style problems before
>>>>> resending.
>>>>>
>>>>> Thanks,
>>>>> Christian.
>>>>>
>>>>> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <shaoyun@amd.com>:
>>>>>
>>>>>   I agree that this HW engineer generated file doesn't match the
>>>>>   coding style from linux  software engineer point  of view , but
>>>>>   since we already import other similar " HW engineer style"  files
>>>>>   under include/asic_reg/vega10/, I don't see a reason to specially
>>>>>   change this file without touch else . This file is actually
>>>>> almost
>>>>>   identical as soc15ip.h .  I think it's easier  for us to import
>>>>>   other offset  file in the future if we keep them un-touched .
>>>>>
>>>>>   Regards
>>>>>   Shaoyun.liu
>>>>>
>>>>>
>>>>>   -Original Message-
>>>>>   From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
>>>>>   Sent: Monday, November 27, 2017 2:17 PM
>

[pull] radeon, amdgpu, and ttm drm-fixes-4.15

[Alex Deucher]

Hi Dave,

Fixes for 4.15.  Highlights:
- DC fixes for S3, gamma, audio, pageflipping, etc.
- fix a regression in radeon from kfd removal
- fix a ttm regression with swiotlb disabled
- misc other fixes

The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.15

for you to fetch changes up to 7fdf165a52505392eb059902b0df55e79a45c25f:

  drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd (2017-11-29 14:43:20 
-0500)


Alex Deucher (4):
  drm/amdgpu/gfx7: cache raster_config values
  drm/amdgpu: used cached gca values for cik_read_register
  Revert "drm/amdgpu: fix rmmod KCQ disable failed error"
  drm/amdgpu: drop experimental flag for raven

Andrew Jiang (1):
  drm/amd/display: Don't reject 3D timings

Andrey Grodzovsky (1):
  drm/amd/display: Switch to drm_atomic_helper_wait_for_flip_done

Bhawanpreet Lakha (1):
  drm/amd/display: Add null check for 24BPP (xfm and dpp)

Charlene Liu (2):
  drm/amd/display: fix seq issue: turn on clock before programming afmt.
  drm/amd/display: try to find matching audio inst for enc inst first

Christian König (2):
  drm/amdgpu: don't try to move pinned BOs
  drm/ttm: fix populate_and_map() functions once more

Colin Ian King (1):
  drm/amd/display: fix memory leaks on error exit return

Dmytro Laktyushkin (3):
  drm/amd/display: fix split recout calculation
  drm/amd/display: fix split recout offset
  drm/amd/display: fix split viewport rounding error

Eric Yang (1):
  drm/amd/display: Add timing validation against dongle cap

Harry Wentland (6):
  drm/amd/display: Fix amdgpu_dm bugs found by smatch
  drm/amd/display: Bunch of smatch error and warning fixes in DC
  drm/amd/display: Fix use before NULL check in validate_timing
  drm/amd/display: Fix hubp check in set_cursor_position
  drm/amd/display: Fix potential NULL and mem leak in create_links
  drm/amd/display: Fix couple more inconsistent NULL checks in dc_resource

Hersen Wu (2):
  drm/amd/display: Handle as MST first and then DP dongle if sink support 
both
  drm/amd/display: USB-C / thunderbolt dock specific workaround

Jerry (Fangzhi) Zuo (1):
  drm/amd/display: Check aux channel before MST resume

Jordan Lazare (1):
  drm/amd/display: Revert noisy assert messages

Leo (Sunpeng) Li (3):
  drm/amd/display: Should disable when new stream is null
  drm/amd/display: Do DC mode-change check when adding CRTCs
  drm/amd/display: Do not put drm_atomic_state on resume

Leo Liu (1):
  drm/amdgpu: move UVD/VCE and VCN structure out from union

Michel Dänzer (2):
  drm/amdgpu: Set adev->vcn.irq.num_types for VCN
  drm/amdgpu: Use unsigned ring indices in amdgpu_queue_mgr_map

Oded Gabbay (1):
  drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

Roman Li (2):
  drm/amd/display: Fix S3 topology change
  drm/amd/display: fix gamma setting

Shirish S (1):
  drm/amd/display: check plane state before validating fbc

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  18 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   3 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c  |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c  |   6 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   | 111 ++---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |  16 +++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  31 --
 .../gpu/drm/amd/display/dc/basics/log_helpers.c|   5 +
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  15 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 102 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 106 +++-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  54 ++
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|   9 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c |  10 +-
 .../drm/amd/display/dc/dce/dce_stream_encoder.c|   3 +
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  32 +++---
 .../drm/amd/display/dc/dce110/dce110_resource.c|  12 ++-
 .../display/dc/dce110/dce110_timing_generator.c|   8 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   6 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |   3 -
 drivers/gpu/drm/amd/display/dc/inc/core_status.h   |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   7 --
 drivers/gpu/drm/radeon/cik.c   

Re: [PATCH 1/2] drm/amd/display: Use macro for isnan check

[Alex Deucher]

On Wed, Nov 29, 2017 at 3:21 PM, Harry Wentland  wrote:
> In code provided by HW teams we do a NaN check on floats
> by comparing the number against itself. This confuses most
> people including myself. Macro it out to make it self-explanatory.
>
> Don't do a NaN check for int.
>
> Signed-off-by: Harry Wentland 
> ---
>  drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 18 --
>  1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> index b6abe0f3bb15..102b5db28402 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> @@ -25,37 +25,35 @@
>
>  #include "dcn_calc_math.h"
>
> +#define isNaN(number) number != number

To be on the safe side, you may want to add some parens around the
argument in case someone passes in an expression.  E.g.,

#define isNaN(number) ((number) != (number))

Alex

> +
>  float dcn_bw_mod(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 - arg1 * ((int) (arg1 / arg2));
>  }
>
>  float dcn_bw_min2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 < arg2 ? arg1 : arg2;
>  }
>
>  unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
>  {
> -   if (arg1 != arg1)
> -   return arg2;
> -   if (arg2 != arg2)
> -   return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
>  float dcn_bw_max2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
> --
> 2.14.1
>
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Re: [PATCH v2 1/2] drm/amd/display: Use macro for isnan check

[Alex Deucher]

On Wed, Nov 29, 2017 at 3:55 PM, Harry Wentland <harry.wentl...@amd.com> wrote:
> In code provided by HW teams we do a NaN check on floats
> by comparing the number against itself. This confuses most
> people including myself. Macro it out to make it self-explanatory.
>
> Don't do a NaN check for int.
>
> v2: parantheses around 'number' expression
>
> Signed-off-by: Harry Wentland <harry.wentl...@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 18 --
>  1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> index b6abe0f3bb15..ae38cdb80915 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> @@ -25,37 +25,35 @@
>
>  #include "dcn_calc_math.h"
>
> +#define isNaN(number) ((number) != (number))
> +
>  float dcn_bw_mod(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 - arg1 * ((int) (arg1 / arg2));
>  }
>
>  float dcn_bw_min2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 < arg2 ? arg1 : arg2;
>  }
>
>  unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
>  {
> -   if (arg1 != arg1)
> -   return arg2;
> -   if (arg2 != arg2)
> -   return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
>  float dcn_bw_max2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
> --
> 2.14.1
>
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[PATCH] drm/amd/display: add mod_freesync_user_enable to dm_connector_state

[Alex Deucher]

We don't currently expose variable refresh rate, but add the state to the
connector state to make it easier to maintain the support for it from a
hw support perspective while we figure out the uapi for drm.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c324c3b76fac..b2359bc4900d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1686,6 +1686,7 @@ struct dm_connector_state {
uint8_t underscan_vborder;
uint8_t underscan_hborder;
bool underscan_enable;
+   struct mod_freesync_user_enable user_enable;
 };
 
 #define to_dm_connector_state(x)\
-- 
2.13.6

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Re: [PATCH libdrm 3/3] amdgpu: Only remember the device's marketing name

[Alex Deucher]

On Fri, Dec 1, 2017 at 11:56 AM, Michel Dänzer <mic...@daenzer.net> wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> There's no point in keeping around the full table of marketing names,
> when amdgpu_get_marketing_name only ever returns the device's marketing
> name.
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  amdgpu/Android.mk|  3 +-
>  amdgpu/Makefile.am   |  5 +--
>  amdgpu/amdgpu_asic_id.c  | 88 
> 
>  amdgpu/amdgpu_device.c   | 23 ++---
>  amdgpu/amdgpu_internal.h | 11 ++
>  5 files changed, 28 insertions(+), 102 deletions(-)
>
> diff --git a/amdgpu/Android.mk b/amdgpu/Android.mk
> index ce273019..1f028d0b 100644
> --- a/amdgpu/Android.mk
> +++ b/amdgpu/Android.mk
> @@ -11,8 +11,7 @@ LOCAL_SHARED_LIBRARIES := libdrm
>  LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES)
>
>  LOCAL_CFLAGS := \
> -   -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\" \
> -   -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(shell egrep -ci 
> '^[0-9a-f]{4},.*[0-9a-f]+,' $(LIBDRM_TOP)/data/amdgpu.ids)
> +   -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\"
>
>  LOCAL_REQUIRED_MODULES := amdgpu.ids
>
> diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
> index 66f6f676..a1b0d05c 100644
> --- a/amdgpu/Makefile.am
> +++ b/amdgpu/Makefile.am
> @@ -31,10 +31,7 @@ AM_CFLAGS = \
> -I$(top_srcdir)/include/drm
>
>  libdrmdatadir = @libdrmdatadir@
> -ASIC_ID_TABLE_NUM_ENTRIES := $(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' \
> -   $(top_srcdir)/data/amdgpu.ids)
> -AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" \
> -   -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(ASIC_ID_TABLE_NUM_ENTRIES)
> +AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\"
>
>  libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
>  libdrm_amdgpu_ladir = $(libdir)
> diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
> index 0b5f2962..0c8925e5 100644
> --- a/amdgpu/amdgpu_asic_id.c
> +++ b/amdgpu/amdgpu_asic_id.c
> @@ -38,11 +38,13 @@
>  #include "amdgpu_drm.h"
>  #include "amdgpu_internal.h"
>
> -static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
> +static int parse_one_line(struct amdgpu_device *dev, const char *line)
>  {
> char *buf, *saveptr;
> char *s_did;
> +   uint32_t did;
> char *s_rid;
> +   uint32_t rid;
> char *s_name;
> char *endptr;
> int r = -EINVAL;
> @@ -60,19 +62,29 @@ static int parse_one_line(const char *line, struct 
> amdgpu_asic_id *id)
> if (!s_did)
> goto out;
>
> -   id->did = strtol(s_did, , 16);
> +   did = strtol(s_did, , 16);
> if (*endptr)
> goto out;
>
> +   if (did != dev->info.asic_id) {
> +   r = -EAGAIN;
> +   goto out;
> +   }
> +
> /* revision id */
> s_rid = strtok_r(NULL, ",", );
> if (!s_rid)
> goto out;
>
> -   id->rid = strtol(s_rid, , 16);
> +   rid = strtol(s_rid, , 16);
> if (*endptr)
> goto out;
>
> +   if (rid != dev->info.pci_rev_id) {
> +   r = -EAGAIN;
> +   goto out;
> +   }
> +
> /* marketing name */
> s_name = strtok_r(NULL, ",", );
> if (!s_name)
> @@ -84,8 +96,8 @@ static int parse_one_line(const char *line, struct 
> amdgpu_asic_id *id)
> if (strlen(s_name) == 0)
> goto out;
>
> -   id->marketing_name = strdup(s_name);
> -   if (id->marketing_name)
> +   dev->marketing_name = strdup(s_name);
> +   if (dev->marketing_name)
> r = 0;
> else
> r = -ENOMEM;
> @@ -96,17 +108,13 @@ out:
> return r;
>  }
>
> -void amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
> +void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
>  {
> -   struct amdgpu_asic_id *asic_id_table;
> -   struct amdgpu_asic_id *id;
> FILE *fp;
> char *line = NULL;
> size_t len = 0;
> ssize_t n;
> int line_num = 1;
> -   size_t table_size = 0;
> -   size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES;
> int r = 0;
>
> fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
> @@ -116,13 +124,6 @@ void amdgpu_parse_asic_ids(struct amdgpu_

Re: [PATCH 0/2] Move scheduler out of AMDGPU

[Alex Deucher]

On Fri, Dec 1, 2017 at 10:55 AM, Christian König
 wrote:
> Am 01.12.2017 um 16:28 schrieb Lucas Stach:
>>
>> Hi all,
>>
>> so this is the first step to make the marvelous AMDGPU scheduler useable
>> for other drivers. I have a (mostly) working prototype of Etnaviv using
>> the scheduler, but those patches need to keep baking for a while.
>>
>> I'm sending this out as I want to avoid rebasing this change too much
>> and don't want to take people by surprise when the Etnaviv implementation
>> surfaces. Also this might need some coordination between AMDGPU and
>> Etnaviv, which might be good to get going now.
>>
>> Please speak up now if you have any objections or comments.
>
>
> Looks good to me, but question is what is this based upon?
>
> I strongly assume drm-next, so question is now if we have any patches inside
> amd branches we should apply before doing this.

We have a bunch of changes queued up which will go usptream for 4.16.
See amd-staging-drm-next:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next
which is a mirror of our main development branch or:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.16-wip
which is what is currently queued for 4.16.

Alex

>
> CCing Andrey as well cause he has some tasks assigned around the scheduler
> as well.
>
> Regards,
> Christian.
>
>
>>
>> Regards,
>> Lucas
>>
>> Lucas Stach (2):
>>drm: move amd_gpu_scheduler into common location
>>drm/sched: move fence slab handling to module init/exit
>>
>>   drivers/gpu/drm/Kconfig|   5 +
>>   drivers/gpu/drm/Makefile   |   1 +
>>   drivers/gpu/drm/amd/amdgpu/Makefile|   5 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h|  16 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   8 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c|  38 +--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  12 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   8 -
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |   4 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_job.c|  22 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  14 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  12 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c  |  20 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h  |   2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   |   6 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|   8 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h|   4 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|   8 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h|   4 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|   8 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h|   2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c|  14 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   4 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  10 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   4 +-
>>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |   4 +-
>>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |   8 +-
>>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   8 +-
>>   drivers/gpu/drm/amd/scheduler/gpu_scheduler.h  | 185 --
>>   drivers/gpu/drm/scheduler/Makefile |   4 +
>>   .../gpu/drm/{amd => }/scheduler/gpu_scheduler.c| 281
>> +++--
>>   drivers/gpu/drm/{amd => }/scheduler/sched_fence.c  | 122 +
>>   include/drm/gpu_scheduler.h| 171 +
>>   .../drm/gpu_scheduler_trace.h  |  14 +-
>>   34 files changed, 525 insertions(+), 511 deletions(-)
>>   delete mode 100644 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
>>   create mode 100644 drivers/gpu/drm/scheduler/Makefile
>>   rename drivers/gpu/drm/{amd => }/scheduler/gpu_scheduler.c (64%)
>>   rename drivers/gpu/drm/{amd => }/scheduler/sched_fence.c (58%)
>>   create mode 100644 include/drm/gpu_scheduler.h
>>   rename drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h =>
>> include/drm/gpu_scheduler_trace.h (83%)
>>
>
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[PATCH 2/3] drm/amdgpu: drop scratch regs save and restore from GPU reset handling

[Alex Deucher]

The expectation is that the base driver doesn't mess with these.
Some components interact with these directly so let the components
handle these directly.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ca1cf8a71dda..046b9d5bc14d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2896,9 +2896,7 @@ static int amdgpu_reset(struct amdgpu_device *adev, 
uint64_t* reset_flags)
r = amdgpu_suspend(adev);
 
 retry:
-   amdgpu_atombios_scratch_regs_save(adev);
r = amdgpu_asic_reset(adev);
-   amdgpu_atombios_scratch_regs_restore(adev);
/* post card */
amdgpu_atom_asic_init(adev->mode_info.atom_context);
 
-- 
2.13.6

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Re: [PATCH] drm/amdgpu: setup the shared and private apertures on gfx9

[Alex Deucher]

On Fri, Dec 8, 2017 at 3:10 PM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> Same as previous asics.  This was not yet set for gfx9.

Ping?

>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  8 
>  2 files changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 3fd13b77e71e..7564f87b084e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1529,11 +1529,18 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device 
> *adev)
> for (i = 0; i < 16; i++) {
> soc15_grbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> -   tmp = 0;
> -   tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
> -   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> -   WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
> -   WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
> +   if (i == 0) {
> +   tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
> +   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> +   WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
> +   WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
> +   } else {
> +   tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
> +   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> +   WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
> +   tmp = adev->mc.shared_aperture_start >> 48;
> +   WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
> +   }
> }
> soc15_grbm_select(adev, 0, 0, 0, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 695e0eada1cd..dbfb746a390c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -497,6 +497,14 @@ static int gmc_v9_0_early_init(void *handle)
> gmc_v9_0_set_gart_funcs(adev);
> gmc_v9_0_set_irq_funcs(adev);
>
> +   adev->mc.shared_aperture_start = 0x2000ULL;
> +   adev->mc.shared_aperture_end =
> +   adev->mc.shared_aperture_start + (4ULL << 30) - 1;
> +   adev->mc.private_aperture_start =
> +   adev->mc.shared_aperture_end + 1;
> +   adev->mc.private_aperture_end =
> +   adev->mc.private_aperture_start + (4ULL << 30) - 1;
> +
> return 0;
>  }
>
> --
> 2.13.6
>
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Re: [PATCH 2/2] drm/amdgpu:impl virt_gart_flush_tlbs

[Alex Deucher]

On Tue, Dec 12, 2017 at 10:42 PM, Monk Liu  wrote:
> a new gart flush tlb function implemented for SRIOV,
> and invoke it during RUNTIME for gart flush TLBs
>
> this could avoid the issue that gart flush (via CPU MMIO)
> being interrupted by word switch which lead to DMAR error
> on Host/IOMMU side, with this function the gart flush
> tlbs always run on KIQ with single PM4 package so it won't
> get interrupted before the flushing finished.
>
> Change-Id: I0849658d7945c3874b3cc0d9369a50e1aedb8312
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 27 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c|  3 +++
>  3 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index e7dfb7b..7a6ef64 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -172,6 +172,33 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, 
> uint32_t reg, uint32_t v)
> DRM_ERROR("wait for kiq fence error: %ld\n", r);
>  }
>
> +int amdgpu_virt_gart_flush_tlbs(struct amdgpu_device *adev)
> +{
> +   struct amdgpu_kiq *kiq = >gfx.kiq;
> +   struct amdgpu_ring *ring = >ring;
> +   unsigned long flags;
> +   signed long r;
> +   uint32_t seq;
> +
> +   if(!ring->funcs->emit_invalidate_tlbs)
> +   return -ENOENT;
> +
> +   spin_lock_irqsave(>ring_lock, flags);
> +   amdgpu_ring_alloc(ring, 16);
> +   amdgpu_ring_emit_invalidate_tlbs(ring);
> +   amdgpu_fence_emit_polling(ring, );
> +   amdgpu_ring_commit(ring);
> +   spin_unlock_irqrestore(>ring_lock, flags);
> +
> +   r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> +   if (r < 1) {
> +   DRM_ERROR("wait for kiq invalidate tlbs error: %ld\n", r);
> +   return -ETIME;
> +   }
> +
> +   return 0;
> +}
> +
>  /**
>   * amdgpu_virt_request_full_gpu() - request full gpu access
>   * @amdgpu:amdgpu device.
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 6a83425..935fed3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -297,5 +297,6 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj, 
> unsigned long obj_size,
> unsigned int key,
> unsigned int chksum);
>  void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
> +int amdgpu_virt_gart_flush_tlbs(struct amdgpu_device *adev);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 1b5dfcc..a195039 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -332,6 +332,9 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct 
> amdgpu_device *adev,
> /* flush hdp cache */
> adev->nbio_funcs->hdp_flush(adev);
>
> +   if (amdgpu_sriov_runtime(adev) && !amdgpu_virt_gart_flush_tlbs(adev))
> +   return;


Do we need a fw version check for the flush_tlb packet?

Alex

> +
> spin_lock(>mc.invalidate_lock);
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> --
> 2.7.4
>
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[pull] amdgpu and ttm drm-fixes-4.15

[Alex Deucher]

Hi Dave,

Nothing too major here.  A couple more ttm fixes for huge page and a kiq
fix for amdgpu.

The following changes since commit 90eeb3aa34831ff3d031589c0c24892eb8a07e51:

  Merge tag 'drm-misc-fixes-2017-12-07' of 
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2017-12-08 08:17:53 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.15

for you to fetch changes up to 0507f438ea19d4280006467ba02956f6a693deca:

  drm/amdgpu: fix MAP_QUEUES paramter (2017-12-12 15:40:11 -0500)


Monk Liu (3):
  drm/ttm: fix incorrect calculate on shrink_pages
  drm/ttm: max_cpages is in unit of native page
  drm/amdgpu: fix MAP_QUEUES paramter

 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
 drivers/gpu/drm/ttm/ttm_page_alloc.c  | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)
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Re: [PATCH] drm/amdgpu: implement 2+1 PD support for Raven v2

[Alex Deucher]

On Thu, Dec 14, 2017 at 7:03 AM, Christian König
 wrote:
> Instead of falling back to 2 level and very limited address space use
> 2+1 PD support and 128TB + 512GB of virtual address space.
>
> v2: cleanup defines, rebase on top of level enum
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h   |  6 
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 42 ++-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 26 ++---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 49 
> 
>  5 files changed, 89 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 0cb2235f4798..8ac5875472bd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -541,6 +541,7 @@ struct amdgpu_mc {
> u64 private_aperture_end;
> /* protects concurrent invalidation */
> spinlock_t  invalidate_lock;
> +   booltranslate_further;
>  };
>
>  /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 1056484de0e3..edd2ea52dc00 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -70,6 +70,12 @@ struct amdgpu_bo_list_entry;
>  /* PDE is handled as PTE for VEGA10 */
>  #define AMDGPU_PDE_PTE (1ULL << 54)
>
> +/* PTE is handled as PDE for VEGA10 (Translate Further) */
> +#define AMDGPU_PTE_TF  (1ULL << 56)
> +
> +/* PDE Block Fragment Size for VEGA10 */
> +#define AMDGPU_PDE_BFS(a)  ((uint64_t)a << 59)

Safer to put parens around the a in case some one passes in an expression.


> +
>  /* VEGA10 only */
>  #define AMDGPU_PTE_MTYPE(a)((uint64_t)a << 57)
>  #define AMDGPU_PTE_MTYPE_MASK  AMDGPU_PTE_MTYPE(3ULL)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 1d392f186e0d..197005e54d78 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -143,8 +143,15 @@ static void gfxhub_v1_0_init_cache_regs(struct 
> amdgpu_device *adev)
> WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
>
> tmp = mmVM_L2_CNTL3_DEFAULT;
> -   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
> -   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
> +   if (adev->mc.translate_further) {
> +   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
> +   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> +   L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
> +   } else {
> +   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
> +   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> +   L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
> +   }

Is this correct?  Aren't the cases reversed here? Won't this change 2
and 4 level?


> WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
>
> tmp = mmVM_L2_CNTL4_DEFAULT;
> @@ -182,31 +189,40 @@ static void 
> gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
>
>  static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
>  {
> -   int i;
> +   unsigned num_level, block_size;
> uint32_t tmp;
> +   int i;
> +
> +   num_level = adev->vm_manager.num_level;
> +   block_size = adev->vm_manager.block_size;
> +   if (adev->mc.translate_further)
> +   num_level -= 1;
> +   else
> +   block_size -= 9;
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> -   adev->vm_manager.num_level);
> +   num_level);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> -   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
> +   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> -   DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 
> 1);
> +   
> DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
> +   1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> -   PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
> +   PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> -   

Re: [trivial PATCH] treewide: Align function definition open/close braces

[Alex Deucher]

On Sun, Dec 17, 2017 at 7:28 PM, Joe Perches <j...@perches.com> wrote:
> Some functions definitions have either the initial open brace and/or
> the closing brace outside of column 1.
>
> Move those braces to column 1.
>
> This allows various function analyzers like gnu complexity to work
> properly for these modified functions.
>
> Miscellanea:
>
> o Remove extra trailing ; and blank line from xfs_agf_verify
>
> Signed-off-by: Joe Perches <j...@perches.com>
> ---
> git diff -w shows no difference other than the above 'Miscellanea'
>
> (this is against -next, but it applies against Linus' tree
>  with a couple offsets)
>
>  arch/x86/include/asm/atomic64_32.h   |  2 +-
>  drivers/acpi/custom_method.c |  2 +-
>  drivers/acpi/fan.c   |  2 +-
>  drivers/gpu/drm/amd/display/dc/core/dc.c |  2 +-

For amdgpu:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>

>  drivers/media/i2c/msp3400-kthreads.c |  2 +-
>  drivers/message/fusion/mptsas.c  |  2 +-
>  drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c |  2 +-
>  drivers/net/wireless/ath/ath9k/xmit.c|  2 +-
>  drivers/platform/x86/eeepc-laptop.c  |  2 +-
>  drivers/rtc/rtc-ab-b5ze-s3.c |  2 +-
>  drivers/scsi/dpt_i2o.c   |  2 +-
>  drivers/scsi/sym53c8xx_2/sym_glue.c  |  2 +-
>  fs/locks.c   |  2 +-
>  fs/ocfs2/stack_user.c|  2 +-
>  fs/xfs/libxfs/xfs_alloc.c|  5 ++---
>  fs/xfs/xfs_export.c  |  2 +-
>  kernel/audit.c   |  6 +++---
>  kernel/trace/trace_printk.c  |  4 ++--
>  lib/raid6/sse2.c | 14 +++---
>  sound/soc/fsl/fsl_dma.c  |  2 +-
>  20 files changed, 30 insertions(+), 31 deletions(-)
>
> diff --git a/arch/x86/include/asm/atomic64_32.h 
> b/arch/x86/include/asm/atomic64_32.h
> index 97c46b8169b7..d4d4883080fa 100644
> --- a/arch/x86/include/asm/atomic64_32.h
> +++ b/arch/x86/include/asm/atomic64_32.h
> @@ -122,7 +122,7 @@ static inline long long atomic64_read(const atomic64_t *v)
> long long r;
> alternative_atomic64(read, "=" (r), "c" (v) : "memory");
> return r;
> - }
> +}
>
>  /**
>   * atomic64_add_return - add and return
> diff --git a/drivers/acpi/custom_method.c b/drivers/acpi/custom_method.c
> index c68e72414a67..e967c1173ba3 100644
> --- a/drivers/acpi/custom_method.c
> +++ b/drivers/acpi/custom_method.c
> @@ -94,7 +94,7 @@ static void __exit acpi_custom_method_exit(void)
>  {
> if (cm_dentry)
> debugfs_remove(cm_dentry);
> - }
> +}
>
>  module_init(acpi_custom_method_init);
>  module_exit(acpi_custom_method_exit);
> diff --git a/drivers/acpi/fan.c b/drivers/acpi/fan.c
> index 6cf4988206f2..3563103590c6 100644
> --- a/drivers/acpi/fan.c
> +++ b/drivers/acpi/fan.c
> @@ -219,7 +219,7 @@ fan_set_cur_state(struct thermal_cooling_device *cdev, 
> unsigned long state)
> return fan_set_state_acpi4(device, state);
> else
> return fan_set_state(device, state);
> - }
> +}
>
>  static const struct thermal_cooling_device_ops fan_cooling_ops = {
> .get_max_state = fan_get_max_state,
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index d1488d5ee028..1e0d1e7c5324 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -461,7 +461,7 @@ static void disable_dangling_plane(struct dc *dc, struct 
> dc_state *context)
>   
> **/
>
>  struct dc *dc_create(const struct dc_init_data *init_params)
> - {
> +{
> struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
> unsigned int full_pipe_count;
>
> diff --git a/drivers/media/i2c/msp3400-kthreads.c 
> b/drivers/media/i2c/msp3400-kthreads.c
> index 4dd01e9f553b..dc6cb8d475b3 100644
> --- a/drivers/media/i2c/msp3400-kthreads.c
> +++ b/drivers/media/i2c/msp3400-kthreads.c
> @@ -885,7 +885,7 @@ static int msp34xxg_modus(struct i2c_client *client)
>  }
>
>  static void msp34xxg_set_source(struct i2c_client *client, u16 reg, int in)
> - {
> +{
> struct msp_state *state = to_state(i2c_get_clientdata(client));
> int source, matrix;
>
> diff --git a/drivers

Re: [PATCH 5/5] drm/amd/pp: implement force_dpm_level on rv

[Alex Deucher]

On Mon, Dec 18, 2017 at 6:50 AM, Rex Zhu <rex@amd.com> wrote:
> user can change engine/mclk/soc/vcn clocks on Rv
>
> v3: add smu version check
> v2: fix no return statement
>
> Change-Id: I4cba759701ab031085a687102de6566771f4494f
> Signed-off-by: Rex Zhu <rex@amd.com>

Patches 1-4:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 127 
> +
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  15 +++
>  2 files changed, 142 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index ae11a85..91f1912 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -484,6 +484,133 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
>  static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> enum amd_dpm_forced_level level)
>  {
> +   uint32_t version;
> +
> +   smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
> +   rv_read_arg_from_smc(hwmgr, );
> +   if (version < 0x1E3700) {
> +   pr_info("smu firmware version too old, can not set dpm 
> level\n");
> +   return 0;
> +   }

I think it would be better to store this in hwmgr state than to look
it up every time.  We need to add fetch it earlier anyway so that we
export the smu version on APUs properly so we can fix the SMU fw
version we expose to userspace (rather than always reporting 0 for
APUs).

Alex

> +
> +   switch (level) {
> +   case AMD_DPM_FORCED_LEVEL_HIGH:
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinGfxClk,
> +   RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinFclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinSocclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinVcn,
> +   RAVEN_UMD_PSTATE_VCE);
> +
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetSoftMaxGfxClk,
> +   RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetSoftMaxFclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetSoftMaxSocclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetSoftMaxVcn,
> +   RAVEN_UMD_PSTATE_VCE);
> +   break;
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinGfxClk,
> +   RAVEN_UMD_PSTATE_MIN_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetSoftMaxGfxClk,
> +   RAVEN_UMD_PSTATE_MIN_GFXCLK);
> +   break;
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinFclkByFreq,
> +   RAVEN_UMD_PSTATE_MIN_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetSoftMaxFclkByFreq,
> +   RAVEN_UMD_PSTATE_MIN_FCLK);
> +   break;
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +  

Re: [PATCH 2/4] drm/amd/pp: update smu_version value for CI/VI

[Alex Deucher]

On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <rex@amd.com> wrote:
> Change-Id: Ia55a0bc2cde45cb995d92ff054e57b07ed548f08

Missing your signed-off-by.  Please also include a patch description.  E.g.,
Set the new common smu firmware version for smu7 parts (CI and VI).

With those things fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c  | 1 +
>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c| 2 +-
>  3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index c6c741a..0b4a556 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -2316,6 +2316,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
> cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, );
>
> hwmgr->is_kicker = info.is_kicker;
> +   hwmgr->smu_version = info.version;
> byte_count = info.image_size;
> src = (uint8_t *)info.kptr;
> start_addr = info.ucode_start_address;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index d75bb99..1253126 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -204,7 +204,7 @@ static int iceland_smu_upload_firmware_image(struct 
> pp_hwmgr *hwmgr)
> pr_err("[ powerplay ] SMC address is beyond the SMC RAM 
> area\n");
> return -EINVAL;
> }
> -
> +   hwmgr->smu_version = info.version;
> /* wait for smc boot up */
> PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
>  RCU_UC_EVENTS, boot_seq_done, 0);
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 7f5359a..cb95e88 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -535,7 +535,7 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
> smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), );
>
> hwmgr->is_kicker = info.is_kicker;
> -
> +   hwmgr->smu_version = info.version;
> result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, 
> (uint32_t *)info.kptr, SMU7_SMC_SIZE);
>
> return result;
> --
> 1.9.1
>
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Re: [PATCH 3/4] drm/amd/pp: get Rv smu_version and notify amdgpu

[Alex Deucher]

On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <rex@amd.com> wrote:

Please include a patch description.  E.g.,
The smu firmware is loaded by the sbios on APUs, so query it from the
smu and update the
smu fw version info that is reported to userspace.

With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

Can you update CZ/ST as well if you get a chance?

Thanks,

Alex


> Signed-off-by: Rex Zhu <rex@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 3 +++
>  drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 8 
>  2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index 85d2149..13607e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -801,6 +801,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
> *cgs_device,
> else
> strcpy(fw_name, 
> "amdgpu/vega10_smc.bin");
> break;
> +   case CHIP_RAVEN:
> +   adev->pm.fw_version = info->version;
> +   return 0;
> default:
> DRM_ERROR("SMC firmware not supported\n");
> return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> index b98ade6..2d662b4 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> @@ -305,6 +305,14 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr)
>
>  static int rv_start_smu(struct pp_hwmgr *hwmgr)
>  {
> +   struct cgs_firmware_info info = {0};
> +
> +   smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
> +   rv_read_arg_from_smc(hwmgr, >smu_version);
> +   info.version = hwmgr->smu_version >> 8;
> +
> +   cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, );
> +
> if (rv_verify_smc_interface(hwmgr))
> return -EINVAL;
> if (rv_smc_enable_sdma(hwmgr))
> --
> 1.9.1
>
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Re: [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr

[Alex Deucher]

On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <rex@amd.com> wrote:

Please include a better patch description.  Something like:
Move the smu_version to common code so it can be shared by other asics.

With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> Change-Id: Ie8c32663aa0d61a1dfdd8e019509cb551f137aa0
> Signed-off-by: Rex Zhu <rex@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 8 
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 -
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 1 +
>  3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index f0295fa..2d55dab 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -426,9 +426,9 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr 
> *hwmgr)
> data->smu_features[GNLD_VR0HOT].supported = true;
>
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
> -   vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
> +   vega10_read_arg_from_smc(hwmgr, &(hwmgr->smu_version));
> /* ACG firmware has major version 5 */
> -   if ((data->smu_version & 0xff00) == 0x500)
> +   if ((hwmgr->smu_version & 0xff00) == 0x500)
> data->smu_features[GNLD_ACG].supported = true;
>
> if (data->registry_data.didt_support)
> @@ -2879,8 +2879,8 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr 
> *hwmgr)
> "DPM is already running right , skipping 
> re-enablement!",
> return 0);
>
> -   if ((data->smu_version == 0x001c2c00) ||
> -   (data->smu_version == 0x001c2d00)) {
> +   if ((hwmgr->smu_version == 0x001c2c00) ||
> +   (hwmgr->smu_version == 0x001c2d00)) {
> tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
> PP_ASSERT_WITH_CODE(!tmp_result,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 8f7358c..e8507ff 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -387,7 +387,6 @@ struct vega10_hwmgr {
> struct vega10_smc_state_table  smc_state_table;
>
> uint32_t   config_telemetry;
> -   uint32_t   smu_version;
> uint32_t   acg_loop_state;
> uint32_t   mem_channels;
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 39eedbc..565fe08 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -692,6 +692,7 @@ enum PP_TABLE_VERSION {
>  struct pp_hwmgr {
> uint32_t chip_family;
> uint32_t chip_id;
> +   uint32_t smu_version;
>
> uint32_t pp_table_version;
> void *device;
> --
> 1.9.1
>
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Re: [PATCH 4/4] drm/amd/pp: implement force_dpm_level on rv

[Alex Deucher]

On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <rex@amd.com> wrote:
> user can change engine/mclk/soc/vcn clocks on Rv
>
> v3: add smu version check
> v2: fix no return statement

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

>
> Signed-off-by: Rex Zhu <rex@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 123 
> +
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  15 +++
>  2 files changed, 138 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index ae11a85..569073e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -484,6 +484,129 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
>  static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> enum amd_dpm_forced_level level)
>  {
> +   if (hwmgr->smu_version < 0x1E3700) {
> +   pr_info("smu firmware version too old, can not set dpm 
> level\n");
> +   return 0;
> +   }
> +
> +   switch (level) {
> +   case AMD_DPM_FORCED_LEVEL_HIGH:
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinGfxClk,
> +   RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinFclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinSocclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinVcn,
> +   RAVEN_UMD_PSTATE_VCE);
> +
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetSoftMaxGfxClk,
> +   RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetSoftMaxFclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetSoftMaxSocclkByFreq,
> +   RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetSoftMaxVcn,
> +   RAVEN_UMD_PSTATE_VCE);
> +   break;
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinGfxClk,
> +   RAVEN_UMD_PSTATE_MIN_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetSoftMaxGfxClk,
> +   RAVEN_UMD_PSTATE_MIN_GFXCLK);
> +   break;
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinFclkByFreq,
> +   RAVEN_UMD_PSTATE_MIN_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetSoftMaxFclkByFreq,
> +   RAVEN_UMD_PSTATE_MIN_FCLK);
> +   break;
> +   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   PPSMC_MSG_SetHardMinGfxClk,
> +   RAVEN_UMD_PSTATE_GFXCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHardMinFclkByFreq,
> +   RAVEN_UMD_PSTATE_FCLK);
> +   smum_send_msg_to_smc_with_parameter(hwmgr,
> +   
> PPSMC_MSG_SetHa

[PATCH 2/2] drm/amdgpu: use defines for mmBIF_IOV_FUNC_IDENTIFIER fields

[Alex Deucher]

Rather than magic numbers.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index c59b37365e4d..da2b99c2d95f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -455,11 +455,10 @@ static void vi_detect_hw_virtualization(struct 
amdgpu_device *adev)
adev->asic_type == CHIP_FIJI) {
   reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
   /* bit0: 0 means pf and 1 means vf */
-  /* bit31: 0 means disable IOV and 1 means enable */
-  if (reg & 1)
+  if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
   adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
-
-  if (reg & 0x8000)
+  /* bit31: 0 means disable IOV and 1 means enable */
+  if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
   adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
}
 
-- 
2.13.6

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[PATCH 1/2] drm/amdgpu: only check mmBIF_IOV_FUNC_IDENTIFIER on tonga/fiji

[Alex Deucher]

We only support SR-IOV on tonga/fiji.  Don't check this register
on other VI parts.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index d9bb26322850..c59b37365e4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -449,14 +449,19 @@ static bool vi_read_bios_from_rom(struct amdgpu_device 
*adev,
 
 static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
 {
-   uint32_t reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
-   /* bit0: 0 means pf and 1 means vf */
-   /* bit31: 0 means disable IOV and 1 means enable */
-   if (reg & 1)
-   adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
-
-   if (reg & 0x8000)
-   adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
+   uint32_t reg = 0;
+
+   if (adev->asic_type == CHIP_TONGA ||
+   adev->asic_type == CHIP_FIJI) {
+  reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
+  /* bit0: 0 means pf and 1 means vf */
+  /* bit31: 0 means disable IOV and 1 means enable */
+  if (reg & 1)
+  adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
+
+  if (reg & 0x8000)
+  adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
+   }
 
if (reg == 0) {
if (is_virtual_machine()) /* passthrough mode exclus sr-iov 
mode */
-- 
2.13.6

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[PATCH 02/16] drm/amdgpu: use consistent naming for static funcs in amdgpu_device.c

[Alex Deucher]

Prefix the functions with device or device_ip for functions which
deal with ip blocks for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 176 +++--
 1 file changed, 90 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7233e69e2aa6..4b4ccf3456fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -332,7 +332,7 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device 
*adev,
BUG();
 }
 
-static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
+static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 {
return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
   PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
@@ -341,7 +341,7 @@ static int amdgpu_vram_scratch_init(struct amdgpu_device 
*adev)
   (void **)>vram_scratch.ptr);
 }
 
-static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
+static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 {
amdgpu_bo_free_kernel(>vram_scratch.robj, NULL, NULL);
 }
@@ -391,14 +391,14 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev)
  * GPU doorbell aperture helpers function.
  */
 /**
- * amdgpu_doorbell_init - Init doorbell driver information.
+ * amdgpu_device_doorbell_init - Init doorbell driver information.
  *
  * @adev: amdgpu_device pointer
  *
  * Init doorbell driver information (CIK)
  * Returns 0 on success, error on failure.
  */
-static int amdgpu_doorbell_init(struct amdgpu_device *adev)
+static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 {
/* No doorbell on SI hardware generation */
if (adev->asic_type < CHIP_BONAIRE) {
@@ -431,13 +431,13 @@ static int amdgpu_doorbell_init(struct amdgpu_device 
*adev)
 }
 
 /**
- * amdgpu_doorbell_fini - Tear down doorbell driver information.
+ * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
  *
  * @adev: amdgpu_device pointer
  *
  * Tear down doorbell driver information (CIK)
  */
-static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
+static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 {
iounmap(adev->doorbell.ptr);
adev->doorbell.ptr = NULL;
@@ -477,20 +477,20 @@ void amdgpu_doorbell_get_kfd_info(struct amdgpu_device 
*adev,
 }
 
 /*
- * amdgpu_wb_*()
+ * amdgpu_device_wb_*()
  * Writeback is the method by which the GPU updates special pages in memory
  * with the status of certain GPU events (fences, ring pointers,etc.).
  */
 
 /**
- * amdgpu_wb_fini - Disable Writeback and free memory
+ * amdgpu_device_wb_fini - Disable Writeback and free memory
  *
  * @adev: amdgpu_device pointer
  *
  * Disables Writeback and frees the Writeback memory (all asics).
  * Used at driver shutdown.
  */
-static void amdgpu_wb_fini(struct amdgpu_device *adev)
+static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 {
if (adev->wb.wb_obj) {
amdgpu_bo_free_kernel(>wb.wb_obj,
@@ -501,7 +501,7 @@ static void amdgpu_wb_fini(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_wb_init- Init Writeback driver info and allocate memory
+ * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
  *
  * @adev: amdgpu_device pointer
  *
@@ -509,7 +509,7 @@ static void amdgpu_wb_fini(struct amdgpu_device *adev)
  * Used at driver startup.
  * Returns 0 on success or an -error on failure.
  */
-static int amdgpu_wb_init(struct amdgpu_device *adev)
+static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 {
int r;
 
@@ -770,7 +770,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
  cmd & ~PCI_COMMAND_MEMORY);
 
/* Free the VRAM and doorbell BAR, we most likely need to move both. */
-   amdgpu_doorbell_fini(adev);
+   amdgpu_device_doorbell_fini(adev);
if (adev->asic_type >= CHIP_BONAIRE)
pci_release_resource(adev->pdev, 2);
 
@@ -787,7 +787,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
/* When the doorbell or fb BAR isn't available we have no chance of
 * using the device.
 */
-   r = amdgpu_doorbell_init(adev);
+   r = amdgpu_device_doorbell_init(adev);
if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
return -ENODEV;
 
@@ -900,7 +900,7 @@ void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 
 /* if we get transitioned to only one device, take VGA back */
 /**
- * amdgpu_vga_set_decode - enable/disable vga decode
+ * amdgpu_device_vga_set_decode - enable/disable vga decode
  *
  * @cookie: amdgpu_device pointer
  * @state: enable/disable vga decode
@@ -908,7 +908,7 @@ void amdgpu_dummy_page_fini(

[PATCH 07/16] drm/amdgpu: rename amdgpu_pci_config_reset

[Alex Deucher]

add device for consistency with other functions in this file.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c| 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ba57d0d6744f..9b595d74ea8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1902,7 +1902,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 /* Common functions */
 int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, 
bool force);
 bool amdgpu_need_backup(struct amdgpu_device *adev);
-void amdgpu_pci_config_reset(struct amdgpu_device *adev);
+void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
 bool amdgpu_need_post(struct amdgpu_device *adev);
 void amdgpu_update_display_priority(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2a4c49875abe..b93308e2353c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -377,7 +377,7 @@ void amdgpu_device_program_register_sequence(struct 
amdgpu_device *adev,
}
 }
 
-void amdgpu_pci_config_reset(struct amdgpu_device *adev)
+void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 {
pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 39d49712f8c9..132ba226f289 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1246,7 +1246,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device 
*adev)
/* disable BM */
pci_clear_master(adev->pdev);
/* reset */
-   amdgpu_pci_config_reset(adev);
+   amdgpu_device_pci_config_reset(adev);
 
udelay(100);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0b57c5d24510..0e1202914fa8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -667,7 +667,7 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device 
*adev)
/* disable BM */
pci_clear_master(adev->pdev);
/* reset */
-   amdgpu_pci_config_reset(adev);
+   amdgpu_device_pci_config_reset(adev);
 
udelay(100);
 
-- 
2.13.6

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[PATCH 15/16] drm/amdgpu: move amdgpu_need_backup to amdgpu_object.c

[Alex Deucher]

It's the only place it's used.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4e9e5b4b1927..bb12d68c21d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1892,7 +1892,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 /* Common functions */
 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
  struct amdgpu_job* job, bool force);
-bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
 bool amdgpu_device_need_post(struct amdgpu_device *adev);
 void amdgpu_update_display_priority(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8863616c5c4c..6961bf208660 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2426,14 +2426,6 @@ static int amdgpu_device_ip_post_soft_reset(struct 
amdgpu_device *adev)
return 0;
 }
 
-bool amdgpu_need_backup(struct amdgpu_device *adev)
-{
-   if (adev->flags & AMD_IS_APU)
-   return false;
-
-   return amdgpu_gpu_recovery;
-}
-
 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
  struct amdgpu_ring *ring,
  struct amdgpu_bo *bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 86340cfa6be7..4feee9927bce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -37,6 +37,14 @@
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
 
+static bool amdgpu_need_backup(struct amdgpu_device *adev)
+{
+   if (adev->flags & AMD_IS_APU)
+   return false;
+
+   return amdgpu_gpu_recovery;
+}
+
 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
-- 
2.13.6

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[PATCH 01/16] drm/amdgpu: move atom functions from amdgpu_device.c

[Alex Deucher]

and move them to amdgpu_atombios.c for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 236 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 231 --
 3 files changed, 236 insertions(+), 235 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index ffaf0534e33c..bf872f694f50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -27,6 +27,7 @@
 #include 
 #include "amdgpu.h"
 #include "amdgpu_atombios.h"
+#include "amdgpu_atomfirmware.h"
 #include "amdgpu_i2c.h"
 
 #include "atom.h"
@@ -1699,7 +1700,7 @@ void amdgpu_atombios_scratch_regs_lock(struct 
amdgpu_device *adev, bool lock)
WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
 }
 
-void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
+static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
 {
uint32_t bios_2_scratch, bios_6_scratch;
 
@@ -1776,7 +1777,7 @@ void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 
num_bytes, bool to_le)
 #endif
 }
 
-int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
+static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
 {
struct atom_context *ctx = adev->mode_info.atom_context;
int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
@@ -1819,3 +1820,234 @@ int amdgpu_atombios_allocate_fb_scratch(struct 
amdgpu_device *adev)
ctx->scratch_size_bytes = usage_bytes;
return 0;
 }
+
+/* ATOM accessor methods */
+/*
+ * ATOM is an interpreted byte code stored in tables in the vbios.  The
+ * driver registers callbacks to access registers and the interpreter
+ * in the driver parses the tables and executes then to program specific
+ * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
+ * atombios.h, and atom.c
+ */
+
+/**
+ * cail_pll_read - read PLL register
+ *
+ * @info: atom card_info pointer
+ * @reg: PLL register offset
+ *
+ * Provides a PLL register accessor for the atom interpreter (r4xx+).
+ * Returns the value of the PLL register.
+ */
+static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
+{
+   return 0;
+}
+
+/**
+ * cail_pll_write - write PLL register
+ *
+ * @info: atom card_info pointer
+ * @reg: PLL register offset
+ * @val: value to write to the pll register
+ *
+ * Provides a PLL register accessor for the atom interpreter (r4xx+).
+ */
+static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+
+}
+
+/**
+ * cail_mc_read - read MC (Memory Controller) register
+ *
+ * @info: atom card_info pointer
+ * @reg: MC register offset
+ *
+ * Provides an MC register accessor for the atom interpreter (r4xx+).
+ * Returns the value of the MC register.
+ */
+static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
+{
+   return 0;
+}
+
+/**
+ * cail_mc_write - write MC (Memory Controller) register
+ *
+ * @info: atom card_info pointer
+ * @reg: MC register offset
+ * @val: value to write to the pll register
+ *
+ * Provides a MC register accessor for the atom interpreter (r4xx+).
+ */
+static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+
+}
+
+/**
+ * cail_reg_write - write MMIO register
+ *
+ * @info: atom card_info pointer
+ * @reg: MMIO register offset
+ * @val: value to write to the pll register
+ *
+ * Provides a MMIO register accessor for the atom interpreter (r4xx+).
+ */
+static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+   struct amdgpu_device *adev = info->dev->dev_private;
+
+   WREG32(reg, val);
+}
+
+/**
+ * cail_reg_read - read MMIO register
+ *
+ * @info: atom card_info pointer
+ * @reg: MMIO register offset
+ *
+ * Provides an MMIO register accessor for the atom interpreter (r4xx+).
+ * Returns the value of the MMIO register.
+ */
+static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
+{
+   struct amdgpu_device *adev = info->dev->dev_private;
+   uint32_t r;
+
+   r = RREG32(reg);
+   return r;
+}
+
+/**
+ * cail_ioreg_write - write IO register
+ *
+ * @info: atom card_info pointer
+ * @reg: IO register offset
+ * @val: value to write to the pll register
+ *
+ * Provides a IO register accessor for the atom interpreter (r4xx+).
+ */
+static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t 
val)
+{
+   struct amdgpu_device *adev = info->dev->dev_private;
+
+   WREG32_IO(reg, val);
+}
+
+/**
+ * cail_ioreg_read - read IO register
+ *
+ * @info: atom card_info pointer
+ * @reg: IO register offset
+ *
+ * Provides an IO register accessor for the atom interpreter (r4xx+).
+ * Returns the val

[PATCH 11/16] drm/amdgpu: rename ip block helper functions

[Alex Deucher]

add device to the name for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  38 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  50 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  18 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  18 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|  16 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   |  88 +--
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  18 ++--
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/si.c|  54 ++--
 drivers/gpu/drm/amd/amdgpu/soc15.c |  46 +-
 drivers/gpu/drm/amd/amdgpu/vi.c| 132 ++---
 14 files changed, 252 insertions(+), 246 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96bbd143efdb..30c9c82e7029 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -224,17 +224,18 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
 };
 
-int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type,
- enum amd_clockgating_state state);
-int amdgpu_set_powergating_state(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type,
- enum amd_powergating_state state);
-void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
-int amdgpu_wait_for_idle(struct amdgpu_device *adev,
-enum amd_ip_block_type block_type);
-bool amdgpu_is_idle(struct amdgpu_device *adev,
-   enum amd_ip_block_type block_type);
+int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+  enum amd_ip_block_type block_type,
+  enum amd_clockgating_state state);
+int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+  enum amd_ip_block_type block_type,
+  enum amd_powergating_state state);
+void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
+   u32 *flags);
+int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
+  enum amd_ip_block_type block_type);
+bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
+ enum amd_ip_block_type block_type);
 
 #define AMDGPU_MAX_IP_NUM 16
 
@@ -259,15 +260,16 @@ struct amdgpu_ip_block {
const struct amdgpu_ip_block_version *version;
 };
 
-int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
-   enum amd_ip_block_type type,
-   u32 major, u32 minor);
+int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
+  enum amd_ip_block_type type,
+  u32 major, u32 minor);
 
-struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
-enum amd_ip_block_type type);
+struct amdgpu_ip_block *
+amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
+ enum amd_ip_block_type type);
 
-int amdgpu_ip_block_add(struct amdgpu_device *adev,
-   const struct amdgpu_ip_block_version *ip_block_version);
+int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
+  const struct amdgpu_ip_block_version 
*ip_block_version);
 
 /* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */
 struct amdgpu_buffer_funcs {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index c04f44a90392..a29362f9ef41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -277,7 +277,7 @@ static int acp_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
const struct amdgpu_ip_block *ip_block =
-   amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
+   amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
 
if (!ip_block)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index df800f268a20..91741eeffb59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -937,9 +937,9 @@ static const struct vga_switcheroo_client_ops 
amdgpu_switcheroo_ops = {
.can_

[PATCH 05/16] drm/amdgpu: rename amdgpu_wb_* functions

[Alex Deucher]

add device for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  8 
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c|  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 16 
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 10 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +-
 drivers/gpu/drm/amd/amdgpu/si_dma.c| 10 +-
 10 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fa39eb146d46..e5b49900ff15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1171,8 +1171,8 @@ struct amdgpu_wb {
unsigned long   used[DIV_ROUND_UP(AMDGPU_MAX_WB, 
BITS_PER_LONG)];
 };
 
-int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
-void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
+int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
+void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
 
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2111a5864c61..c4c7d2daaa60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -530,7 +530,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_wb_get - Allocate a wb entry
+ * amdgpu_device_wb_get - Allocate a wb entry
  *
  * @adev: amdgpu_device pointer
  * @wb: wb index
@@ -538,7 +538,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev)
  * Allocate a wb slot for use by the driver (all asics).
  * Returns 0 on success or -EINVAL on failure.
  */
-int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
+int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 {
unsigned long offset = find_first_zero_bit(adev->wb.used, 
adev->wb.num_wb);
 
@@ -552,14 +552,14 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 }
 
 /**
- * amdgpu_wb_free - Free a wb entry
+ * amdgpu_device_wb_free - Free a wb entry
  *
  * @adev: amdgpu_device pointer
  * @wb: wb index
  *
  * Free a wb slot allocated for use by the driver (all asics)
  */
-void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
+void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 {
if (wb < adev->wb.num_wb)
__clear_bit(wb >> 3, adev->wb.used);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ef043361009f..bb40d2529a30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -203,7 +203,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 
spin_lock_init(>ring_lock);
 
-   r = amdgpu_wb_get(adev, >virt.reg_val_offs);
+   r = amdgpu_device_wb_get(adev, >virt.reg_val_offs);
if (r)
return r;
 
@@ -229,7 +229,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
  struct amdgpu_irq_src *irq)
 {
-   amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
+   amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
amdgpu_ring_fini(ring);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index f5f27e4f0f7f..06373d44b3da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -92,15 +92,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, 
unsigned ring_size,
}
return 0;
} else {
-   r = amdgpu_wb_get(adev, >irq.ih.wptr_offs);
+   r = amdgpu_device_wb_get(adev, >irq.ih.wptr_offs);
if (r) {
dev_err(adev->dev, "(%d) ih wptr_offs wb alloc 
failed\n", r);
return r;
}
 
-   r = amdgpu_wb_get(adev, >irq.ih.rptr_offs);
+   r = amdgpu_device_wb_get(adev, >irq.ih.rptr_offs);
if (r) {
-   amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
+   amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
dev_err(adev->dev, "(%d) ih rptr_offs wb alloc 
failed\n", r);
return r;
}
@@ -133,8 +133,8 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
amdgpu_bo_free_kernel(>irq.ih.ring_obj,
  

[PATCH 00/16] clean up amdgpu_device.c

[Alex Deucher]

This file has gotten huge and has become a dumping ground for all
sorts of things.  The function naming is also really inconsistent.
This patch set:
1. cleans up the function naming to make it consistent
2. moves all the debugfs stuff to it's own file
3. moves all the atom stuff to amdgpu_atombios.c
4. moves a bunch of helper functions local to where they are used

Alex Deucher (16):
  drm/amdgpu: move atom functions from amdgpu_device.c
  drm/amdgpu: use consistent naming for static funcs in amdgpu_device.c
  drm/amdgpu: rename amdgpu_suspend to amdgpu_device_ip_suspend
  drm/amdgpu: move debugfs functions to their own file
  drm/amdgpu: rename amdgpu_wb_* functions
  drm/amdgpu: rename amdgpu_program_register_sequence
  drm/amdgpu: rename amdgpu_pci_config_reset
  drm/amdgpu: move amdgpu_doorbell_get_kfd_info to amdgpu_amdkfd.c
  drm/amdgpu: rename amdgpu_*_location functions
  drm/amdgpu: move fw_reserve functions to amdgpu_ttm.c
  drm/amdgpu: rename ip block helper functions
  drm/amdgpu: rename amdgpu_need_post
  drm/amdgpu: move dummy page functions to amdgpu_gart.c
  drm/amdgpu: rename amdgpu_gpu_recover
  drm/amdgpu: move amdgpu_need_backup to amdgpu_object.c
  drm/amdgpu: rename amdgpu_get_pcie_info

 drivers/gpu/drm/amd/amdgpu/Makefile  |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   90 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c  |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c   |   33 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c |  236 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c  |  792 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h  |   42 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 1458 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c|2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c |   49 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c  |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c  |4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c   |   10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c  |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c  |2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c   |8 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c   |   18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c |   16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |   99 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |   18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |   16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |2 +-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c  |8 +-
 drivers/gpu/drm/amd/amdgpu/cik.c |  212 ++--
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c|   10 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c   |   24 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c   |   30 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c|  132 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c|4 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c|   16 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c|   58 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c|   10 +-
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c  |8 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c|2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c|   50 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   |   22 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   |   70 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |   10 +-
 drivers/gpu/drm/amd/amdgpu/si.c  |  156 +--
 drivers/gpu/drm/amd/amdgpu/si_dma.c  |   10 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c   |   48 +-
 drivers/gpu/drm/amd/amdgpu/vi.c  |  166 +--
 45 files changed, 2008 insertions(+), 1949 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h

-- 
2.13.6

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[PATCH 10/16] drm/amdgpu: move fw_reserve functions to amdgpu_ttm.c

[Alex Deucher]

It's the only place they are used.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  3 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 95 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 99 +-
 3 files changed, 97 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c779f4b40280..96bbd143efdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1390,9 +1390,6 @@ struct amdgpu_fw_vram_usage {
void *va;
 };
 
-int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
-void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev);
-
 /*
  * CGS
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 31436296fc13..df800f268a20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -597,101 +597,6 @@ void amdgpu_device_gart_location(struct amdgpu_device 
*adev,
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 }
 
-/*
- * Firmware Reservation functions
- */
-/**
- * amdgpu_fw_reserve_vram_fini - free fw reserved vram
- *
- * @adev: amdgpu_device pointer
- *
- * free fw reserved vram if it has been reserved.
- */
-void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
-{
-   amdgpu_bo_free_kernel(>fw_vram_usage.reserved_bo,
-   NULL, >fw_vram_usage.va);
-}
-
-/**
- * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
- *
- * @adev: amdgpu_device pointer
- *
- * create bo vram reservation from fw.
- */
-int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
-{
-   struct ttm_operation_ctx ctx = { false, false };
-   int r = 0;
-   int i;
-   u64 vram_size = adev->mc.visible_vram_size;
-   u64 offset = adev->fw_vram_usage.start_offset;
-   u64 size = adev->fw_vram_usage.size;
-   struct amdgpu_bo *bo;
-
-   adev->fw_vram_usage.va = NULL;
-   adev->fw_vram_usage.reserved_bo = NULL;
-
-   if (adev->fw_vram_usage.size > 0 &&
-   adev->fw_vram_usage.size <= vram_size) {
-
-   r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
-   PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
-   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
-   >fw_vram_usage.reserved_bo);
-   if (r)
-   goto error_create;
-
-   r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
-   if (r)
-   goto error_reserve;
-
-   /* remove the original mem node and create a new one at the
-* request position
-*/
-   bo = adev->fw_vram_usage.reserved_bo;
-   offset = ALIGN(offset, PAGE_SIZE);
-   for (i = 0; i < bo->placement.num_placement; ++i) {
-   bo->placements[i].fpfn = offset >> PAGE_SHIFT;
-   bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
-   }
-
-   ttm_bo_mem_put(>tbo, >tbo.mem);
-   r = ttm_bo_mem_space(>tbo, >placement,
->tbo.mem, );
-   if (r)
-   goto error_pin;
-
-   r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
-   AMDGPU_GEM_DOMAIN_VRAM,
-   adev->fw_vram_usage.start_offset,
-   (adev->fw_vram_usage.start_offset +
-   adev->fw_vram_usage.size), NULL);
-   if (r)
-   goto error_pin;
-   r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
-   >fw_vram_usage.va);
-   if (r)
-   goto error_kmap;
-
-   amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
-   }
-   return r;
-
-error_kmap:
-   amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
-error_pin:
-   amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
-error_reserve:
-   amdgpu_bo_unref(>fw_vram_usage.reserved_bo);
-error_create:
-   adev->fw_vram_usage.va = NULL;
-   adev->fw_vram_usage.reserved_bo = NULL;
-   return r;
-}
-
 /**
  * amdgpu_device_resize_fb_bar - try to resize FB BAR
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c307a7d2cf16..5b5554cba35f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1269,6 +1269,101 @@ static struct ttm_bo_driver amdgpu_bo_driver = {

[PATCH 03/16] drm/amdgpu: rename amdgpu_suspend to amdgpu_device_ip_suspend

[Alex Deucher]

for consistency with the other functions in that file.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 406038bab554..07980146869a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1964,7 +1964,7 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev);
 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 struct drm_file *file_priv);
-int amdgpu_suspend(struct amdgpu_device *adev);
+int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4b4ccf3456fe..a18a267b32cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1690,7 +1690,7 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
amdgpu_device_ip_late_set_cg_state(adev);
 }
 
-int amdgpu_suspend(struct amdgpu_device *adev)
+int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
 {
int i, r;
 
@@ -2344,7 +2344,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
 
amdgpu_fence_driver_suspend(adev);
 
-   r = amdgpu_suspend(adev);
+   r = amdgpu_device_ip_suspend(adev);
 
/* evict remaining vram memory
 * This second call to evict vram is to evict the gart page table
@@ -2670,7 +2670,7 @@ static int amdgpu_device_reset(struct amdgpu_device *adev,
}
 
if (need_full_reset) {
-   r = amdgpu_suspend(adev);
+   r = amdgpu_device_ip_suspend(adev);
 
 retry:
r = amdgpu_asic_reset(adev);
@@ -2709,7 +2709,7 @@ static int amdgpu_device_reset(struct amdgpu_device *adev,
r = amdgpu_ib_ring_tests(adev);
if (r) {
dev_err(adev->dev, "ib ring test failed (%d).\n", r);
-   r = amdgpu_suspend(adev);
+   r = amdgpu_device_ip_suspend(adev);
need_full_reset = true;
goto retry;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1fc5499cb5fd..50afcf65181a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -649,7 +649,7 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
 * unfortunately we can't detect certain
 * hypervisors so just do this all the time.
 */
-   amdgpu_suspend(adev);
+   amdgpu_device_ip_suspend(adev);
 }
 
 static int amdgpu_pmops_suspend(struct device *dev)
-- 
2.13.6

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[PATCH 13/16] drm/amdgpu: move dummy page functions to amdgpu_gart.c

[Alex Deucher]

It's the only place they are used.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  3 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   | 49 --
 3 files changed, 47 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d67e3c853301..5837298fb701 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -377,9 +377,6 @@ struct amdgpu_dummy_page {
struct page *page;
dma_addr_t  addr;
 };
-int amdgpu_dummy_page_init(struct amdgpu_device *adev);
-void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
-
 
 /*
  * Clocks
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 89ac4cdbe3fc..745076b69648 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -724,51 +724,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
return true;
 }
 
-/**
- * amdgpu_dummy_page_init - init dummy page used by the driver
- *
- * @adev: amdgpu_device pointer
- *
- * Allocate the dummy page used by the driver (all asics).
- * This dummy page is used by the driver as a filler for gart entries
- * when pages are taken out of the GART
- * Returns 0 on sucess, -ENOMEM on failure.
- */
-int amdgpu_dummy_page_init(struct amdgpu_device *adev)
-{
-   if (adev->dummy_page.page)
-   return 0;
-   adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
-   if (adev->dummy_page.page == NULL)
-   return -ENOMEM;
-   adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
-   0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-   if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
-   dev_err(>pdev->dev, "Failed to DMA MAP the dummy page\n");
-   __free_page(adev->dummy_page.page);
-   adev->dummy_page.page = NULL;
-   return -ENOMEM;
-   }
-   return 0;
-}
-
-/**
- * amdgpu_dummy_page_fini - free dummy page used by the driver
- *
- * @adev: amdgpu_device pointer
- *
- * Frees the dummy page used by the driver (all asics).
- */
-void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
-{
-   if (adev->dummy_page.page == NULL)
-   return;
-   pci_unmap_page(adev->pdev, adev->dummy_page.addr,
-   PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-   __free_page(adev->dummy_page.page);
-   adev->dummy_page.page = NULL;
-}
-
 /* if we get transitioned to only one device, take VGA back */
 /**
  * amdgpu_device_vga_set_decode - enable/disable vga decode
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 1f51897acc5b..0a4f34af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -57,6 +57,51 @@
  */
 
 /**
+ * amdgpu_dummy_page_init - init dummy page used by the driver
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Allocate the dummy page used by the driver (all asics).
+ * This dummy page is used by the driver as a filler for gart entries
+ * when pages are taken out of the GART
+ * Returns 0 on sucess, -ENOMEM on failure.
+ */
+static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
+{
+   if (adev->dummy_page.page)
+   return 0;
+   adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
+   if (adev->dummy_page.page == NULL)
+   return -ENOMEM;
+   adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
+   0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+   if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
+   dev_err(>pdev->dev, "Failed to DMA MAP the dummy page\n");
+   __free_page(adev->dummy_page.page);
+   adev->dummy_page.page = NULL;
+   return -ENOMEM;
+   }
+   return 0;
+}
+
+/**
+ * amdgpu_dummy_page_fini - free dummy page used by the driver
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Frees the dummy page used by the driver (all asics).
+ */
+static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
+{
+   if (adev->dummy_page.page == NULL)
+   return;
+   pci_unmap_page(adev->pdev, adev->dummy_page.addr,
+   PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+   __free_page(adev->dummy_page.page);
+   adev->dummy_page.page = NULL;
+}
+
+/**
  * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
  *
  * @adev: amdgpu_device pointer
@@ -308,7 

[PATCH 08/16] drm/amdgpu: move amdgpu_doorbell_get_kfd_info to amdgpu_amdkfd.c

[Alex Deucher]

It's the only place it's used.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 33 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +-
 3 files changed, 34 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9b595d74ea8c..b363dbf304ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -651,12 +651,6 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_INVALID = 0x
 } AMDGPU_DOORBELL64_ASSIGNMENT;
 
-
-void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
-   phys_addr_t *aperture_base,
-   size_t *aperture_size,
-   size_t *start_offset);
-
 /*
  * IRQS.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index c70cda04dbfb..896b16db58aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -93,6 +93,39 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
   adev->pdev, kfd2kgd);
 }
 
+/**
+ * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
+ *setup amdkfd
+ *
+ * @adev: amdgpu_device pointer
+ * @aperture_base: output returning doorbell aperture base physical address
+ * @aperture_size: output returning doorbell aperture size in bytes
+ * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
+ *
+ * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
+ * takes doorbells required for its own rings and reports the setup to amdkfd.
+ * amdgpu reserved doorbells are at the start of the doorbell aperture.
+ */
+static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
+phys_addr_t *aperture_base,
+size_t *aperture_size,
+size_t *start_offset)
+{
+   /*
+* The first num_doorbells are used by amdgpu.
+* amdkfd takes whatever's left in the aperture.
+*/
+   if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
+   *aperture_base = adev->doorbell.base;
+   *aperture_size = adev->doorbell.size;
+   *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
+   } else {
+   *aperture_base = 0;
+   *aperture_size = 0;
+   *start_offset = 0;
+   }
+}
+
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 {
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b93308e2353c..a7370458acca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -438,38 +438,7 @@ static void amdgpu_device_doorbell_fini(struct 
amdgpu_device *adev)
adev->doorbell.ptr = NULL;
 }
 
-/**
- * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
- *setup amdkfd
- *
- * @adev: amdgpu_device pointer
- * @aperture_base: output returning doorbell aperture base physical address
- * @aperture_size: output returning doorbell aperture size in bytes
- * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
- *
- * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
- * takes doorbells required for its own rings and reports the setup to amdkfd.
- * amdgpu reserved doorbells are at the start of the doorbell aperture.
- */
-void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
-   phys_addr_t *aperture_base,
-   size_t *aperture_size,
-   size_t *start_offset)
-{
-   /*
-* The first num_doorbells are used by amdgpu.
-* amdkfd takes whatever's left in the aperture.
-*/
-   if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
-   *aperture_base = adev->doorbell.base;
-   *aperture_size = adev->doorbell.size;
-   *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
-   } else {
-   *aperture_base = 0;
-   *aperture_size = 0;
-   *start_offset = 0;
-   }
-}
+
 
 /*
  * amdgpu_device_wb_*()
-- 
2.13.6

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[PATCH 12/16] drm/amdgpu: rename amdgpu_need_post

[Alex Deucher]

add device to the name for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 30c9c82e7029..d67e3c853301 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1896,7 +1896,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, 
bool force);
 bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
-bool amdgpu_need_post(struct amdgpu_device *adev);
+bool amdgpu_device_need_post(struct amdgpu_device *adev);
 void amdgpu_update_display_priority(struct amdgpu_device *adev);
 
 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 057e1ecd83ce..a5df80d50d44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -93,7 +93,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device 
*adev)
resource_size_t size = 256 * 1024; /* ??? */
 
if (!(adev->flags & AMD_IS_APU))
-   if (amdgpu_need_post(adev))
+   if (amdgpu_device_need_post(adev))
return false;
 
adev->bios = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 91741eeffb59..89ac4cdbe3fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -671,7 +671,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
  * GPU helpers function.
  */
 /**
- * amdgpu_need_post - check if the hw need post or not
+ * amdgpu_device_need_post - check if the hw need post or not
  *
  * @adev: amdgpu_device pointer
  *
@@ -679,7 +679,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
  * or post is needed if  hw reset is performed.
  * Returns true if need or false if not.
  */
-bool amdgpu_need_post(struct amdgpu_device *adev)
+bool amdgpu_device_need_post(struct amdgpu_device *adev)
 {
uint32_t reg;
 
@@ -1946,7 +1946,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_device_detect_sriov_bios(adev);
 
/* Post card if necessary */
-   if (amdgpu_need_post(adev)) {
+   if (amdgpu_device_need_post(adev)) {
if (!adev->bios) {
dev_err(adev->dev, "no vBIOS found\n");
r = -EINVAL;
@@ -2275,7 +2275,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
}
 
/* post card */
-   if (amdgpu_need_post(adev)) {
+   if (amdgpu_device_need_post(adev)) {
r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
if (r)
DRM_ERROR("amdgpu asic init failed\n");
-- 
2.13.6

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[PATCH 06/16] drm/amdgpu: rename amdgpu_program_register_sequence

[Alex Deucher]

add device for consistency with other functions in this file.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   8 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   | 120 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c |  24 +++---
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c |  30 
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 114 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  12 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  54 ++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |   6 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c  |  48 ++--
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  12 +--
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  60 +++
 drivers/gpu/drm/amd/amdgpu/si.c| 102 
 drivers/gpu/drm/amd/amdgpu/vi.c|  30 
 14 files changed, 311 insertions(+), 311 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e5b49900ff15..ba57d0d6744f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1916,7 +1916,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device 
*adev);
 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
 int amdgpu_ttm_init(struct amdgpu_device *adev);
 void amdgpu_ttm_fini(struct amdgpu_device *adev);
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 const u32 *registers,
 const u32 array_size);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c4c7d2daaa60..2a4c49875abe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct 
amdgpu_device *adev)
 }
 
 /**
- * amdgpu_program_register_sequence - program an array of registers.
+ * amdgpu_device_program_register_sequence - program an array of registers.
  *
  * @adev: amdgpu_device pointer
  * @registers: pointer to the register array
@@ -351,9 +351,9 @@ static void amdgpu_device_vram_scratch_fini(struct 
amdgpu_device *adev)
  * Programs an array or registers with and and or masks.
  * This is a helper for setting golden registers.
  */
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
- const u32 *registers,
- const u32 array_size)
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+const u32 *registers,
+const u32 array_size)
 {
u32 tmp, reg, and_mask, or_mask;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 8ba056a2a5da..39d49712f8c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct 
amdgpu_device *adev)
 
switch (adev->asic_type) {
case CHIP_BONAIRE:
-   amdgpu_program_register_sequence(adev,
-bonaire_mgcg_cgcg_init,
-
ARRAY_SIZE(bonaire_mgcg_cgcg_init));
-   amdgpu_program_register_sequence(adev,
-bonaire_golden_registers,
-
ARRAY_SIZE(bonaire_golden_registers));
-   amdgpu_program_register_sequence(adev,
-
bonaire_golden_common_registers,
-
ARRAY_SIZE(bonaire_golden_common_registers));
-   amdgpu_program_register_sequence(adev,
-bonaire_golden_spm_registers,
-
ARRAY_SIZE(bonaire_golden_spm_registers));
+   amdgpu_device_program_register_sequence(adev,
+   bonaire_mgcg_cgcg_init,
+   
ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+   amdgpu_device_program_register_sequence(adev,
+   
bonaire_golden_registers,
+   
ARRAY_SIZE(bonaire_golden_registers));
+   amdgpu_device_program_register_sequence(adev,
+   
bonaire_golden_common_registers,
+   
A

[PATCH 14/16] drm/amdgpu: rename amdgpu_gpu_recover

[Alex Deucher]

add device to the name for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c  | 2 +-
 7 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5837298fb701..4e9e5b4b1927 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1890,7 +1890,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_psp_check_fw_loading_status(adev, i) 
(adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 
 /* Common functions */
-int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, 
bool force);
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ struct amdgpu_job* job, bool force);
 bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
 bool amdgpu_device_need_post(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 745076b69648..8863616c5c4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2612,7 +2612,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
 }
 
 /**
- * amdgpu_gpu_recover - reset the asic and recover scheduler
+ * amdgpu_device_gpu_recover - reset the asic and recover scheduler
  *
  * @adev: amdgpu device pointer
  * @job: which job trigger hang
@@ -2621,7 +2621,8 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
  * Attempt to reset the GPU if it has hung (all asics).
  * Returns 0 for success or an error on failure.
  */
-int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, 
bool force)
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ struct amdgpu_job *job, bool force)
 {
struct drm_atomic_state *state = NULL;
uint64_t reset_flags = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index da1510f65ee0..008e1984b7e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -693,7 +693,7 @@ static int amdgpu_debugfs_gpu_recover(struct seq_file *m, 
void *data)
struct amdgpu_device *adev = dev->dev_private;
 
seq_printf(m, "gpu recover\n");
-   amdgpu_gpu_recover(adev, NULL, true);
+   amdgpu_device_gpu_recover(adev, NULL, true);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index c43643e8c8c8..56bcd59c3399 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -88,7 +88,7 @@ static void amdgpu_irq_reset_work_func(struct work_struct 
*work)
  reset_work);
 
if (!amdgpu_sriov_vf(adev))
-   amdgpu_gpu_recover(adev, NULL, false);
+   amdgpu_device_gpu_recover(adev, NULL, false);
 }
 
 /* Disable *all* interrupts */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index be8a437fad54..56d9ee5013a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -37,7 +37,7 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
  atomic_read(>ring->fence_drv.last_seq),
  job->ring->fence_drv.sync_seq);
 
-   amdgpu_gpu_recover(job->adev, job, false);
+   amdgpu_device_gpu_recover(job->adev, job, false);
 }
 
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 43e74ec93147..271452d3999a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -253,7 +253,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct 
*work)
}
 
/* Trigger recovery due to world switch failure */
-   amdgpu_gpu_recover(adev, NULL, false);
+   amdgpu_device_gpu_recover(adev, NULL, false);
 }
 
 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index af2d47e9abdc..9fc1c37344ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -521,7 +521,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct 
*work)
}
 

[PATCH 09/16] drm/amdgpu: rename amdgpu_*_location functions

[Alex Deucher]

add device to the name for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 ++--
 6 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b363dbf304ef..c779f4b40280 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1904,8 +1904,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device 
*adev, u64 num_bytes,
  u64 num_vis_bytes);
 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
-void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, 
u64 base);
-void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
+void amdgpu_device_vram_location(struct amdgpu_device *adev,
+struct amdgpu_mc *mc, u64 base);
+void amdgpu_device_gart_location(struct amdgpu_device *adev,
+struct amdgpu_mc *mc);
 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
 int amdgpu_ttm_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a7370458acca..31436296fc13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -535,7 +535,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 
wb)
 }
 
 /**
- * amdgpu_vram_location - try to find VRAM location
+ * amdgpu_device_vram_location - try to find VRAM location
  * @adev: amdgpu device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
  * @base: base address at which to put VRAM
@@ -543,7 +543,8 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 
wb)
  * Function will try to place VRAM at base address provided
  * as parameter.
  */
-void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, 
u64 base)
+void amdgpu_device_vram_location(struct amdgpu_device *adev,
+struct amdgpu_mc *mc, u64 base)
 {
uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 
@@ -557,7 +558,7 @@ void amdgpu_vram_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc, u64
 }
 
 /**
- * amdgpu_gart_location - try to find GTT location
+ * amdgpu_device_gart_location - try to find GTT location
  * @adev: amdgpu device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
  *
@@ -568,7 +569,8 @@ void amdgpu_vram_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc, u64
  *
  * FIXME: when reducing GTT size align new size on power of 2.
  */
-void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
+void amdgpu_device_gart_location(struct amdgpu_device *adev,
+struct amdgpu_mc *mc)
 {
u64 size_af, size_bf;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 279f43a2b1a4..e1a73c43f32d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -222,8 +222,8 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device 
*adev,
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
base <<= 24;
 
-   amdgpu_vram_location(adev, >mc, base);
-   amdgpu_gart_location(adev, mc);
+   amdgpu_device_vram_location(adev, >mc, base);
+   amdgpu_device_gart_location(adev, mc);
 }
 
 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index c4285395b5fe..356a9a71b8cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -240,8 +240,8 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device 
*adev,
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
base <<= 24;
 
-   amdgpu_vram_location(adev, >mc, base);
-   amdgpu_gart_location(adev, mc);
+   amdgpu_device_vram_location(adev, >mc, base);
+   amdgpu_device_gart_location(adev, mc);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 6641276ecbdf..fce45578f5fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -405,8 +405,8 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_

[PATCH 04/16] drm/amdgpu: move debugfs functions to their own file

[Alex Deucher]

amdgpu_device.c was getting pretty cluttered.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/Makefile |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 792 
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h |  42 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 769 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |   2 +-
 6 files changed, 838 insertions(+), 785 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index f778a3b4abe6..d8da12c114b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -52,7 +52,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
-   amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o
+   amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 07980146869a..fa39eb146d46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -71,7 +71,7 @@
 #include "amdgpu_dm.h"
 #include "amdgpu_virt.h"
 #include "amdgpu_gart.h"
-
+#include "amdgpu_debugfs.h"
 
 /*
  * Modules parameters.
@@ -425,7 +425,6 @@ struct reservation_object *amdgpu_gem_prime_res_obj(struct 
drm_gem_object *);
 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct 
*vma);
-int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
 
 /* sub-allocation manager, it has to be protected by another lock.
  * By conception this is an helper for other part of the driver
@@ -1240,19 +1239,6 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int 
test_number);
  */
 void amdgpu_test_moves(struct amdgpu_device *adev);
 
-/*
- * Debugfs
- */
-struct amdgpu_debugfs {
-   const struct drm_info_list  *files;
-   unsignednum_files;
-};
-
-int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
-const struct drm_info_list *files,
-unsigned nfiles);
-int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
-int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
 
 /*
  * amdgpu smumgr functions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
new file mode 100644
index ..ee76b468774a
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -0,0 +1,792 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include "amdgpu.h"
+
+/*
+ * Debugfs
+ */
+int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
+const struct drm_info_list *files,
+unsigned nfiles)
+{
+   unsigned i;
+
+   for (i = 0; i < adev->debugfs_count; i++) {
+   if (adev->debugfs[i].files == files) {
+   /* Already registered */
+   return 0;
+   }
+   }
+
+   i = adev->debugfs_count + 1;
+   if (i > AMDGPU_DEBUGFS_M

[PATCH 16/16] drm/amdgpu: rename amdgpu_get_pcie_info

[Alex Deucher]

add device to the name for consistency.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c| 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bb12d68c21d8..05992a201cdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1167,7 +1167,7 @@ struct amdgpu_wb {
 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
 
-void amdgpu_get_pcie_info(struct amdgpu_device *adev);
+void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 
 /*
  * SDMA
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6961bf208660..e91575311646 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2750,7 +2750,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
return r;
 }
 
-void amdgpu_get_pcie_info(struct amdgpu_device *adev)
+void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
 {
u32 mask;
int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6a92abc736e0..8e59e65efd44 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1866,7 +1866,7 @@ static int cik_common_early_init(void *handle)
 
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, 
amdgpu_fw_load_type);
 
-   amdgpu_get_pcie_info(adev);
+   amdgpu_device_get_pcie_info(adev);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f0fb4161e866..8f2cff7b7e0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -682,7 +682,7 @@ static int soc15_common_early_init(void *handle)
 
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, 
amdgpu_fw_load_type);
 
-   amdgpu_get_pcie_info(adev);
+   amdgpu_device_get_pcie_info(adev);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 66072063bc7c..d9bb26322850 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1074,7 +1074,7 @@ static int vi_common_early_init(void *handle)
/* vi use smc load by default */
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, 
amdgpu_fw_load_type);
 
-   amdgpu_get_pcie_info(adev);
+   amdgpu_device_get_pcie_info(adev);
 
return 0;
 }
-- 
2.13.6

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[pull] amdgpu drm-fixes-4.15

[Alex Deucher]

Hi Dave,

I forgot to include the DC fixes from Harry when I sent out
my fixes yesterday.  This just adds them on top.

The following changes since commit 0507f438ea19d4280006467ba02956f6a693deca:

  drm/amdgpu: fix MAP_QUEUES paramter (2017-12-12 15:40:11 -0500)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.15

for you to fetch changes up to becd0875f4393a992afbf57aa323f7bf1a71c3ff:

  drm/amd/display: Fix rehook MST display not light back on (2017-12-15 
17:32:42 -0500)


Bhawanpreet Lakha (1):
  drm/amd/display: add pipe locking before front end programing

Dmytro Laktyushkin (1):
  drm/amd/display: set chroma taps to 1 when not scaling

Eric Yang (1):
  drm/amd/display: fix missing pixel clock adjustment for dongle

Jerry (Fangzhi) Zuo (1):
  drm/amd/display: Fix rehook MST display not light back on

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 13 +++---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  2 +
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 51 ++
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h|  1 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  9 
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  4 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 26 ---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |  9 ++--
 8 files changed, 99 insertions(+), 16 deletions(-)
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Re: [PATCH] drm/amd/pp: need to notify umd the pstate clock.

[Alex Deucher]

On Wed, Dec 13, 2017 at 4:52 AM, Rex Zhu  wrote:
> Change-Id: I344731cc6398c40976e08a125808bbfa85cb59a3
> Signed-off-by: Rex Zhu 

Please include a better patch description.  Something like:
Flag the stable pstate clocks in sysfs so userspace knows what clocks
are in use when stable pstate is selected for profiling.

We also probably need to handles APUs.

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 43 
> +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 36 ++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 +
>  3 files changed, 56 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 8edb0c4..ecf9449 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2590,8 +2590,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
> *hwmgr, enum amd_dpm_forced_le
> break;
> }
> }
> -   if (count < 0 || level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> +   if (count < 0 || level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> *sclk_mask = 0;
> +   tmp_sclk = 
> table_info->vdd_dep_on_sclk->entries[0].clk;
> +   }
>
> if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
> @@ -2603,6 +2605,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr 
> *hwmgr, enum amd_dpm_forced_le
> *mclk_mask = golden_dpm_table->mclk_table.count - 1;
>
> *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
> +
> +   hwmgr->pstate_sclk = tmp_sclk;
> +   hwmgr->pstate_mclk = tmp_mclk;
> +
> return 0;
>  }
>
> @@ -2614,6 +2620,10 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
> uint32_t mclk_mask = 0;
> uint32_t pcie_mask = 0;
>
> +   ret = smu7_get_profiling_clk(hwmgr, level, _mask, _mask, 
> _mask);
> +   if (ret)
> +   return ret;
> +
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> ret = smu7_force_dpm_highest(hwmgr);
> @@ -2628,9 +2638,6 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> -   ret = smu7_get_profiling_clk(hwmgr, level, _mask, 
> _mask, _mask);
> -   if (ret)
> -   return ret;
> smu7_force_clock_level(hwmgr, PP_SCLK, 1< smu7_force_clock_level(hwmgr, PP_MCLK, 1< smu7_force_clock_level(hwmgr, PP_PCIE, 1< @@ -4292,7 +4299,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> struct smu7_single_dpm_table *sclk_table = 
> &(data->dpm_table.sclk_table);
> struct smu7_single_dpm_table *mclk_table = 
> &(data->dpm_table.mclk_table);
> struct smu7_single_dpm_table *pcie_table = 
> &(data->dpm_table.pcie_speed_table);
> -   int i, now, size = 0;
> +   int i, now, p, size = 0;
> uint32_t clock, pcie_speed;
>
> switch (type) {
> @@ -4301,32 +4308,34 @@ static int smu7_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
>
> for (i = 0; i < sclk_table->count; i++) {
> -   if (clock > sclk_table->dpm_levels[i].value)
> -   continue;
> -   break;
> +   if (hwmgr->pstate_sclk == 
> sclk_table->dpm_levels[i].value)
> +   p = i;
> +   if (clock <= sclk_table->dpm_levels[i].value)
> +   now = i;
> }
> -   now = i;
>
> for (i = 0; i < sclk_table->count; i++)
> -   size += sprintf(buf + size, "%d: %uMhz %s\n",
> +   size += sprintf(buf + size, "%d: %uMhz %s %s\n",
> i, sclk_table->dpm_levels[i].value / 
> 100,
> -   (i == now) ? "*" : "");
> +   (i == now) ? "*" : "",
> +   (i == p) ? "P" : "");
> break;
> case PP_MCLK:
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
> clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
>
> for (i = 0; i < mclk_table->count; i++) {
> -   if (clock > mclk_table->dpm_levels[i].value)
> - 

Re: [PATCH] drm/amdgpu: Add gpu_recovery parameter

[Alex Deucher]

On Tue, Dec 12, 2017 at 2:16 PM, Andrey Grodzovsky
 wrote:
> Add new parameter to control GPU recovery procedure.
> Retire old way of disabling GPU recovery by setting lockup_timeout == 0 and
> set default for lockup_timeout to 10s.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 8 ++--
>  3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3735500..26abe03 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -126,6 +126,7 @@ extern int amdgpu_param_buf_per_se;
>  extern int amdgpu_job_hang_limit;
>  extern int amdgpu_lbpw;
>  extern int amdgpu_compute_multipipe;
> +extern int amdgpu_gpu_recovery;
>
>  #ifdef CONFIG_DRM_AMDGPU_SI
>  extern int amdgpu_si_support;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 8d03baa..d84b57a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3030,6 +3030,11 @@ int amdgpu_gpu_recover(struct amdgpu_device *adev, 
> struct amdgpu_job *job)
> return 0;
> }
>
> +   if (!amdgpu_gpu_recovery) {
> +   DRM_INFO("GPU recovery disabled.\n");
> +   return 0;
> +   }


Probably need and else here for the -1 (auto) case so we can disable
by default for non-SR-IOV and always keep it enabled for SR-IOV.


> +
> dev_info(adev->dev, "GPU reset begin!\n");
>
> mutex_lock(>lock_reset);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 0b039bd..5c612e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -90,7 +90,7 @@ int amdgpu_disp_priority = 0;
>  int amdgpu_hw_i2c = 0;
>  int amdgpu_pcie_gen2 = -1;
>  int amdgpu_msi = -1;
> -int amdgpu_lockup_timeout = 0;
> +int amdgpu_lockup_timeout = 1;
>  int amdgpu_dpm = -1;
>  int amdgpu_fw_load_type = -1;
>  int amdgpu_aspm = -1;
> @@ -128,6 +128,7 @@ int amdgpu_param_buf_per_se = 0;
>  int amdgpu_job_hang_limit = 0;
>  int amdgpu_lbpw = -1;
>  int amdgpu_compute_multipipe = -1;
> +int amdgpu_gpu_recovery = 1;
>
>  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
>  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
> @@ -165,7 +166,7 @@ module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 
> 0444);
>  MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
>  module_param_named(msi, amdgpu_msi, int, 0444);
>
> -MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = 
> disable)");
> +MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 1)");

Make this a separate change.

>  module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
>
>  MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
> @@ -280,6 +281,9 @@ module_param_named(lbpw, amdgpu_lbpw, int, 0444);
>  MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread 
> across pipes (1 = enable, 0 = disable, -1 = auto)");
>  module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
>
> +MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable 
> (default) , 0 = disable");
> +module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
> +

set the default to -1 so we can have different default behavior in
different cases, e.g., different asics or environments (like SR-IOV).

Alex

>  #ifdef CONFIG_DRM_AMDGPU_SI
>
>  #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
> --
> 2.7.4
>
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[PATCH 1/3] drm/amdgpu: drop scratch regs save and restore from S3/S4 handling

[Alex Deucher]

The expectation is that the base driver doesn't mess with these.
Some components interact with these directly so let the components
handle these directly.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 98d62a991b67..ca1cf8a71dda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2577,7 +2577,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
 */
amdgpu_bo_evict_vram(adev);
 
-   amdgpu_atombios_scratch_regs_save(adev);
pci_save_state(dev->pdev);
if (suspend) {
/* Shut down the device */
@@ -2626,7 +2625,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
if (r)
goto unlock;
}
-   amdgpu_atombios_scratch_regs_restore(adev);
 
/* post card */
if (amdgpu_need_post(adev)) {
-- 
2.13.6

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[PATCH 3/3] drm/amdgpu: drop amdgpu_atombios_scratch_regs_save/restore

[Alex Deucher]

No longer used.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 22 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |  2 --
 2 files changed, 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 39f4d0df1ada..ffaf0534e33c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1721,28 +1721,6 @@ void amdgpu_atombios_scratch_regs_init(struct 
amdgpu_device *adev)
WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
 }
 
-void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
-{
-   int i;
-
-   for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
-   adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + 
i);
-}
-
-void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
-{
-   int i;
-
-   /*
-* VBIOS will check ASIC_INIT_COMPLETE bit to decide if
-* execute ASIC_Init posting via driver
-*/
-   adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;
-
-   for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
-   WREG32(adev->bios_scratch_reg_offset + i, 
adev->bios_scratch[i]);
-}
-
 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
  bool hung)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
index b0d5d1d7fdba..58507f9ff856 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
@@ -196,8 +196,6 @@ bool amdgpu_atombios_has_gpu_virtualization_table(struct 
amdgpu_device *adev);
 
 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
-void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
-void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
  bool hung);
 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
-- 
2.13.6

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[PATCH] drm/amdgpu: remove some old gc 9.x registers

[Alex Deucher]

Leftover from bring up.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h   |  8 ++--
 .../drm/amd/include/asic_reg/gc/gc_9_0_default.h   |  7 
 .../drm/amd/include/asic_reg/gc/gc_9_0_offset.h| 14 ---
 .../drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h   | 45 --
 .../drm/amd/include/asic_reg/gc/gc_9_1_offset.h| 14 ---
 5 files changed, 4 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h 
b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
index 003a131bad47..567a904804bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
+++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
@@ -48,7 +48,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
 0x, // DB_STENCIL_WRITE_BASE
 0x, // DB_STENCIL_WRITE_BASE_HI
 0x, // DB_DFSM_CONTROL
-0x, // DB_RENDER_FILTER
+0, // HOLE
 0x, // DB_Z_INFO2
 0x, // DB_STENCIL_INFO2
 0, // HOLE
@@ -259,8 +259,8 @@ static const unsigned int gfx9_SECT_CONTEXT_def_2[] =
 0x, // PA_SC_RIGHT_VERT_GRID
 0x, // PA_SC_LEFT_VERT_GRID
 0x, // PA_SC_HORIZ_GRID
-0x, // PA_SC_FOV_WINDOW_LR
-0x, // PA_SC_FOV_WINDOW_TB
+0, // HOLE
+0, // HOLE
 0, // HOLE
 0, // HOLE
 0, // HOLE
@@ -701,7 +701,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_7[] =
 {
 0x, // VGT_GS_MAX_PRIMS_PER_SUBGROUP
 0x, // VGT_DRAW_PAYLOAD_CNTL
-0x, // VGT_INDEX_PAYLOAD_CNTL
+0, // HOLE
 0x, // VGT_INSTANCE_STEP_RATE_0
 0x, // VGT_INSTANCE_STEP_RATE_1
 0, // HOLE
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
index 663d3af35baf..5bf84c6d0ec3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
@@ -436,7 +436,6 @@
 #define mmTA_CNTL_DEFAULT  
  0x8004d850
 #define mmTA_CNTL_AUX_DEFAULT  
  0x
 #define mmTA_RESERVED_010C_DEFAULT 
  0x
-#define mmTA_GRAD_ADJ_DEFAULT  
  0x4040
 #define mmTA_STATUS_DEFAULT
  0x
 #define mmTA_SCRATCH_DEFAULT   
  0x
 
@@ -1700,7 +1699,6 @@
 #define mmDB_STENCIL_WRITE_BASE_DEFAULT
  0x
 #define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 
  0x
 #define mmDB_DFSM_CONTROL_DEFAULT  
  0x
-#define mmDB_RENDER_FILTER_DEFAULT 
  0x
 #define mmDB_Z_INFO2_DEFAULT   
  0x
 #define mmDB_STENCIL_INFO2_DEFAULT 
  0x
 #define mmTA_BC_BASE_ADDR_DEFAULT  
  0x
@@ -1806,8 +1804,6 @@
 #define mmPA_SC_RIGHT_VERT_GRID_DEFAULT
  0x
 #define mmPA_SC_LEFT_VERT_GRID_DEFAULT 
  0x
 #define mmPA_SC_HORIZ_GRID_DEFAULT 
  0x
-#define mmPA_SC_FOV_WINDOW_LR_DEFAULT  
  0x
-#define mmPA_SC_FOV_WINDOW_TB_DEFAULT  
  0x
 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 
  0x
 #define mmCB_BLEND_RED_DEFAULT 
  0x
 #define mmCB_BLEND_GREEN_DEFAULT   
  0x
@@ -2072,7 +2068,6 @@
 #define mmVGT_EVENT_INITIATOR_DEFAULT  
  0x
 #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT
  0x
 #define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT
  0x
-#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT   
  0x
 #define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 
  0x
 #define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 
  0x
 #define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT   
  0x
@@ -2490,7 +2485,6 @@
 #define mmWD_INDEX_BUF_BASE_DEFAULT
  0x
 #define mmWD_INDEX_BUF_BASE_HI_DEFAULT 
  0x
 #

Re: [PATCH 2/3] drm/amd/include:cleanup vega10 hdp header files.

[Alex Deucher]

On Thu, Nov 16, 2017 at 3:03 AM, Feifei Xu <feifei...@amd.com> wrote:
> Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h
>
> Change-Id: Ia7cd2e660ceb89a1096c195c6a67677714ccbd69
> Signed-off-by: Feifei Xu <feifei...@amd.com>
> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |   4 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |   2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15.c |   4 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   2 +-
>  .../drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h  | 209 +++
>  .../drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 601 
> +
>  .../include/asic_reg/vega10/HDP/hdp_4_0_default.h  | 117 
>  .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h   | 209 ---
>  .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h  | 601 
> -
>  11 files changed, 818 insertions(+), 935 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h
>  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
>  delete mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
>  delete mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
>  delete mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h

Is there a reason to remove hdp_4_0_default.h?  It's useful if we ever
need to get the default values of the registers.  I think we should
try and keep the register headers consistent.  If we aren't using any
of the default headers, that's fine, we can remove them.

Alex
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Re: [PATCH] drm/amd/pp: fix typecast error in powerplay.

[Alex Deucher]

On Fri, Nov 17, 2017 at 3:59 AM, Rex Zhu <rex@amd.com> wrote:
> resulted in data truncation
>
> Change-Id: I110011ba402a85fade89bb797adcf7318c0f0eb0
> Signed-off-by: Rex Zhu <rex@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> index d1af148..a651ebc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> @@ -830,9 +830,9 @@ static int init_over_drive_limits(
> const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
>  {
> hwmgr->platform_descriptor.overdriveLimit.engineClock =
> -   le16_to_cpu(powerplay_table->ulMaxODEngineClock);
> +   le32_to_cpu(powerplay_table->ulMaxODEngineClock);
> hwmgr->platform_descriptor.overdriveLimit.memoryClock =
> -   le16_to_cpu(powerplay_table->ulMaxODMemoryClock);
> +   le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
>
> hwmgr->platform_descriptor.minOverdriveVDDC = 0;
> hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
> --
> 1.9.1
>
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Re: [PATCH 1/4] drm/amdgpu: always make gart.table_addr 64bit

[Alex Deucher]

On Fri, Nov 17, 2017 at 5:12 AM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Fixing warning/compile errors on 32bit kernels.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index f15e319580ec..5eb1a6800f72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -39,7 +39,7 @@ struct amdgpu_gart_funcs;
>  #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & 
> ~AMDGPU_GPU_PAGE_MASK)
>
>  struct amdgpu_gart {
> -   dma_addr_t  table_addr;
> +   u64 table_addr;
> struct amdgpu_bo*robj;
> void*ptr;
> unsignednum_gpu_pages;
> --
> 2.11.0
>
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Re: [PATCH 3/4] drm/amdgpu: align GTT start to 4GB

[Alex Deucher]

On Fri, Nov 17, 2017 at 5:12 AM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> For VCE to work properly the start of the GTT space must be aligned to a
> 4GB boundary.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index f9bee76e7071..bbaab31218a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -622,7 +622,7 @@ void amdgpu_gart_location(struct amdgpu_device *adev, 
> struct amdgpu_mc *mc)
> dev_warn(adev->dev, "limiting GTT\n");
> mc->gart_size = size_af;
> }
> -   mc->gart_start = mc->vram_end + 1;
> +   mc->gart_start = ALIGN(mc->vram_end + 1, 0x10000ULL);

Please add a comment here as to why we are doing this.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>


> }
> mc->gart_end = mc->gart_start + mc->gart_size - 1;
> dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
> --
> 2.11.0
>
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Re: [PATCH 2/4] drm/amdgpu: remove VRAM size reduction

[Alex Deucher]

On Fri, Nov 17, 2017 at 5:12 AM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Remove some outdated comments and all code which tries to reduce the VRAM size
> mapped into the MC.
>
> This is superfluous and misleading since we never actually program the size.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30 
> +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  6 --
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  6 --

Please also fix up gmc_v6_0.c.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

>  3 files changed, 1 insertion(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 65fba5fb537e..f9bee76e7071 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -578,41 +578,13 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
>   * @base: base address at which to put VRAM
>   *
>   * Function will try to place VRAM at base address provided
> - * as parameter (which is so far either PCI aperture address or
> - * for IGP TOM base address).
> - *
> - * If there is not enough space to fit the unvisible VRAM in the 32bits
> - * address space then we limit the VRAM size to the aperture.
> - *
> - * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
> - * this shouldn't be a problem as we are using the PCI aperture as a 
> reference.
> - * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
> - * not IGP.
> - *
> - * Note: we use mc_vram_size as on some board we need to program the mc to
> - * cover the whole aperture even if VRAM size is inferior to aperture size
> - * Novell bug 204882 + along with lots of ubuntu ones
> - *
> - * Note: when limiting vram it's safe to overwritte real_vram_size because
> - * we are not in case where real_vram_size is inferior to mc_vram_size (ie
> - * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
> - * ones)
> - *
> - * Note: IGP TOM addr should be the same as the aperture addr, we don't
> - * explicitly check for that though.
> - *
> - * FIXME: when reducing VRAM size align new size on power of 2.
> + * as parameter.
>   */
>  void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, 
> u64 base)
>  {
> uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
>
> mc->vram_start = base;
> -   if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
> -   dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
> -   mc->real_vram_size = mc->aper_size;
> -   mc->mc_vram_size = mc->aper_size;
> -   }
> mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
> if (limit && limit < mc->real_vram_size)
> mc->real_vram_size = limit;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index de7a249f0e24..d521862804ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -240,12 +240,6 @@ static void gmc_v7_0_vram_gtt_location(struct 
> amdgpu_device *adev,
> u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
> base <<= 24;
>
> -   if (mc->mc_vram_size > 0xFFC000ULL) {
> -   /* leave room for at least 1024M GTT */
> -   dev_warn(adev->dev, "limiting VRAM\n");
> -   mc->real_vram_size = 0xFFC000ULL;
> -   mc->mc_vram_size = 0xFFC000ULL;
> -   }
> amdgpu_vram_location(adev, >mc, base);
> amdgpu_gart_location(adev, mc);
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 67778744da5a..bd3f842cca00 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -405,12 +405,6 @@ static void gmc_v8_0_vram_gtt_location(struct 
> amdgpu_device *adev,
> base = RREG32(mmMC_VM_FB_LOCATION) & 0x;
> base <<= 24;
>
> -   if (mc->mc_vram_size > 0xFFC000ULL) {
> -   /* leave room for at least 1024M GTT */
> -   dev_warn(adev->dev, "limiting VRAM\n");
> -   mc->real_vram_size = 0xFFC000ULL;
> -   mc->mc_vram_size = 0xFFC000ULL;
> -   }
> amdgpu_vram_location(adev, >mc, base);
> amdgpu_gart_location(adev, mc);
>  }
> --
> 2.11.0
>
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Re: [PATCH 4/4] drm/amdgpu: fix VCE buffer placement restrictions

[Alex Deucher]

On Fri, Nov 17, 2017 at 5:12 AM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Turned out that VCE still has a placement restriction that BOs can't
> cross a 4GB boundary.
>
> Fix this by adding a command submission parser prepass to correctly
> place the buffers.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 90 
> -
>  1 file changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> index 92477e67087c..2843e5b728e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> @@ -543,6 +543,43 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, 
> uint32_t handle,
> return r;
>  }
>
> +static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t 
> ib_idx,
> + int lo, int hi, unsigned size, int32_t 
> index)
> +{
> +   int64_t offset = ((uint64_t)size) * ((uint64_t)index);
> +   struct amdgpu_bo_va_mapping *mapping;
> +   unsigned i, fpfn, lpfn;
> +   struct amdgpu_bo *bo;
> +   uint64_t addr;
> +   int r;
> +
> +   addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
> +  ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
> +   if (index >= 0) {
> +   addr += offset;
> +   fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
> +   lpfn = 0x1ULL >> PAGE_SHIFT;
> +   } else {
> +   fpfn = 0;
> +   lpfn = (0x1ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
> +   }
> +
> +   r = amdgpu_cs_find_mapping(p, addr, , );
> +   if (r) {
> +   DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
> + addr, lo, hi, size, index);
> +   return r;
> +   }
> +
> +   for (i = 0; i < bo->placement.num_placement; ++i) {
> +   bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
> +   bo->placements[i].lpfn = bo->placements[i].fpfn ?
> +   min(bo->placements[i].fpfn, lpfn) : lpfn;
> +   }
> +   return ttm_bo_validate(>tbo, >placement, false, false);
> +}
> +
> +
>  /**
>   * amdgpu_vce_cs_reloc - command submission relocation
>   *
> @@ -648,12 +685,13 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser 
> *p, uint32_t ib_idx)
> uint32_t allocated = 0;
> uint32_t tmp, handle = 0;
> uint32_t *size = 
> -   int i, r = 0, idx = 0;
> +   unsigned idx;
> +   int i, r = 0;
>
> p->job->vm = NULL;
> ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
>
> -   while (idx < ib->length_dw) {
> +   for (idx = 0; idx < ib->length_dw;) {
> uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
> uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
>
> @@ -664,6 +702,54 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, 
> uint32_t ib_idx)
> }
>
> switch (cmd) {
> +   case 0x0002: /* task info */
> +   fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
> +   bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
> +   break;
> +
> +   case 0x0301: /* encode */
> +   r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
> +  idx + 9, 0, 0);
> +   if (r)
> +   goto out;
> +
> +   r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
> +  idx + 11, 0, 0);
> +   if (r)
> +   goto out;
> +   break;
> +
> +   case 0x0501: /* context buffer */
> +   r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
> +  idx + 2, 0, 0);
> +   if (r)
> +   goto out;
> +   break;
> +
> +   case 0x0504: /* video bitstream buffer */
> +   tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
> +   r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 
> 2,
> +

Re: [PATCH] drm/amdgpu: remove amdgpu_pm_sysfs_init in ci_dpm.c

[Alex Deucher]

On Fri, Nov 17, 2017 at 3:15 AM, Rex Zhu <rex@amd.com> wrote:
> this function was called in amdgpu_device_init
>
> Change-Id: I69aa77ba7db41d2202c3d6ffd606965f0cad3106
> Signed-off-by: Rex Zhu <rex@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 5 -
>  1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
> b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index 5a60c16..b47da60 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -6294,11 +6294,6 @@ static int ci_dpm_late_init(void *handle)
> if (!amdgpu_dpm)
> return 0;
>
> -   /* init the sysfs and debugfs files late */
> -   ret = amdgpu_pm_sysfs_init(adev);
> -   if (ret)
> -   return ret;
> -
> ret = ci_set_temperature_range(adev);
> if (ret)
> return ret;
> --
> 1.9.1
>
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Re: [PATCH 2/4] drm: amd: Fix line continuation formats

[Alex Deucher]

On Thu, Nov 16, 2017 at 10:50 AM, Joe Perches  wrote:
> On Thu, 2017-11-16 at 10:38 -0500, Harry Wentland wrote:
>> On 2017-11-16 10:27 AM, Joe Perches wrote:
>> > Line continuations with excess spacing causes unexpected output.
> []
>> > @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence(
>> > if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
>> > ASSERT(0);
>> > dm_logger_write(link->ctx->logger, LOG_ERROR,
>> > -   "%s: Link Training Error, could not \
>> > -get CR after %d tries. \
>> > -   Possibly voltage swing issue", __func__,
>> > +   "%s: Link Training Error, could not get CR after %d 
>> > tries. Possibly voltage swing issue",
>>
>> Would probably be good to add a '\n' here as well but that's not the main 
>> intention of this patch.
>
> About 1/4 of the dm_logger_write calls are missing
> newlines and I think it should be a separate patch.
>
> I encourage you to fix them one day.
>
>> Reviewed-by: Harry Wentland 
>
> cheers, Joe

Applied.  Thanks!

Alex
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[PATCH] drm/amdgpu/gmc9: make some ECC messages debug only

[Alex Deucher]

To avoid spamming the logs on non-ECC boards.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 798f7fc2d4e9..8529005a5022 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -571,11 +571,11 @@ static int gmc_v9_0_ecc_available(struct amdgpu_device 
*adev)
  reg_val, field_val, fv2);
 
if (!field_val) {
-   DRM_ERROR("ecc: WrEccEn is not set\n");
+   DRM_DEBUG("ecc: WrEccEn is not set\n");
++lost_sheep;
}
if (!fv2) {
-   DRM_ERROR("ecc: RdEccEn is not set\n");
+   DRM_DEBUG("ecc: RdEccEn is not set\n");
++lost_sheep;
}
}
-- 
2.13.6

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Re: [PATCH 3/3] drm/amdgpu: expose the VA above the hole to userspace

[Alex Deucher]

On Thu, Nov 16, 2017 at 5:22 AM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Let userspace know how much area we have above the 48bit VA hole on
> Vega10.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Please add a patch to bump the driver version as well.  With that,
this series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++--
>  include/uapi/drm/amdgpu_drm.h   |  4 
>  2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index e84a7f7f642e..9875d64ae7d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -550,6 +550,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file
> }
> case AMDGPU_INFO_DEV_INFO: {
> struct drm_amdgpu_info_device dev_info = {};
> +   uint64_t vm_size;
>
> dev_info.device_id = dev->pdev->device;
> dev_info.chip_rev = adev->rev_id;
> @@ -577,10 +578,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, 
> void *data, struct drm_file
> dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
> if (amdgpu_sriov_vf(adev))
> dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
> +
> +   vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
> dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
> dev_info.virtual_address_max =
> -   min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
> -   AMDGPU_VA_HOLE_START);
> +   min(vm_size, AMDGPU_VA_HOLE_START);
> +
> +   vm_size -= AMDGPU_VA_RESERVED_SIZE;
> +   if (vm_size > AMDGPU_VA_HOLE_START) {
> +   dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
> +   dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
> +   }
> dev_info.virtual_address_alignment = max((int)PAGE_SIZE, 
> AMDGPU_GPU_PAGE_SIZE);
> dev_info.pte_fragment_size = (1 << 
> adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
> dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index f7a4cf1b6ef6..1dc8089b480a 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -880,6 +880,10 @@ struct drm_amdgpu_info_device {
> __u32 _pad1;
> /* always on cu bitmap */
> __u32 cu_ao_bitmap[4][4];
> +   /** Starting high virtual address for UMDs. */
> +   __u64 high_va_offset;
> +   /** The maximum high virtual address */
> +   __u64 high_va_max;
>  };
>
>  struct drm_amdgpu_info_hw_ip {
> --
> 2.11.0
>
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Re: [PATCH] drm/amdgpu: set f_mapping on exported DMA-bufs

[Alex Deucher]

On Tue, Nov 14, 2017 at 7:13 AM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Otherwise we can't correctly CPU map TTM buffers.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> index 90af8e82b16a..ae9c106979d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> @@ -169,10 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct 
> drm_device *dev,
> int flags)
>  {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
> +   struct dma_buf *buf;
>
> if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
> bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
> return ERR_PTR(-EPERM);
>
> -   return drm_gem_prime_export(dev, gobj, flags);
> +   buf = drm_gem_prime_export(dev, gobj, flags);
> +   if (!IS_ERR(buf))
> +   buf->file->f_mapping = dev->anon_inode->i_mapping;
> +   return buf;
>  }
> --
> 2.11.0
>
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Re: [PATCH] drm/amdgpu/virt: remove redundant variable pf2vf_ver

[Alex Deucher]

On Mon, Nov 13, 2017 at 9:40 AM, Chen, Horace  wrote:
> Reivewed-by: Horace Chen 

Applied.  thanks!

Alex

>
> -Original Message-
> From: Liu, Monk
> Sent: Monday, November 13, 2017 11:43 AM
> To: Chen, Horace ; Colin King 
> ; Deucher, Alexander ; 
> Koenig, Christian ; David Airlie 
> ; Yu, Xiangliang ; 
> amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
> Subject: RE: [PATCH] drm/amdgpu/virt: remove redundant variable pf2vf_ver
> Importance: High
>
> + Horace
>
> -Original Message-
> From: Colin King [mailto:colin.k...@canonical.com]
> Sent: 2017年11月11日 19:51
> To: Deucher, Alexander ; Koenig, Christian 
> ; David Airlie ; Liu, Monk 
> ; Yu, Xiangliang ; 
> amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
> Subject: [PATCH] drm/amdgpu/virt: remove redundant variable pf2vf_ver
>
> From: Colin Ian King 
>
> Variable pf2vf_ver is assigned but never read, it is redundant and hence can 
> be removed.
>
> Cleans up clang warning:
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:310:3: warning: Value stored to 
> 'pf2vf_ver' is never read
>
> Signed-off-by: Colin Ian King 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 6738df836a70..b1cc179512fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -296,7 +296,6 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj,
>
>  void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)  {
> -   uint32_t pf2vf_ver = 0;
> uint32_t pf2vf_size = 0;
> uint32_t checksum = 0;
> uint32_t checkval;
> @@ -309,7 +308,6 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device 
> *adev)
> adev->virt.fw_reserve.p_pf2vf =
> (struct amdgim_pf2vf_info_header *)(
> adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
> -   pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version;
> AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, _size);
> AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, );
>
> --
> 2.14.1
>
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Re: [PATCH 0/7] *** GPU recover V3 ***

[Alex Deucher]

On Mon, Nov 13, 2017 at 6:24 AM, Julien Isorce <julien.iso...@gmail.com> wrote:
> Hi Alex,
>
> Thx for your reply, but in all of the cases you mentioned, the user would
> still
> be able to reboot properly ( i.e. typing reboot or a magic keyboard key)
> or to have a trace of a kernel panic if it happens, is it correct ?

Yes, the deadlock in the GPU scheduler was the issue preventing that
from working properly.

Alex

>
> Thx
> Julien
>
> On 9 November 2017 at 18:08, Alex Deucher <alexdeuc...@gmail.com> wrote:
>>
>> On Thu, Nov 9, 2017 at 4:35 AM, Julien Isorce <julien.iso...@gmail.com>
>> wrote:
>> > Hi Monk.
>> >
>> > I am interested on this. Currently when a "ring X stalled for more than
>> > N
>> > sec" happens it usually goes into the gpu reset routine.
>> > Does it always cause the vram to be lost ? Could you explain what
>> > happens if
>> > the vram remains lost ?
>>
>> It means the contents of vram are gone or unreliable.  In that case
>> applications need to re-initialize all of their buffers before
>> submitting any work.  You really need to add GL_robustness support to
>> any applications you care about.  Whether vram is lost or not depends
>> on the reset method and the asic.  E.g., soft reset of a specific
>> engine won't cause a loss of vram, but a full adapter reset or an FLR
>> may.
>>
>> >
>> > I am asking this because I experienced some recurrent gpu reset that are
>> > marked succeeded from the log but fail in the "resume" step.
>> > I would not be interested in this if it would always leave a chance to
>> > the
>> > user to cleanly reboot the machine.
>> >
>> > The issue is that it can require a hard reboot without kernel panic and
>> > without keeping the keyboard responding to magic keys.
>> > Are those patches trying to address this issue ?
>> >
>> > Note that here "issue" is not referring to the root cause of a ring X
>> > stalled and it is also not referring to why "resume" step fails.
>>
>> There were a few issues that caused problems with GPU reset.  The
>> biggest was that the GPU scheduler deadlocked in certain cases so if
>> you got a GPU hang, the driver locked up.  That should mostly be
>> straightened out at this point.  I think there may still be some
>> deadlocks in the modesetting code after a reset.  Once that is sorted,
>> it will come down to fine tuning the actual reset sequences.  Full
>> adapter resets are the easiest to get working reliably (and are
>> already implemented in the driver), but also the most destructive.
>>
>> Alex
>>
>> >
>> > Thx a lot
>> > Julien
>> >
>> >
>> > On 30 October 2017 at 04:15, Monk Liu <monk@amd.com> wrote:
>> >>
>> >> *** job skipping logic in scheduler part is re-implemented  ***
>> >>
>> >> Monk Liu (7):
>> >>   amd/scheduler:imple job skip feature(v3)
>> >>   drm/amdgpu:implement new GPU recover(v3)
>> >>   drm/amdgpu:cleanup in_sriov_reset and lock_reset
>> >>   drm/amdgpu:cleanup ucode_init_bo
>> >>   drm/amdgpu:block kms open during gpu_reset
>> >>   drm/amdgpu/sriov:fix memory leak in psp_load_fw
>> >>   drm/amdgpu:fix random missing of FLR NOTIFY
>> >>
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   9 +-
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 311
>> >> --
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c |  10 +-
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c   |   2 +-
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  18 +-
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   3 +
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  22 +-
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |   4 +-
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |   2 -
>> >>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |   2 -
>> >>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |   6 +-
>> >>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   6 +-
>> >>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  16 +-
>> >>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c |   2 +-
>> >>  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  39 ++--
>> >>  15 files changed, 220 insertions(+), 232 deletions(-)
>> >>
>> >> --
>> >> 2.7.4
>> >>
>> >> ___
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>> >> amd-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>> >
>> >
>> >
>> > ___
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>> >
>
>
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Re: [PATCH] drm/amdgpu: Properly allocate VM invalidate eng v2

[Alex Deucher]

On Tue, Nov 14, 2017 at 10:22 AM, Oak Zeng <zengshan...@gmail.com> wrote:
> From: ozeng <oak.z...@amd.com>
>
> v1: Properly allocate TLB invalidation engine to avoid conflict.
> v2: Added comments to codes
>
> Change-Id: I9a32cbcb133c07d7efad1a7bd07c6e2098c747e7
> Signed-off-by: Oak Zeng <oak.z...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 15 ---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 16bba97..b067b46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -392,7 +392,16 @@ static int gmc_v9_0_early_init(void *handle)
>  static int gmc_v9_0_late_init(void *handle)
>  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -   unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
> +   /*
> +* The latest engine allocation on gfx9 is:
> +* Engine 0, 1: idle
> +* Engine 2, 3: firmware
> +* Engine 4~13: amdgpu ring, subject to change when ring number 
> changes
> +* Engine 14~15: idle
> +* Engine 16: kfd tlb invalidation
> +* Engine 17: Gart flushes
> +*/
> +   unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
> unsigned i;
>
> for(i = 0; i < adev->num_rings; ++i) {
> @@ -405,9 +414,9 @@ static int gmc_v9_0_late_init(void *handle)
>  ring->funcs->vmhub);
> }
>
> -   /* Engine 17 is used for GART flushes */
> +   /* Engine 16 is used for KFD and 17 for GART flushes */
> for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
> -   BUG_ON(vm_inv_eng[i] > 17);
> +   BUG_ON(vm_inv_eng[i] > 16);
>
> return amdgpu_irq_get(adev, >mc.vm_fault, 0);
>  }
> --
> 2.7.4
>
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[PATCH] drm/amdgpu: don't skip attributes when powerplay is enabled

[Alex Deucher]

The function checks non-powerplay structures so regressed when
the pp_enabled check was removed.  This should ideally be
implemented similarly for powerplay.

Fixes: 6d07fe7bcae57 ("drm/amdgpu: delete pp_enable in adev")
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 3506758349dc..6f56ff606e43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -945,6 +945,10 @@ static umode_t hwmon_attributes_visible(struct kobject 
*kobj,
struct amdgpu_device *adev = dev_get_drvdata(dev);
umode_t effective_mode = attr->mode;
 
+   /* no skipping for powerplay */
+   if (adev->powerplay.cgs_device)
+   return effective_mode;
+
/* Skip limit attributes if DPM is not enabled */
if (!adev->pm.dpm_enabled &&
(attr == _dev_attr_temp1_crit.dev_attr.attr ||
-- 
2.13.6

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Re: [amd-staging-drm-next] regression - no fan info (sensors) on RX580

[Alex Deucher]

On Sun, Oct 8, 2017 at 10:31 PM, Dieter Nützel <die...@nuetzel-hh.de> wrote:
> OK, got it but can't revert the commit clean.
>
> amdgpu-pci-0100
> Adapter: PCI adapter
> fan1: 873 RPM
> temp1:+26.0°C  (crit =  +0.0°C, hyst =  +0.0°C)
>
> SOURCE/amd-staging-drm-next> git bisect good
> 0944c350c8eddf4064e7abb881dd245032fdfa23 is the first bad commit
> commit 0944c350c8eddf4064e7abb881dd245032fdfa23
> Author: Rex Zhu <rex@amd.com>
> Date:   Mon Sep 25 18:51:50 2017 +0800
>
> drm/amdgpu: delete pp_enable in adev
>
> amdgpu not care powerplay or dpm is enabled.
> just check ip functions and pp functions
>
> Change-Id: Iaac75d45170ef9b20e212465f837eaaa798365bd
> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> Signed-off-by: Rex Zhu <rex@amd.com>
>
> :04 04 72361654709479890586e383ec73088e535a1cf5
> 2b6d5a75ffc3b6fd48c63e79bf28faddcc734918 M drivers

I think the attached patch should fix it.

Alex

>
> Greetings,
> Dieter
>
>
>
> Am 09.10.2017 02:19, schrieb Dieter Nützel:
>>
>> Sorry Rex,
>>
>> after return from our vacation,
>> I've tested latest amd-staging-drm-next (e5f6a57e350a)
>> but it is NOT solved on my RX580.
>> I'll try bisecting if I find some more time in the coming days.
>>
>> amdgpu-pci-0100
>> Adapter: PCI adapter
>> temp1:+27.0°C  (crit =  +0.0°C, hyst =  +0.0°C)
>>
>> 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
>> [AMD/ATI] Ellesmere [Radeon RX 470/480/570/580] (rev e7) (prog-if 00
>> [VGA controller])
>> Subsystem: Sapphire Technology Limited Radeon RX 570
>>
>> [36.740] (--) AMDGPU(0): Chipset: "Radeon RX 580 Series" (ChipID =
>> 0x67df)
>>
>> Thanks,
>> Dieter
>>
>> Am 30.09.2017 05:09, schrieb Zhu, Rex:
>>>
>>> Yes, caused by the commit e37a7b4088da
>>> ("drm/amd/powerplay: tidy up ret checks in amd_powerplay.c")
>>>
>>> Replace error when split patches.
>>>
>>> Have sent the fix patch.
>>> Please review.
>>>
>>> Best Regards
>>> Rex
>>>
>>>
>>> -Original Message-
>>> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
>>> Sent: Friday, September 29, 2017 10:11 PM
>>> To: Dieter Nützel; Zhu, Rex
>>> Cc: amd-devel; DRI Devel; Wentland, Harry; Michel Dänzer
>>> Subject: Re: [amd-staging-drm-next] regression - no fan info (sensors) on
>>> RX580
>>>
>>> Rex, probably related to the recent cleanups in powerplay.
>>>
>>> On Fri, Sep 29, 2017 at 10:09 AM, Dieter Nützel <die...@nuetzel-hh.de>
>>> wrote:
>>>>
>>>> Hello all,
>>>>
>>>> since latest update
>>>>
>>>> 1d7da702e70d3c27408a3bb312c71d6be9f7bebe
>>>> drm/amd/powerplay: fix spelling mistake: "dividable" -> "divisible"
>>>>
>>>> I didn't get fan info with my RX580 (Polaris21) any longer.
>>>>
>>>> Worked with this commit:
>>>>
>>>> 786df0b89fe5a0b405d4de0a1ce03003c0743ec3
>>>> drm/amd/display: fix pflip irq registor for raven
>>>>
>>>> Sorry, I do not have full time for bisect, because we are on way to
>>>> our vacation.
>>>>
>>>> Maybe in the evening (only a few commits).
>>>>
>>>> Greetings,
>>>> Dieter
>>
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From 70d57b480ece67dbb4c54294f5b34549043688ac Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deuc...@amd.com>
Date: Mon, 20 Nov 2017 17:49:53 -0500
Subject: [PATCH] drm/amdgpu: don't skip attributes when powerplay is enabled

The function checks non-powerplay structures so regressed when
the pp_enabled check was removed.  This should ideally be
implemented similarly for powerplay.

Fixes: 6d07fe7bcae57 ("drm/amdgpu: delete pp_enable in adev")
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 3506758349dc..6f56ff606e43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -945,6 +945,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	umode_t effective_mode = attr->mode;
 
+	/* no skipping for powerplay */
+	if (adev->powerplay.cgs_device)
+		return effective_mode;
+
 	/* Skip limit attributes if DPM is not enabled */
 	if (!adev->pm.dpm_enabled &&
 	(attr == _dev_attr_temp1_crit.dev_attr.attr ||
-- 
2.13.6

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[PATCH] drm/radeon: fix possible memory leak in radeon_bo_create

[Alex Deucher]

if ttm_bo_init fails, don't leak the bo object.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/radeon/radeon_object.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_object.c 
b/drivers/gpu/drm/radeon/radeon_object.c
index 093594976126..53c5bb6c25e4 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -262,6 +262,8 @@ int radeon_bo_create(struct radeon_device *rdev,
acc_size, sg, resv, _ttm_bo_destroy);
up_read(>pm.mclk_lock);
if (unlikely(r != 0)) {
+   drm_gem_object_release(>gem_base);
+   kfree(bo);
return r;
}
*bo_ptr = bo;
-- 
2.13.6

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Re: [PATCH] drm/radeon: fix possible memory leak in radeon_bo_create

[Alex Deucher]

On Mon, Nov 20, 2017 at 11:36 PM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> if ttm_bo_init fails, don't leak the bo object.
>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>

Ignore this patch.  ttm cleans up for us.

Alex

> ---
>  drivers/gpu/drm/radeon/radeon_object.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c 
> b/drivers/gpu/drm/radeon/radeon_object.c
> index 093594976126..53c5bb6c25e4 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -262,6 +262,8 @@ int radeon_bo_create(struct radeon_device *rdev,
> acc_size, sg, resv, _ttm_bo_destroy);
> up_read(>pm.mclk_lock);
> if (unlikely(r != 0)) {
> +   drm_gem_object_release(>gem_base);
> +   kfree(bo);
> return r;
> }
> *bo_ptr = bo;
> --
> 2.13.6
>
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[PATCH 1/2] drm/radeon: Add dpm quirk for Jet PRO

[Alex Deucher]

Fixes stability issues.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=103370
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/radeon/si_dpm.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index ee3e74266a13..bd4e9638b744 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2984,6 +2984,11 @@ static void si_apply_state_adjust_rules(struct 
radeon_device *rdev,
(rdev->pdev->device == 0x6667)) {
max_sclk = 75000;
}
+   if ((rdev->pdev->revision == 0xC3) ||
+   (rdev->pdev->device == 0x6665)) {
+   max_sclk = 65000;
+   max_mclk = 8;
+   }
} else if (rdev->family == CHIP_OLAND) {
if ((rdev->pdev->revision == 0xC7) ||
(rdev->pdev->revision == 0x80) ||
-- 
2.13.6

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[pull] amdgpu drm-next-4.15

[Alex Deucher]

Hi Dave,

A few more misc fixes for 4.15.  It doesn't look like you pulled
my request from last week.  Those fixes are in this branch as well.

The following changes since commit 451cc55dd17fa5130f05629ac8d90e32facf27f6:

  drm/amd/pp: fix dpm randomly failed on Vega10 (2017-11-15 14:03:45 -0500)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.15

for you to fetch changes up to 446947b44fb8cabc0213ff4efd706931e36b1963:

  drm/amdgpu: fix rmmod KCQ disable failed error (2017-11-21 10:45:05 -0500)


Alex Deucher (2):
  Revert "drm/radeon: dont switch vt on suspend"
  drm/amdgpu: don't skip attributes when powerplay is enabled

Eric Huang (1):
  drm/amd/powerplay: fix unfreeze level smc message for smu7

Monk Liu (2):
  drm/amdgpu:fix memleak in takedown
  drm/amdgpu:fix memleak

Rex Zhu (1):
  drm/amd/pp: fix typecast error in powerplay.

Roger He (1):
  drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

Wang Hongcheng (1):
  drm/amdgpu: fix rmmod KCQ disable failed error

Xiangliang.Yu (1):
  drm/amdgpu: fix kernel hang when starting VNC server

 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c   | 3 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c| 5 -
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 8 
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 9 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 8 
 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c | 4 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c| 2 +-
 drivers/gpu/drm/radeon/radeon_fb.c  | 1 -
 14 files changed, 37 insertions(+), 25 deletions(-)
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Re: [PATCH 1/5] drm/amd/powerplay: Minor fixes in processpptables.c

[Alex Deucher]

On Tue, Nov 21, 2017 at 10:49 AM, Ernst Sjöstrand <ern...@gmail.com> wrote:
> I think my idea here was that if it's not updated later for some
> reason we shouldn't silently return success.
> But I'm guessing this can't happen with current hardware at least.

Right we shouldn't actually hit this case, but if we did, it's fine to
return success.

Alex

>
> Regards
> //Ernst
>
> 2017-11-21 16:15 GMT+01:00 Alex Deucher <alexdeuc...@gmail.com>:
>> On Sun, Nov 19, 2017 at 12:52 PM, Ernst Sjöstrand <ern...@gmail.com> wrote:
>>> Reported by smatch:
>>> init_overdrive_limits() error: uninitialized symbol 'result'.
>>> get_clock_voltage_dependency_table() warn: inconsistent indenting
>>>
>>> Signed-off-by: Ernst Sjöstrand <ern...@gmail.com>
>>> ---
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 6 +++---
>>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 
>>> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>>> index afae32ee2b0d..7c5b426320f1 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>>> @@ -394,8 +394,8 @@ static int get_clock_voltage_dependency_table(struct 
>>> pp_hwmgr *hwmgr,
>>> dep_table->entries[i].clk =
>>> ((unsigned long)table->entries[i].ucClockHigh << 
>>> 16) |
>>> le16_to_cpu(table->entries[i].usClockLow);
>>> -   dep_table->entries[i].v =
>>> -   (unsigned 
>>> long)le16_to_cpu(table->entries[i].usVoltage);
>>> +   dep_table->entries[i].v =
>>> +   (unsigned 
>>> long)le16_to_cpu(table->entries[i].usVoltage);
>>> }
>>>
>>> *ptable = dep_table;
>>> @@ -1042,7 +1042,7 @@ static int init_overdrive_limits_V2_1(struct pp_hwmgr 
>>> *hwmgr,
>>>  static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
>>> const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
>>>  {
>>> -   int result;
>>> +   int result = 1;
>>
>> I think this should probably be initialized to 0.
>>
>> Alex
>>
>>> uint8_t frev, crev;
>>> uint16_t size;
>>>
>>> --
>>> 2.14.1
>>>
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Re: [PATCH] drm/amdgpu: move UVD/VCE and VCN structure out from union

[Alex Deucher]

On Tue, Nov 21, 2017 at 11:13 AM, Leo Liu <leo@amd.com> wrote:
> Wth the current upstream Mesa, kernel will spin error and break when
> starting display manger at least on my Polaris10 card.
>
> This is because the query info from VCN enc from Mesa, and
> "adev->vcn.num_enc_rings" is not zero because of the union.

For some reason the patch doesn't seem to have come through properly
on the mailing list.

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

>
> [ 9066.794232] BUG: unable to handle kernel paging request at
> 99b641ec
> [ 9066.794293] IP: amdgpu_info_ioctl+0xee2/0x1070 [amdgpu]
> [ 9066.794295] PGD 44229067 P4D 44229067 PUD 0
> [ 9066.794300] Oops:  [#1] SMP
> [ 9066.794302] Modules linked in: fuse amdgpu(OE) mfd_core chash ttm k10temp
> i2c_piix4
> [ 9066.794310] CPU: 3 PID: 24999 Comm: Xorg Tainted: G   OE
> 4.14.0-rc3+ #4
> [ 9066.794311] Hardware name: Gigabyte Technology Co., Ltd.
> GA-880GMA-UD2H/GA-880GMA-UD2H, BIOS F5 09/30/2010
> [ 9066.794313] task: 99b62a930040 task.stack: adf280c6
> [ 9066.794339] RIP: 0010:amdgpu_info_ioctl+0xee2/0x1070 [amdgpu]
> [ 9066.794340] RSP: 0018:adf280c63b70 EFLAGS: 00010217
> [ 9066.794342] RAX:  RBX: adf280c63db0 RCX:
> 00063c59
> [ 9066.794344] RDX: 99b641ec RSI:  RDI:
> 
> [ 9066.794345] RBP: adf280c63d28 R08: e200 R09:
> 0001
> [ 9066.794346] R10:  R11:  R12:
> 99b61e7b
> [ 9066.794348] R13: c0127730 R14: 0020 R15:
> 7ffd852f0410
> [ 9066.794350] FS:  7f0265507a00() GS:99b63fcc()
> knlGS:
> [ 9066.794351] CS:  0010 DS:  ES:  CR0: 80050033
> [ 9066.794352] CR2: 99b641ec CR3: 00013763d000 CR4:
> 06e0
> [ 9066.794354] Call Trace:
> [ 9066.794359]  ? kernel_text_address+0x69/0xc0
> [ 9066.794362]  ? rcu_read_lock_sched_held+0x1d/0x60
> [ 9066.794365]  ? module_assert_mutex_or_preempt+0x13/0x40
> [ 9066.794366]  ? __module_address+0x27/0xf0
> [ 9066.794391]  ? amdgpu_drm_ioctl+0x32/0x80 [amdgpu]
> [ 9066.794395]  ? entry_SYSCALL_64_fastpath+0x1f/0xbe
> [ 9066.794396]  ? __kernel_text_address+0xd/0x40
> [ 9066.794399]  ? unwind_get_return_address+0x1a/0x30
> [ 9066.794402]  ? __save_stack_trace+0x61/0xd0
> [ 9066.794404]  ? entry_SYSCALL_64_fastpath+0x1f/0xbe
> [ 9066.794430]  ? amdgpu_debugfs_firmware_info+0x290/0x290 [amdgpu]
> [ 9066.794433]  drm_ioctl_kernel+0x64/0xb0
> [ 9066.794435]  drm_ioctl+0x30a/0x3d0
> [ 9066.794461]  ? amdgpu_debugfs_firmware_info+0x290/0x290 [amdgpu]
> [ 9066.794464]  ? trace_hardirqs_on_caller+0x11f/0x190
> [ 9066.794466]  ? trace_hardirqs_on+0xd/0x10
> [ 9066.794492]  amdgpu_drm_ioctl+0x47/0x80 [amdgpu]
> [ 9066.794495]  do_vfs_ioctl+0x8e/0x640
> [ 9066.794497]  ? trace_hardirqs_on+0xd/0x10
> [ 9066.794500]  ? security_file_ioctl+0x3e/0x60
>
>
> On 11/21/2017 09:28 AM, Leo Liu wrote:
>
> With the enablement of VCN Dec and Enc from user space, User space queries
> kernel for the IP information, if HW has UVD/VCE, the info comes from these
> IP blocks, but this could end up mis-interpret for VCN when they are in the
> union, ther other way same when HW with VCN block.
>
> Signed-off-by: Leo Liu <leo@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 20 
>  1 file changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 750336dce0e9..86f91789de6d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1590,18 +1590,14 @@ struct amdgpu_device {
>   /* sdma */
>   struct amdgpu_sdma sdma;
>
> - union {
> - struct {
> - /* uvd */
> - struct amdgpu_uvd uvd;
> -
> - /* vce */
> - struct amdgpu_vce vce;
> - };
> -
> - /* vcn */
> - struct amdgpu_vcn vcn;
> - };
> + /* uvd */
> + struct amdgpu_uvd uvd;
> +
> + /* vce */
> + struct amdgpu_vce vce;
> +
> + /* vcn */
> + struct amdgpu_vcn vcn;
>
>   /* firmwares */
>   struct amdgpu_firmware firmware;
>
>
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH 1/5] drm/amd/powerplay: Minor fixes in processpptables.c

[Alex Deucher]

On Sun, Nov 19, 2017 at 12:52 PM, Ernst Sjöstrand  wrote:
> Reported by smatch:
> init_overdrive_limits() error: uninitialized symbol 'result'.
> get_clock_voltage_dependency_table() warn: inconsistent indenting
>
> Signed-off-by: Ernst Sjöstrand 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> index afae32ee2b0d..7c5b426320f1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> @@ -394,8 +394,8 @@ static int get_clock_voltage_dependency_table(struct 
> pp_hwmgr *hwmgr,
> dep_table->entries[i].clk =
> ((unsigned long)table->entries[i].ucClockHigh << 16) |
> le16_to_cpu(table->entries[i].usClockLow);
> -   dep_table->entries[i].v =
> -   (unsigned 
> long)le16_to_cpu(table->entries[i].usVoltage);
> +   dep_table->entries[i].v =
> +   (unsigned 
> long)le16_to_cpu(table->entries[i].usVoltage);
> }
>
> *ptable = dep_table;
> @@ -1042,7 +1042,7 @@ static int init_overdrive_limits_V2_1(struct pp_hwmgr 
> *hwmgr,
>  static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
> const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
>  {
> -   int result;
> +   int result = 1;

I think this should probably be initialized to 0.

Alex

> uint8_t frev, crev;
> uint16_t size;
>
> --
> 2.14.1
>
> ___
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Re: [PATCH 1/5] drm/amd/powerplay: Minor fixes in processpptables.c

[Alex Deucher]

On Tue, Nov 21, 2017 at 10:15 AM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> On Sun, Nov 19, 2017 at 12:52 PM, Ernst Sjöstrand <ern...@gmail.com> wrote:
>> Reported by smatch:
>> init_overdrive_limits() error: uninitialized symbol 'result'.
>> get_clock_voltage_dependency_table() warn: inconsistent indenting
>>
>> Signed-off-by: Ernst Sjöstrand <ern...@gmail.com>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> index afae32ee2b0d..7c5b426320f1 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
>> @@ -394,8 +394,8 @@ static int get_clock_voltage_dependency_table(struct 
>> pp_hwmgr *hwmgr,
>> dep_table->entries[i].clk =
>> ((unsigned long)table->entries[i].ucClockHigh << 16) 
>> |
>> le16_to_cpu(table->entries[i].usClockLow);
>> -   dep_table->entries[i].v =
>> -   (unsigned 
>> long)le16_to_cpu(table->entries[i].usVoltage);
>> +   dep_table->entries[i].v =
>> +   (unsigned 
>> long)le16_to_cpu(table->entries[i].usVoltage);
>> }
>>
>> *ptable = dep_table;
>> @@ -1042,7 +1042,7 @@ static int init_overdrive_limits_V2_1(struct pp_hwmgr 
>> *hwmgr,
>>  static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
>> const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
>>  {
>> -   int result;
>> +   int result = 1;
>
> I think this should probably be initialized to 0.

Applied the series with that fixed up locally.

Thanks!

Alex

>
> Alex
>
>> uint8_t frev, crev;
>> uint16_t size;
>>
>> --
>> 2.14.1
>>
>> ___
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[PATCH] drm/amdgpu: used cached gca values for cik_read_register

[Alex Deucher]

Using the cached values has less latency for bare metal and
prevents reading back bogus values if the engine is powergated.

This was implemented for VI and SI, but somehow CIK got missed.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cik.c | 111 +--
 1 file changed, 95 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6128080ff662..8ba056a2a5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1023,22 +1023,101 @@ static const struct amdgpu_allowed_register_entry 
cik_allowed_read_registers[] =
{mmPA_SC_RASTER_CONFIG_1, true},
 };
 
-static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
- u32 se_num, u32 sh_num,
- u32 reg_offset)
+
+static uint32_t cik_get_register_value(struct amdgpu_device *adev,
+  bool indexed, u32 se_num,
+  u32 sh_num, u32 reg_offset)
 {
-   uint32_t val;
+   if (indexed) {
+   uint32_t val;
+   unsigned se_idx = (se_num == 0x) ? 0 : se_num;
+   unsigned sh_idx = (sh_num == 0x) ? 0 : sh_num;
+
+   switch (reg_offset) {
+   case mmCC_RB_BACKEND_DISABLE:
+   return 
adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
+   case mmGC_USER_RB_BACKEND_DISABLE:
+   return 
adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
+   case mmPA_SC_RASTER_CONFIG:
+   return 
adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
+   case mmPA_SC_RASTER_CONFIG_1:
+   return 
adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
+   }
 
-   mutex_lock(>grbm_idx_mutex);
-   if (se_num != 0x || sh_num != 0x)
-   amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0x);
+   mutex_lock(>grbm_idx_mutex);
+   if (se_num != 0x || sh_num != 0x)
+   amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 
0x);
 
-   val = RREG32(reg_offset);
+   val = RREG32(reg_offset);
 
-   if (se_num != 0x || sh_num != 0x)
-   amdgpu_gfx_select_se_sh(adev, 0x, 0x, 
0x);
-   mutex_unlock(>grbm_idx_mutex);
-   return val;
+   if (se_num != 0x || sh_num != 0x)
+   amdgpu_gfx_select_se_sh(adev, 0x, 0x, 
0x);
+   mutex_unlock(>grbm_idx_mutex);
+   return val;
+   } else {
+   unsigned idx;
+
+   switch (reg_offset) {
+   case mmGB_ADDR_CONFIG:
+   return adev->gfx.config.gb_addr_config;
+   case mmMC_ARB_RAMCFG:
+   return adev->gfx.config.mc_arb_ramcfg;
+   case mmGB_TILE_MODE0:
+   case mmGB_TILE_MODE1:
+   case mmGB_TILE_MODE2:
+   case mmGB_TILE_MODE3:
+   case mmGB_TILE_MODE4:
+   case mmGB_TILE_MODE5:
+   case mmGB_TILE_MODE6:
+   case mmGB_TILE_MODE7:
+   case mmGB_TILE_MODE8:
+   case mmGB_TILE_MODE9:
+   case mmGB_TILE_MODE10:
+   case mmGB_TILE_MODE11:
+   case mmGB_TILE_MODE12:
+   case mmGB_TILE_MODE13:
+   case mmGB_TILE_MODE14:
+   case mmGB_TILE_MODE15:
+   case mmGB_TILE_MODE16:
+   case mmGB_TILE_MODE17:
+   case mmGB_TILE_MODE18:
+   case mmGB_TILE_MODE19:
+   case mmGB_TILE_MODE20:
+   case mmGB_TILE_MODE21:
+   case mmGB_TILE_MODE22:
+   case mmGB_TILE_MODE23:
+   case mmGB_TILE_MODE24:
+   case mmGB_TILE_MODE25:
+   case mmGB_TILE_MODE26:
+   case mmGB_TILE_MODE27:
+   case mmGB_TILE_MODE28:
+   case mmGB_TILE_MODE29:
+   case mmGB_TILE_MODE30:
+   case mmGB_TILE_MODE31:
+   idx = (reg_offset - mmGB_TILE_MODE0);
+   return adev->gfx.config.tile_mode_array[idx];
+   case mmGB_MACROTILE_MODE0:
+   case mmGB_MACROTILE_MODE1:
+   case mmGB_MACROTILE_MODE2:
+   case mmGB_MACROTILE_MODE3:
+   case mmGB_MACROTILE_MODE4:
+   case mmGB_MACROTILE_MODE5:
+   case mmGB_MACROTILE_MODE6:
+   case mmGB_MACROTILE_MODE7:
+   case mmGB_MACROTILE_MODE8:
+   case mmGB_MACROTILE_MODE9:
+  

Re: [PATCH] drm/amd/vce: correct vce fw data and stack size config for sriov

[Alex Deucher]

On Tue, Nov 21, 2017 at 3:33 AM, Frank Min  wrote:

Please provide a better patch description.  What was the problem and
how did you fix it?

Alex

> Signed-off-by: Frank Min 
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 30 +-
>  1 file changed, 17 insertions(+), 13 deletions(-)
>  mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> old mode 100644
> new mode 100755
> index 7574554..4a92530
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -243,37 +243,41 @@ static int vce_v4_0_sriov_start(struct amdgpu_device 
> *adev)
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VM_CTRL), 0);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> -   
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> -   
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> 
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
> +   
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);
> } else {
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
> adev->vce.gpu_addr >> 8);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
> +   (adev->vce.gpu_addr >> 40) & 
> 0xff);
> +   }
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
> adev->vce.gpu_addr >> 8);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_64BIT_BAR1),
> +   (adev->vce.gpu_addr >> 40) & 
> 0xff);
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
> adev->vce.gpu_addr >> 8);
> -   }
> +   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),
> +   (adev->vce.gpu_addr >> 40) & 
> 0xff);
>
> offset = AMDGPU_VCE_FIRMWARE_OFFSET;
> size = VCE_V4_0_FW_SIZE;
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_VCPU_CACHE_OFFSET0),
> -   offset & 0x7FFF);
> +   offset & ~0x0f00);
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_VCPU_CACHE_SIZE0), size);
>
> -   offset += size;
> +   offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? 
> offset + size : 0;
> size = VCE_V4_0_STACK_SIZE;
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_VCPU_CACHE_OFFSET1),
> -   offset & 0x7FFF);
> +   (offset & ~0x0f00) | (1 << 24));
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_VCPU_CACHE_SIZE1), size);
>
> offset += size;
> size = VCE_V4_0_DATA_SIZE;
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_VCPU_CACHE_OFFSET2),
> -   offset & 0x7FFF);
> +   (offset & ~0x0f00) | (2 << 24));
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
> mmVCE_VCPU_CACHE_SIZE2), size);
>
> MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 

Re: [PATCH] drm/amdgpu: always make gart.table_addr 64bit

[Alex Deucher]

On Thu, Nov 16, 2017 at 12:31 PM, Christian König
<ckoenig.leichtzumer...@gmail.com> wrote:
> Fixing warning/compile errors on 32bit kernels.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index f15e319580ec..5eb1a6800f72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -39,7 +39,7 @@ struct amdgpu_gart_funcs;
>  #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & 
> ~AMDGPU_GPU_PAGE_MASK)
>
>  struct amdgpu_gart {
> -   dma_addr_t  table_addr;
> +   u64 table_addr;
> struct amdgpu_bo*robj;
> void*ptr;
> unsignednum_gpu_pages;
> --
> 2.11.0
>
> ___
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Re: [PATCH] Revert "drm/radeon: dont switch vt on suspend"

[Alex Deucher]

Ping?


On Tue, Nov 14, 2017 at 5:33 PM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> Fixes distorted colors on some cards on resume from suspend.
>
> This reverts commit b9729b17a414f99c61f4db9ac9f9ed987fa0cbfe.
>
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=98832
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/radeon/radeon_fb.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_fb.c 
> b/drivers/gpu/drm/radeon/radeon_fb.c
> index 2fcf805d3a16..33b821d6d018 100644
> --- a/drivers/gpu/drm/radeon/radeon_fb.c
> +++ b/drivers/gpu/drm/radeon/radeon_fb.c
> @@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
> }
>
> info->par = rfbdev;
> -   info->skip_vt_switch = true;
>
> ret = radeon_framebuffer_init(rdev->ddev, >rfb, _cmd, 
> gobj);
> if (ret) {
> --
> 2.13.6
>
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Re: [PATCH] drm/amd/display: remove unnecessary cast and use kcalloc instead of kzalloc

[Alex Deucher]

On Wed, Nov 15, 2017 at 10:45 AM, Colin King  wrote:
> From: Colin Ian King 
>
> Use kcalloc instead of kzalloc and the cast on the return from kzalloc is
> unnecessary and can be removed.
>
> Signed-off-by: Colin Ian King 

Reviewed and pushed.

Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/basics/logger.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
> b/drivers/gpu/drm/amd/display/dc/basics/logger.c
> index e04e8ecd4874..2ff5b467603d 100644
> --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
> +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
> @@ -70,9 +70,8 @@ static bool construct(struct dc_context *ctx, struct 
> dal_logger *logger,
>  {
> /* malloc buffer and init offsets */
> logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
> -   logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * 
> sizeof(char),
> -GFP_KERNEL);
> -
> +   logger->log_buffer = kcalloc(logger->log_buffer_size, sizeof(char),
> +GFP_KERNEL);
> if (!logger->log_buffer)
> return false;
>
> --
> 2.14.1
>
> ___
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