Re: [PATCH 03/12] drm/amdgpu: allow flushing VMID0 before IB execution as well

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This allows us to queue IBs which needs an up to date system domain as well.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index f774b3f..1b30d2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -172,7 +172,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
> num_ibs,
> if (ring->funcs->insert_start)
> ring->funcs->insert_start(ring);
>
> -   if (vm) {
> +   if (job) {
> r = amdgpu_vm_flush(ring, job);
> if (r) {
> amdgpu_ring_undo(ring);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 3d641e1..4510627 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -81,6 +81,8 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, 
> unsigned size,
> r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
> if (r)
> kfree(*job);
> +   else
> +   (*job)->vm_pd_addr = adev->gart.table_addr;
>
> return r;
>  }
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 06/12] drm/amdgpu: bind BOs with GTT space allocated directly

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This avoids binding them later on.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 49 
> ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
>  3 files changed, 46 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index f7d22c4..6fdf83a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -81,6 +81,20 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager 
> *man)
>  }
>
>  /**
> + * amdgpu_gtt_mgr_is_allocated - Check if mem has address space
> + *
> + * @mem: the mem object to check
> + *
> + * Check if a mem object has already address space allocated.
> + */
> +bool amdgpu_gtt_mgr_is_alloced(struct ttm_mem_reg *mem)

mismatch between documentation and function name.  I prefer the full
amdgpu_gtt_mgr_is_allocated or even better
amdgpu_gtt_mgr_addr_is_allocated.  With that fixed up:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>


> +{
> +   struct drm_mm_node *node = mem->mm_node;
> +
> +   return (node->start != AMDGPU_BO_INVALID_OFFSET);
> +}
> +
> +/**
>   * amdgpu_gtt_mgr_alloc - allocate new ranges
>   *
>   * @man: TTM memory type manager
> @@ -101,7 +115,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
> unsigned long fpfn, lpfn;
> int r;
>
> -   if (node->start != AMDGPU_BO_INVALID_OFFSET)
> +   if (amdgpu_gtt_mgr_is_alloced(mem))
> return 0;
>
> if (place)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 5bfe7f6..eb0d7d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -681,6 +681,31 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt 
> *ttm)
> sg_free_table(ttm->sg);
>  }
>
> +static int amdgpu_ttm_do_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
> +{
> +   struct amdgpu_ttm_tt *gtt = (void *)ttm;
> +   uint64_t flags;
> +   int r;
> +
> +   spin_lock(>adev->gtt_list_lock);
> +   flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, mem);
> +   gtt->offset = (u64)mem->start << PAGE_SHIFT;
> +   r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
> +   ttm->pages, gtt->ttm.dma_address, flags);
> +
> +   if (r) {
> +   DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
> + ttm->num_pages, gtt->offset);
> +   goto error_gart_bind;
> +   }
> +
> +   list_add_tail(>list, >adev->gtt_list);
> +error_gart_bind:
> +   spin_unlock(>adev->gtt_list_lock);
> +   return r;
> +
> +}
> +
>  static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
>struct ttm_mem_reg *bo_mem)
>  {
> @@ -704,7 +729,10 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
> bo_mem->mem_type == AMDGPU_PL_OA)
> return -EINVAL;
>
> -   return 0;
> +   if (amdgpu_gtt_mgr_is_alloced(bo_mem))
> +   r = amdgpu_ttm_do_bind(ttm, bo_mem);
> +
> +   return r;
>  }
>
>  bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
> @@ -717,8 +745,6 @@ bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
>  int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
>  {
> struct ttm_tt *ttm = bo->ttm;
> -   struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
> -   uint64_t flags;
> int r;
>
> if (!ttm || amdgpu_ttm_is_bound(ttm))
> @@ -731,22 +757,7 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct 
> ttm_mem_reg *bo_mem)
> return r;
> }
>
> -   spin_lock(>adev->gtt_list_lock);
> -   flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
> -   gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
> -   r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
> -   ttm->pages, gtt->ttm.dma_address, flags);
> -
> -   if (r) {
> -   DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
> - ttm->num_pages, gtt->offset);
> -   go

Re: [PATCH 12/12] drm/amdgpu: add gtt_sys_limit

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> Limit the size of the GART table for the system domain.
>
> This saves us a bunch of visible VRAM, but also limitates the maximum BO size 
> we can swap out.

The last phrase can be dropped as it's no longer relevant.

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

>
> Signed-off-by: Christian König <christian.koe...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 6 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c| 8 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 --
>  5 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4a2b33d..ef8e6b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -76,6 +76,7 @@
>  extern int amdgpu_modeset;
>  extern int amdgpu_vram_limit;
>  extern int amdgpu_gart_size;
> +extern unsigned amdgpu_gart_sys_limit;
>  extern int amdgpu_moverate;
>  extern int amdgpu_benchmarking;
>  extern int amdgpu_testing;
> @@ -605,6 +606,7 @@ struct amdgpu_mc {
> u64 mc_vram_size;
> u64 visible_vram_size;
> u64 gtt_size;
> +   u64 gtt_sys_limit;
> u64 gtt_start;
> u64 gtt_end;
> u64 vram_start;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5b1220f..7e3f8cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1122,6 +1122,12 @@ static void amdgpu_check_arguments(struct 
> amdgpu_device *adev)
> }
> }
>
> +   if (amdgpu_gart_sys_limit < 32) {
> +   dev_warn(adev->dev, "gart sys limit (%d) too small\n",
> +amdgpu_gart_sys_limit);
> +   amdgpu_gart_sys_limit = 32;
> +   }
> +
> amdgpu_check_vm_size(adev);
>
> amdgpu_check_block_size(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 5a1d794..907ae5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -75,6 +75,7 @@
>
>  int amdgpu_vram_limit = 0;
>  int amdgpu_gart_size = -1; /* auto */
> +unsigned amdgpu_gart_sys_limit = 256;
>  int amdgpu_moverate = -1; /* auto */
>  int amdgpu_benchmarking = 0;
>  int amdgpu_testing = 0;
> @@ -124,6 +125,9 @@ module_param_named(vramlimit, amdgpu_vram_limit, int, 
> 0600);
>  MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 
> 64, etc., -1 = auto)");
>  module_param_named(gartsize, amdgpu_gart_size, int, 0600);
>
> +MODULE_PARM_DESC(gartlimit, "GART limit for the system domain in megabytes 
> (default 256)");
> +module_param_named(gartlimit, amdgpu_gart_sys_limit, int, 0600);
> +
>  MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
> etc., -1=auto, 0=1=disabled)");
>  module_param_named(moverate, amdgpu_moverate, int, 0600);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index d99b2b2..f82eeaa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -70,6 +70,9 @@ void amdgpu_gart_set_defaults(struct amdgpu_device *adev)
> adev->mc.mc_vram_size);
> else
> adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
> +
> +   adev->mc.gtt_sys_limit = min((uint64_t)amdgpu_gart_sys_limit << 20,
> +adev->mc.gtt_size);
>  }
>
>  /**
> @@ -384,8 +387,9 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
> if (r)
> return r;
> /* Compute table size */
> -   adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
> -   adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
> +   adev->gart.num_cpu_pages = adev->mc.gtt_sys_limit / PAGE_SIZE;
> +   adev->gart.num_gpu_pages = adev->mc.gtt_sys_limit /
> +   AMDGPU_GPU_PAGE_SIZE;
> DRM_INFO("GART: num cpu pages %u, nu

Re: [PATCH 04/12] drm/amdgpu: add vm_needs_flush parameter to amdgpu_copy_buffer

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This allows us to flush the system VM here.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c|  4 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_test.c  |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   | 12 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  9 -
>  5 files changed, 15 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> index 1beae5b..2fb299a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> @@ -40,7 +40,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device 
> *adev, unsigned size,
> for (i = 0; i < n; i++) {
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, ,
> -  false);
> +  false, false);
> if (r)
> goto exit_do_move;
> r = dma_fence_wait(fence, false);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 8ee6965..c34cf2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -535,7 +535,7 @@ int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
>
> r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
>amdgpu_bo_size(bo), resv, fence,
> -  direct);
> +  direct, false);
> if (!r)
> amdgpu_bo_fence(bo, *fence, true);
>
> @@ -588,7 +588,7 @@ int amdgpu_bo_restore_from_shadow(struct amdgpu_device 
> *adev,
>
> r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
>amdgpu_bo_size(bo), resv, fence,
> -  direct);
> +  direct, false);
> if (!r)
> amdgpu_bo_fence(bo, *fence, true);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
> index 15510da..d02e611 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
> @@ -111,7 +111,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device 
> *adev)
> amdgpu_bo_kunmap(gtt_obj[i]);
>
> r = amdgpu_copy_buffer(ring, gtt_addr, vram_addr,
> -  size, NULL, , false);
> +  size, NULL, , false, false);
>
> if (r) {
> DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
> @@ -156,7 +156,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device 
> *adev)
> amdgpu_bo_kunmap(vram_obj);
>
> r = amdgpu_copy_buffer(ring, vram_addr, gtt_addr,
> -  size, NULL, , false);
> +  size, NULL, , false, false);
>
> if (r) {
> DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index e4860ac..bbe1639 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -318,7 +318,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
>
> r = amdgpu_copy_buffer(ring, old_start, new_start,
>cur_pages * PAGE_SIZE,
> -  bo->resv, , false);
> +  bo->resv, , false, false);
> if (r)
> goto error;
>
> @@ -1256,12 +1256,11 @@ int amdgpu_mmap(struct file *filp, struct 
> vm_area_struct *vma)
> return ttm_bo_mmap(filp, vma, >mman.bdev);
>  }
>
> -int amdgpu_copy_buffer(struct amdgpu_ring *ring,
> -  uint64_t src_offset,
> -  uint64_t dst_offset,
> -  uint32_t byte_count,
> +int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> +  uint64_t dst_offset

Re: [PATCH 08/12] drm/amdgpu: add amdgpu_gart_map function

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This allows us to write the mapped PTEs into
> an IB instead of the table directly.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  3 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 64 
> 
>  2 files changed, 52 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 810796a..4a2b33d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -572,6 +572,9 @@ int amdgpu_gart_init(struct amdgpu_device *adev);
>  void amdgpu_gart_fini(struct amdgpu_device *adev);
>  int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
> int pages);
> +int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> +   int pages, dma_addr_t *dma_addr, uint64_t flags,
> +   void *dst);
>  int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
>  int pages, struct page **pagelist,
>  dma_addr_t *dma_addr, uint64_t flags);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 8877015..d99b2b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -280,6 +280,43 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, 
> uint64_t offset,
>  }
>
>  /**
> + * amdgpu_gart_map - map dma_addresses into GART entries
> + *
> + * @adev: amdgpu_device pointer
> + * @offset: offset into the GPU's gart aperture
> + * @pages: number of pages to bind
> + * @dma_addr: DMA addresses of pages
> + *
> + * Map the dma_addresses into GART entries (all asics).
> + * Returns 0 for success, -EINVAL for failure.
> + */
> +int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> +   int pages, dma_addr_t *dma_addr, uint64_t flags,
> +   void *dst)
> +{
> +   uint64_t page_base;
> +   unsigned t, p;
> +   int i, j;
> +
> +   if (!adev->gart.ready) {
> +   WARN(1, "trying to bind memory to uninitialized GART !\n");
> +   return -EINVAL;
> +   }
> +
> +   t = offset / AMDGPU_GPU_PAGE_SIZE;
> +   p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
> +
> +   for (i = 0; i < pages; i++, p++) {
> +   page_base = dma_addr[i];
> +   for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) 
> {
> +   amdgpu_gart_set_pte_pde(adev, dst, t, page_base, 
> flags);
> +   page_base += AMDGPU_GPU_PAGE_SIZE;
> +   }
> +   }
> +   return 0;
> +}
> +
> +/**
>   * amdgpu_gart_bind - bind pages into the gart page table
>   *
>   * @adev: amdgpu_device pointer
> @@ -296,31 +333,28 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, 
> uint64_t offset,
>  int pages, struct page **pagelist, dma_addr_t *dma_addr,
>  uint64_t flags)
>  {
> -   unsigned t;
> -   unsigned p;
> -   uint64_t page_base;
> -   int i, j;
> +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> +   unsigned i;
> +#endif
> +   int r;
>
> if (!adev->gart.ready) {
> WARN(1, "trying to bind memory to uninitialized GART !\n");
> return -EINVAL;
> }
>
> -   t = offset / AMDGPU_GPU_PAGE_SIZE;
> -   p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
> -
> -   for (i = 0; i < pages; i++, p++) {
>  #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> +   for (i = 0; i < pages; i++, p++)
> adev->gart.pages[p] = pagelist[i];
>  #endif
> -   if (adev->gart.ptr) {
> -   page_base = dma_addr[i];
> -   for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 
> j++, t++) {
> -   amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, 
> t, page_base, flags);
> -   page_base += AMDGPU_GPU_PAGE_SIZE;
> -   }
> -   }
> +
> +   if (adev->gart.ptr) {
> +   r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
> +   adev->gart.ptr);
> +   if (r)
> +   return r;
> }
> +
> mb();
> amdgpu_gart_flush_gpu_tlb(adev, 0);
> return 0;
> --
> 2.7.4
>
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[PATCH] drm/amdgpu/acp: properly handle powergating in hw_fini

[Alex Deucher]

Stoney does not have powergating, so make the powergating
teardown dependent on whether we have a genpd structure.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 06879d1..091b5e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -398,20 +398,22 @@ static int acp_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
/* return early if no ACP */
-   if (!adev->acp.acp_genpd)
+   if (!adev->acp.acp_cell)
return 0;
 
-   for (i = 0; i < ACP_DEVS ; i++) {
-   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-   ret = pm_genpd_remove_device(>acp.acp_genpd->gpd, dev);
-   /* If removal fails, dont giveup and try rest */
-   if (ret)
-   dev_err(dev, "remove dev from genpd failed\n");
+   if (adev->acp.acp_genpd) {
+   for (i = 0; i < ACP_DEVS ; i++) {
+   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+   ret = pm_genpd_remove_device(>acp.acp_genpd->gpd, 
dev);
+   /* If removal fails, dont giveup and try rest */
+   if (ret)
+   dev_err(dev, "remove dev from genpd failed\n");
+   }
+   kfree(adev->acp.acp_genpd);
}
 
mfd_remove_devices(adev->acp.parent);
kfree(adev->acp.acp_res);
-   kfree(adev->acp.acp_genpd);
kfree(adev->acp.acp_cell);
 
return 0;
-- 
2.5.5

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Re: [PATCH 07/12] drm/amdgpu: reserve the first 2x2MB of GART

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
 wrote:
> From: Christian König 
>
> We want to use them as remap address space.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 5 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index 6fdf83a..a0976dc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -43,12 +43,15 @@ static int amdgpu_gtt_mgr_init(struct 
> ttm_mem_type_manager *man,
>unsigned long p_size)
>  {
> struct amdgpu_gtt_mgr *mgr;
> +   uint64_t start, size;
>
> mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
> if (!mgr)
> return -ENOMEM;
>
> -   drm_mm_init(>mm, 0, p_size);
> +   start = AMDGPU_GTT_MAX_TRANSFER_SIZE * 
> AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
> +   size = p_size - start;
> +   drm_mm_init(>mm, start, size);
> spin_lock_init(>lock);
> mgr->available = p_size;
> man->priv = mgr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 2ade5c5..9c4da0a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -34,6 +34,9 @@
>  #define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
>  #define AMDGPU_PL_FLAG_OA  (TTM_PL_FLAG_PRIV << 2)
>
> +#define AMDGPU_GTT_MAX_TRANSFER_SIZE   512

Maybe AMDGPU_GTT_MAX_TRANSFER_SIZE_PAGES?  Also you may want to update
the patch title to say 2x512 pages rather than 2x2MB.

> +#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS2
> +
>  struct amdgpu_mman {
> struct ttm_bo_global_refbo_global_ref;
> struct drm_global_reference mem_global_ref;
> --
> 2.7.4
>
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Re: [PATCH 01/12] drm/amdgpu: move ring helpers to amdgpu_ring.h

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> Keep them where they belong.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 44 
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 42 ++
>  2 files changed, 42 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ab1dad2..810796a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1801,50 +1801,6 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device 
> *adev);
>  #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
>  #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
>
> -/*
> - * RING helpers.
> - */
> -static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
> -{
> -   if (ring->count_dw <= 0)
> -   DRM_ERROR("amdgpu: writing more dwords to the ring than 
> expected!\n");
> -   ring->ring[ring->wptr++ & ring->buf_mask] = v;
> -   ring->wptr &= ring->ptr_mask;
> -   ring->count_dw--;
> -}
> -
> -static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void 
> *src, int count_dw)
> -{
> -   unsigned occupied, chunk1, chunk2;
> -   void *dst;
> -
> -   if (unlikely(ring->count_dw < count_dw)) {
> -   DRM_ERROR("amdgpu: writing more dwords to the ring than 
> expected!\n");
> -   return;
> -   }
> -
> -   occupied = ring->wptr & ring->buf_mask;
> -   dst = (void *)>ring[occupied];
> -   chunk1 = ring->buf_mask + 1 - occupied;
> -   chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
> -   chunk2 = count_dw - chunk1;
> -   chunk1 <<= 2;
> -   chunk2 <<= 2;
> -
> -   if (chunk1)
> -   memcpy(dst, src, chunk1);
> -
> -   if (chunk2) {
> -   src += chunk1;
> -   dst = (void *)ring->ring;
> -   memcpy(dst, src, chunk2);
> -   }
> -
> -   ring->wptr += count_dw;
> -   ring->wptr &= ring->ptr_mask;
> -   ring->count_dw -= count_dw;
> -}
> -
>  static inline struct amdgpu_sdma_instance *
>  amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>  {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index bc8dec9..04cbc3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -212,4 +212,46 @@ static inline void amdgpu_ring_clear_ring(struct 
> amdgpu_ring *ring)
>
>  }
>
> +static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
> +{
> +   if (ring->count_dw <= 0)
> +   DRM_ERROR("amdgpu: writing more dwords to the ring than 
> expected!\n");
> +   ring->ring[ring->wptr++ & ring->buf_mask] = v;
> +   ring->wptr &= ring->ptr_mask;
> +   ring->count_dw--;
> +}
> +
> +static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
> + void *src, int count_dw)
> +{
> +   unsigned occupied, chunk1, chunk2;
> +   void *dst;
> +
> +   if (unlikely(ring->count_dw < count_dw)) {
> +   DRM_ERROR("amdgpu: writing more dwords to the ring than 
> expected!\n");
> +   return;
> +   }
> +
> +   occupied = ring->wptr & ring->buf_mask;
> +   dst = (void *)>ring[occupied];
> +   chunk1 = ring->buf_mask + 1 - occupied;
> +   chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
> +   chunk2 = count_dw - chunk1;
> +   chunk1 <<= 2;
> +   chunk2 <<= 2;
> +
> +   if (chunk1)
> +   memcpy(dst, src, chunk1);
> +
> +   if (chunk2) {
> +   src += chunk1;
> +   dst = (void *)ring->ring;
> +   memcpy(dst, src, chunk2);
> +   }
> +
> +   ring->wptr += count_dw;
> +   ring->wptr &= ring->ptr_mask;
> +   ring->count_dw -= count_dw;
> +}
> +
>  #endif
> --
> 2.7.4
>
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Re: [PATCH 05/12] drm/amdgpu: bind BOs to TTM only once

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> No need to do this on every round.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 70 
> ++---
>  1 file changed, 29 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index bbe1639..5bfe7f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -252,29 +252,15 @@ static void amdgpu_move_null(struct ttm_buffer_object 
> *bo,
> new_mem->mm_node = NULL;
>  }
>
> -static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
> -  struct drm_mm_node *mm_node,
> -  struct ttm_mem_reg *mem,
> -  uint64_t *addr)
> +static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
> +   struct drm_mm_node *mm_node,
> +   struct ttm_mem_reg *mem)
>  {
> -   int r;
> -
> -   switch (mem->mem_type) {
> -   case TTM_PL_TT:
> -   r = amdgpu_ttm_bind(bo, mem);
> -   if (r)
> -   return r;
> -
> -   case TTM_PL_VRAM:
> -   *addr = mm_node->start << PAGE_SHIFT;
> -   *addr += bo->bdev->man[mem->mem_type].gpu_offset;
> -   break;
> -   default:
> -   DRM_ERROR("Unknown placement %d\n", mem->mem_type);
> -   return -EINVAL;
> -   }
> +   uint64_t addr;
>
> -   return 0;
> +   addr = mm_node->start << PAGE_SHIFT;
> +   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   return addr;
>  }
>
>  static int amdgpu_move_blit(struct ttm_buffer_object *bo,
> @@ -298,18 +284,25 @@ static int amdgpu_move_blit(struct ttm_buffer_object 
> *bo,
> return -EINVAL;
> }
>
> +   if (old_mem->mem_type == TTM_PL_TT) {
> +   r = amdgpu_ttm_bind(bo, old_mem);
> +   if (r)
> +   return r;
> +   }
> +
> old_mm = old_mem->mm_node;
> -   r = amdgpu_mm_node_addr(bo, old_mm, old_mem, _start);
> -   if (r)
> -   return r;
> old_size = old_mm->size;
> +   old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
>
> +   if (new_mem->mem_type == TTM_PL_TT) {
> +   r = amdgpu_ttm_bind(bo, new_mem);
> +   if (r)
> +   return r;
> +   }
>
> new_mm = new_mem->mm_node;
> -   r = amdgpu_mm_node_addr(bo, new_mm, new_mem, _start);
> -   if (r)
> -   return r;
> new_size = new_mm->size;
> +   new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
>
> num_pages = new_mem->num_pages;
> while (num_pages) {
> @@ -331,10 +324,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
>
> old_size -= cur_pages;
> if (!old_size) {
> -   r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
> -   _start);
> -   if (r)
> -   goto error;
> +   old_start = amdgpu_mm_node_addr(bo, ++old_mm, 
> old_mem);
> old_size = old_mm->size;
> } else {
> old_start += cur_pages * PAGE_SIZE;
> @@ -342,11 +332,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
>
> new_size -= cur_pages;
> if (!new_size) {
> -   r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem,
> -   _start);
> -   if (r)
> -   goto error;
> -
> +   new_start = amdgpu_mm_node_addr(bo, ++new_mm, 
> new_mem);
> new_size = new_mm->size;
> } else {
> new_start += cur_pages * PAGE_SIZE;
> @@ -1347,6 +1333,12 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
> return -EINVAL;
> }
>
> +   if (bo->tbo.mem.mem_type == TTM_PL_TT) {
> +   r = amdgpu_ttm_bind(>tbo, >tbo.mem);
> +   if (r)
> +   return r;

Re: [PATCH 09/12] drm/amdgpu: use the GTT windows for BO moves

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This way we don't need to map the full BO at a time any more.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 127 
> +++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |   3 +
>  2 files changed, 111 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index eb0d7d7..247ce21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -47,10 +47,15 @@
>
>  #define DRM_FILE_PAGE_OFFSET (0x1ULL >> PAGE_SHIFT)
>
> +static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
> +struct ttm_mem_reg *mem,
> +unsigned num_pages, uint64_t offset,
> +struct amdgpu_ring *ring,
> +uint64_t *addr);
> +
>  static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
>  static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
>
> -
>  /*
>   * Global memory.
>   */
> @@ -97,6 +102,9 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
> *adev)
> goto error_bo;
> }
>
> +   mutex_init(>mman.gtt_window_lock);
> +   adev->mman.gtt_index = 0;
> +
> ring = adev->mman.buffer_funcs_ring;
> rq = >sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
> r = amd_sched_entity_init(>sched, >mman.entity,
> @@ -123,6 +131,7 @@ static void amdgpu_ttm_global_fini(struct amdgpu_device 
> *adev)
> if (adev->mman.mem_global_referenced) {
> amd_sched_entity_fini(adev->mman.entity.sched,
>   >mman.entity);
> +   mutex_destroy(>mman.gtt_window_lock);
> drm_global_item_unref(>mman.bo_global_ref.ref);
> drm_global_item_unref(>mman.mem_global_ref);
> adev->mman.mem_global_referenced = false;
> @@ -256,10 +265,12 @@ static uint64_t amdgpu_mm_node_addr(struct 
> ttm_buffer_object *bo,
> struct drm_mm_node *mm_node,
> struct ttm_mem_reg *mem)
>  {
> -   uint64_t addr;
> +   uint64_t addr = 0;
>
> -   addr = mm_node->start << PAGE_SHIFT;
> -   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
> +   addr = mm_node->start << PAGE_SHIFT;
> +   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   }
> return addr;
>  }
>
> @@ -284,34 +295,41 @@ static int amdgpu_move_blit(struct ttm_buffer_object 
> *bo,
> return -EINVAL;
> }
>
> -   if (old_mem->mem_type == TTM_PL_TT) {
> -   r = amdgpu_ttm_bind(bo, old_mem);
> -   if (r)
> -   return r;
> -   }
> -
> old_mm = old_mem->mm_node;
> old_size = old_mm->size;
> old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
>
> -   if (new_mem->mem_type == TTM_PL_TT) {
> -   r = amdgpu_ttm_bind(bo, new_mem);
> -   if (r)
> -   return r;
> -   }
> -
> new_mm = new_mem->mm_node;
> new_size = new_mm->size;
> new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
>
> num_pages = new_mem->num_pages;
> +   mutex_lock(>mman.gtt_window_lock);
> while (num_pages) {
> -   unsigned long cur_pages = min(old_size, new_size);
> +   unsigned long cur_pages = min(min(old_size, new_size),
> + 
> (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
> +   uint64_t from = old_start, to = new_start;
> struct dma_fence *next;
>
> -   r = amdgpu_copy_buffer(ring, old_start, new_start,
> +   if (old_mem->mem_type == TTM_PL_TT &&
> +   !amdgpu_gtt_mgr_is_alloced(old_mem)) {
> +   r = amdgpu_map_buffer(bo, old_mem, cur_pages,
> + old_start, ring, );
> +   if (r)
> +   goto error;
> +   }
> +
> +   if (new_mem->mem_type == TTM_PL_TT &a

Re: [PATCH 10/12] drm/amdgpu: stop mapping BOs to GTT

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> No need to map BOs to GTT on eviction and intermediate transfers any more.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 19 ++-
>  1 file changed, 2 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 247ce21..e1ebcba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -200,7 +200,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> .lpfn = 0,
> .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
> };
> -   unsigned i;
>
> if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
> placement->placement = 
> @@ -218,20 +217,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> amdgpu_ttm_placement_from_domain(abo, 
> AMDGPU_GEM_DOMAIN_CPU);
> } else {
> amdgpu_ttm_placement_from_domain(abo, 
> AMDGPU_GEM_DOMAIN_GTT);
> -   for (i = 0; i < abo->placement.num_placement; ++i) {
> -   if (!(abo->placements[i].flags &
> - TTM_PL_FLAG_TT))
> -   continue;
> -
> -   if (abo->placements[i].lpfn)
> -   continue;
> -
> -   /* set an upper limit to force directly
> -* allocating address space for the BO.
> -*/
> -   abo->placements[i].lpfn =
> -   adev->mc.gtt_size >> PAGE_SHIFT;
> -   }
> }
> break;
> case TTM_PL_TT:
> @@ -391,7 +376,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object 
> *bo,
> placement.num_busy_placement = 1;
> placement.busy_placement = 
> placements.fpfn = 0;
> -   placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
> +   placements.lpfn = 0;
> placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
> r = ttm_bo_mem_space(bo, , _mem,
>  interruptible, no_wait_gpu);
> @@ -438,7 +423,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object 
> *bo,
> placement.num_busy_placement = 1;
> placement.busy_placement = 
> placements.fpfn = 0;
> -   placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
> +   placements.lpfn = 0;
> placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
> r = ttm_bo_mem_space(bo, , _mem,
>  interruptible, no_wait_gpu);
> --
> 2.7.4
>
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Re: [PATCH 11/12] drm/amdgpu: remove maximum BO size limitation.

[Alex Deucher]

On Fri, Jun 30, 2017 at 7:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> We can finally remove this now.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Woot!
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 ---
>  1 file changed, 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 96c4493..2382785 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -58,17 +58,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
> unsigned long size,
> alignment = PAGE_SIZE;
> }
>
> -   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS 
> | AMDGPU_GEM_DOMAIN_OA))) {
> -   /* Maximum bo size is the unpinned gtt size since we use the 
> gtt to
> -* handle vram to system pool migrations.
> -*/
> -   max_size = adev->mc.gtt_size - adev->gart_pin_size;
> -   if (size > max_size) {
> -   DRM_DEBUG("Allocation size %ldMb bigger than %ldMb 
> limit\n",
> - size >> 20, max_size >> 20);
> -   return -ENOMEM;
> -   }
> -   }
>  retry:
> r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
>  flags, NULL, NULL, );
> --
> 2.7.4
>
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[PATCH 3/5] drm/amdgpu/atombios: add function for whether we need asic_init

[Alex Deucher]

Check the atom scratch registers to see if asic_init is complete
or not.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 10 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |  1 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 8e7a7b9..ce44358 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1756,6 +1756,16 @@ void amdgpu_atombios_scratch_regs_engine_hung(struct 
amdgpu_device *adev,
WREG32(adev->bios_scratch_reg_offset + 3, tmp);
 }
 
+bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
+{
+   u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
+
+   if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
+   return false;
+   else
+   return true;
+}
+
 /* Atom needs data in little endian format
  * so swap as appropriate when copying data to
  * or from atom. Note that atom operates on
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
index 38d0fe3..b0d5d1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
@@ -200,6 +200,7 @@ void amdgpu_atombios_scratch_regs_save(struct amdgpu_device 
*adev);
 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
  bool hung);
+bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
 
 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
-- 
2.5.5

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[PATCH 1/5] drm/amdgpu/atombios: use bios_scratch_reg_offset for atombios

[Alex Deucher]

Align with the atomfirmware code.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 1e8e112..8e7a7b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1686,7 +1686,7 @@ void amdgpu_atombios_scratch_regs_lock(struct 
amdgpu_device *adev, bool lock)
 {
uint32_t bios_6_scratch;
 
-   bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
+   bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
 
if (lock) {
bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
@@ -1696,15 +1696,17 @@ void amdgpu_atombios_scratch_regs_lock(struct 
amdgpu_device *adev, bool lock)
bios_6_scratch |= ATOM_S6_ACC_MODE;
}
 
-   WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
+   WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
 }
 
 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
 {
uint32_t bios_2_scratch, bios_6_scratch;
 
-   bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
-   bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
+   adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
+
+   bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
+   bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
 
/* let the bios control the backlight */
bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
@@ -1715,8 +1717,8 @@ void amdgpu_atombios_scratch_regs_init(struct 
amdgpu_device *adev)
/* clear the vbios dpms state */
bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
 
-   WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
-   WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
+   WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
+   WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
 }
 
 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
@@ -1724,7 +1726,7 @@ void amdgpu_atombios_scratch_regs_save(struct 
amdgpu_device *adev)
int i;
 
for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
-   adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
+   adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + 
i);
 }
 
 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
@@ -1738,20 +1740,20 @@ void amdgpu_atombios_scratch_regs_restore(struct 
amdgpu_device *adev)
adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;
 
for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
-   WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
+   WREG32(adev->bios_scratch_reg_offset + i, 
adev->bios_scratch[i]);
 }
 
 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
  bool hung)
 {
-   u32 tmp = RREG32(mmBIOS_SCRATCH_3);
+   u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
 
if (hung)
tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
else
tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
 
-   WREG32(mmBIOS_SCRATCH_3, tmp);
+   WREG32(adev->bios_scratch_reg_offset + 3, tmp);
 }
 
 /* Atom needs data in little endian format
-- 
2.5.5

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[PATCH 4/5] drm/amdgpu: check scratch registers to see if we need post

[Alex Deucher]

Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 63f4bed..9d08f53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -716,20 +716,12 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc)
  */
 bool amdgpu_need_post(struct amdgpu_device *adev)
 {
-   uint32_t reg;
-
if (adev->has_hw_reset) {
adev->has_hw_reset = false;
return true;
}
-   /* then check MEM_SIZE, in case the crtcs are off */
-   reg = amdgpu_asic_get_config_memsize(adev);
-
-   if ((reg != 0) && (reg != 0x))
-   return false;
-
-   return true;
 
+   return amdgpu_atombios_scratch_need_asic_init(adev);
 }
 
 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
-- 
2.5.5

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[PATCH 2/5] drm/amdgpu: unify some atombios/atomfirmware scratch reg functions

[Alex Deucher]

Now that we use a pointer to the scratch reg start offset,
most of the functions were duplicated.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 35 
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h |  4 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 20 +++---
 drivers/gpu/drm/amd/amdgpu/soc15.c   |  6 ++--
 4 files changed, 7 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 4bdda56..9ddfe34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -66,41 +66,6 @@ void amdgpu_atomfirmware_scratch_regs_init(struct 
amdgpu_device *adev)
}
 }
 
-void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev)
-{
-   int i;
-
-   for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
-   adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + 
i);
-}
-
-void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev)
-{
-   int i;
-
-   /*
-* VBIOS will check ASIC_INIT_COMPLETE bit to decide if
-* execute ASIC_Init posting via driver
-*/
-   adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;
-
-   for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
-   WREG32(adev->bios_scratch_reg_offset + i, 
adev->bios_scratch[i]);
-}
-
-void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,
- bool hung)
-{
-   u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
-
-   if (hung)
-   tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-   else
-   tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-
-   WREG32(adev->bios_scratch_reg_offset + 3, tmp);
-}
-
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 {
struct atom_context *ctx = adev->mode_info.atom_context;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index a2c3ebe..907e48f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -26,10 +26,6 @@
 
 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device 
*adev);
 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
-void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev);
-void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev);
-void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,
- bool hung);
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5b1220f..63f4bed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2438,10 +2438,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
 */
amdgpu_bo_evict_vram(adev);
 
-   if (adev->is_atom_fw)
-   amdgpu_atomfirmware_scratch_regs_save(adev);
-   else
-   amdgpu_atombios_scratch_regs_save(adev);
+   amdgpu_atombios_scratch_regs_save(adev);
pci_save_state(dev->pdev);
if (suspend) {
/* Shut down the device */
@@ -2490,10 +2487,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
if (r)
goto unlock;
}
-   if (adev->is_atom_fw)
-   amdgpu_atomfirmware_scratch_regs_restore(adev);
-   else
-   amdgpu_atombios_scratch_regs_restore(adev);
+   amdgpu_atombios_scratch_regs_restore(adev);
 
/* post card */
if (amdgpu_need_post(adev)) {
@@ -2926,15 +2920,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
r = amdgpu_suspend(adev);
 
 retry:
-   if (adev->is_atom_fw)
-   amdgpu_atomfirmware_scratch_regs_save(adev);
-   else
-   amdgpu_atombios_scratch_regs_save(adev);
+   amdgpu_atombios_scratch_regs_save(adev);
r = amdgpu_asic_reset(adev);
-   if (adev->is_atom_fw)
-   amdgpu_atomfirmware_scratch_regs_restore(adev);
-   else
-   amdgpu_atombios_scratch_regs_restore(adev);
+   amdgpu_atombios_scratch_regs_restore(adev);
/* post card */
amdgpu_atom_asic_init(adev->mode_info.atom_context);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 9210126..8a4b76d 100644
--- a/drivers/gpu/d

Re: [PATCH 08/12] drm/amdgpu: disallow foreign BOs for UVD/VCE

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
> From: Christian König 
>
> They don't support VM mode yet.
>
> Signed-off-by: Christian König 
> Reviewed-by: Felix Kuehling 

This could probably be refined since newer asics support VM for MM
engines.  Maybe add a comment to that effect?  I would add a comment
in general either way.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 82131d7..24035e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1343,7 +1343,8 @@ struct amdgpu_bo_va_mapping *
> struct amdgpu_bo_list_entry *lobj;
>
> lobj = >bo_list->array[i];
> -   if (!lobj->bo_va)
> +   if (!lobj->bo_va ||
> +   amdgpu_ttm_adev(lobj->bo_va->bo->tbo.bdev) != 
> parser->adev)
> continue;
>
> list_for_each_entry(mapping, >bo_va->valids, list) {
> --
> 1.9.1
>
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Re: [PATCH 2/2] drm/amdgpu: Don't call amd_powerplay_destroy() if we don't have powerplay

[Alex Deucher]

On Sat, Jul 1, 2017 at 1:13 PM, John Brooks <j...@fastquake.com> wrote:
> amd_powerplay_destroy() expects a handle pointing to a struct pp_instance.
> On chips without PowerPlay, pp_handle points to a struct amdgpu_device. The
> resulting attempt to kfree() fields of the wrong struct ends in fire:
>
> [   91.560405] BUG: unable to handle kernel paging request at ebe00620
> [   91.560414] IP: kfree+0x57/0x160
> [   91.560416] PGD 0
> [   91.560416] P4D 0
>
> [   91.560420] Oops:  [#1] SMP
> [   91.560422] Modules linked in: tun x86_pkg_temp_thermal crc32_pclmul 
> ghash_clmulni_intel efivarfs amdgpu(-) i2c_algo_bit drm_kms_helper 
> syscopyarea sysfillrect sysimgblt fb_sys_fops ttm drm
> [   91.560438] CPU: 6 PID: 3598 Comm: rmmod Not tainted 
> 4.12.0-rc5-drm-next-4.13-ttmpatch+ #1
> [   91.560443] Hardware name: Gigabyte Technology Co., Ltd. 
> Z97X-UD3H-BK/Z97X-UD3H-BK-CF, BIOS F6 06/17/2014
> [   91.560448] task: 8805063d6a00 task.stack: c9000340
> [   91.560451] RIP: 0010:kfree+0x57/0x160
> [   91.560454] RSP: 0018:c90003403cc0 EFLAGS: 00010286
> [   91.560457] RAX: 77ff8000 RBX: 000186a0 RCX: 
> 000180400035
> [   91.560460] RDX: 000180400036 RSI: ea001418e740 RDI: 
> ea00
> [   91.560463] RBP: c90003403cd8 R08: 0639d201 R09: 
> 000180400035
> [   91.560467] R10: ebe00600 R11: 0300 R12: 
> 880500530030
> [   91.560470] R13: a01e70fc R14:  R15: 
> 88050053
> [   91.560473] FS:  7f7e500c3700() GS:88051ed8() 
> knlGS:
> [   91.560478] CS:  0010 DS:  ES:  CR0: 80050033
> [   91.560480] CR2: ebe00620 CR3: 000503103000 CR4: 
> 001406e0
> [   91.560483] DR0:  DR1:  DR2: 
> 
> [   91.560487] DR3:  DR6: fffe0ff0 DR7: 
> 0400
> [   91.560489] Call Trace:
> [   91.560530]  amd_powerplay_destroy+0x1c/0x60 [amdgpu]
> [   91.560558]  amdgpu_pp_late_fini+0x44/0x60 [amdgpu]
> [   91.560575]  amdgpu_fini+0x254/0x490 [amdgpu]
> [   91.560593]  amdgpu_device_fini+0x58/0x1b0 [amdgpu]
> [   91.560610]  amdgpu_driver_unload_kms+0x4f/0xa0 [amdgpu]
> [   91.560622]  drm_dev_unregister+0x3c/0xe0 [drm]
> [   91.560638]  amdgpu_pci_remove+0x19/0x30 [amdgpu]
> [   91.560643]  pci_device_remove+0x39/0xc0
> [   91.560648]  device_release_driver_internal+0x155/0x210
> [   91.560651]  driver_detach+0x38/0x70
> [   91.560655]  bus_remove_driver+0x4c/0xa0
> [   91.560658]  driver_unregister+0x2c/0x40
> [   91.560662]  pci_unregister_driver+0x21/0x90
> [   91.560689]  amdgpu_exit+0x15/0x406 [amdgpu]
> [   91.560694]  SyS_delete_module+0x1a8/0x270
> [   91.560698]  ? exit_to_usermode_loop+0x92/0xa0
> [   91.560702]  entry_SYSCALL_64_fastpath+0x13/0x94
> [   91.560705] RIP: 0033:0x7f7e4fc118e7
> [   91.560708] RSP: 002b:7fff978ca118 EFLAGS: 0206 ORIG_RAX: 
> 00b0
> [   91.560713] RAX: ffda RBX: 55afe21bc200 RCX: 
> 7f7e4fc118e7
> [   91.560716] RDX: 000a RSI: 0800 RDI: 
> 55afe21bc268
> [   91.560719] RBP: 0003 R08:  R09: 
> 1999
> [   91.560722] R10: 0883 R11: 0206 R12: 
> 7fff978c9100
> [   91.560725] R13:  R14:  R15: 
> 55afe21bc200
> [   91.560728] Code: 00 00 00 80 ff 77 00 00 48 bf 00 00 00 00 00 ea ff ff 49 
> 01 da 48 0f 42 05 57 33 bd 00 49 01 c2 49 c1 ea 0c 49 c1 e2 06 49 01 fa <49> 
> 8b 42 20 48 8d 78 ff a8 01 4c 0f 45 d7 49 8b 52 20 48 8d 42
> [   91.560759] RIP: kfree+0x57/0x160 RSP: c90003403cc0
> [   91.560761] CR2: ffffebe00620
> [   91.560765] ---[ end trace 08a9f3cd82223c1d ]---
>
> Fixes: 1c8638024846 (drm/amd/powerplay: refine powerplay interface.)
> Signed-off-by: John Brooks <j...@fastquake.com>

Both patches are:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index 72c03c7..93ffb85 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -209,7 +209,8 @@ static void amdgpu_pp_late_fini(void *handle)
> if (adev->pp_enabled && adev->pm.dpm_enabled)
> amdgpu_pm_sysfs_fini(adev);
>
> -   amd_powerplay_destroy(adev->powerplay.pp_handle);
> +   if (adev->pp_enabled)
> +   amd_powerplay_destroy(adev->powerplay.pp_handle);
>  }
>
>  static int amdgpu_pp_suspend(void *handle)
> --
> 2.7.4
>
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[PATCH 2/2] drm/amdgpu/gfx9: fix driver reload with KIQ

[Alex Deucher]

Drop the KCQ disabling via KIQ.  We disable the MEC shortly
after anyway, so there is no need to wait for all of this.
Doing so seems to leave the MEC in a bad way.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 51 ---
 1 file changed, 51 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2034592..3a0b69b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2502,56 +2502,6 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device 
*adev)
return r;
 }
 
-static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
-{
-   struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
-   uint32_t scratch, tmp = 0;
-   int r, i;
-
-   r = amdgpu_gfx_scratch_get(adev, );
-   if (r) {
-   DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-   return r;
-   }
-   WREG32(scratch, 0xCAFEDEAD);
-
-   r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
-   if (r) {
-   DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-   amdgpu_gfx_scratch_free(adev, scratch);
-   return r;
-   }
-   /* unmap queues */
-   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
-   amdgpu_ring_write(kiq_ring,
- PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
- PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all 
queues */
-   amdgpu_ring_write(kiq_ring, 0);
-   amdgpu_ring_write(kiq_ring, 0);
-   amdgpu_ring_write(kiq_ring, 0);
-   amdgpu_ring_write(kiq_ring, 0);
-   /* write to scratch for completion */
-   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-   amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
-   amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
-   amdgpu_ring_commit(kiq_ring);
-
-   for (i = 0; i < adev->usec_timeout; i++) {
-   tmp = RREG32(scratch);
-   if (tmp == 0xDEADBEEF)
-   break;
-   DRM_UDELAY(1);
-   }
-   if (i >= adev->usec_timeout) {
-   DRM_ERROR("KCQ disable failed (scratch(0x%04X)=0x%08X)\n",
- scratch, tmp);
-   r = -EINVAL;
-   }
-   amdgpu_gfx_scratch_free(adev, scratch);
-
-   return r;
-}
-
 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
@@ -2996,7 +2946,6 @@ static int gfx_v9_0_hw_fini(void *handle)
pr_debug("For SRIOV client, shouldn't do anything.\n");
return 0;
}
-   gfx_v9_0_kiq_kcq_disable(adev);
gfx_v9_0_cp_enable(adev, false);
gfx_v9_0_rlc_stop(adev);
 
-- 
2.5.5

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[PATCH 1/2] drm/amdgpu/gfx8: fix driver reload with KIQ

[Alex Deucher]

Drop the deactivation in KIQ init and drop the KCQ disabling
via KIQ.  We disable the MEC shortly after anyway, so there is
no need to wait for all of this.  Doing so seems to leave the
MEC in a bad way.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 69 +--
 1 file changed, 1 insertion(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 1ca642b..4bb12ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4636,56 +4636,6 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device 
*adev)
return r;
 }
 
-static int gfx_v8_0_kiq_kcq_disable(struct amdgpu_device *adev)
-{
-   struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
-   uint32_t scratch, tmp = 0;
-   int r, i;
-
-   r = amdgpu_gfx_scratch_get(adev, );
-   if (r) {
-   DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-   return r;
-   }
-   WREG32(scratch, 0xCAFEDEAD);
-
-   r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
-   if (r) {
-   DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-   amdgpu_gfx_scratch_free(adev, scratch);
-   return r;
-   }
-   /* unmap queues */
-   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
-   amdgpu_ring_write(kiq_ring,
- PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
- PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all 
queues */
-   amdgpu_ring_write(kiq_ring, 0);
-   amdgpu_ring_write(kiq_ring, 0);
-   amdgpu_ring_write(kiq_ring, 0);
-   amdgpu_ring_write(kiq_ring, 0);
-   /* write to scratch for completion */
-   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-   amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
-   amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
-   amdgpu_ring_commit(kiq_ring);
-
-   for (i = 0; i < adev->usec_timeout; i++) {
-   tmp = RREG32(scratch);
-   if (tmp == 0xDEADBEEF)
-   break;
-   DRM_UDELAY(1);
-   }
-   if (i >= adev->usec_timeout) {
-   DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n",
- scratch, tmp);
-   r = -EINVAL;
-   }
-   amdgpu_gfx_scratch_free(adev, scratch);
-
-   return r;
-}
-
 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
 {
int i, r = 0;
@@ -4891,7 +4841,6 @@ int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
 
 static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
 {
-   int r = 0;
struct amdgpu_device *adev = ring->adev;
struct vi_mqd *mqd = ring->mqd_ptr;
int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
@@ -4908,11 +4857,6 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring 
*ring)
amdgpu_ring_clear_ring(ring);
mutex_lock(>srbm_mutex);
vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-   r = gfx_v8_0_deactivate_hqd(adev, 1);
-   if (r) {
-   dev_err(adev->dev, "failed to deactivate ring %s\n", 
ring->name);
-   goto out_unlock;
-   }
gfx_v8_0_mqd_commit(adev, mqd);
vi_srbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
@@ -4923,11 +4867,6 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring 
*ring)
mutex_lock(>srbm_mutex);
vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v8_0_mqd_init(ring);
-   r = gfx_v8_0_deactivate_hqd(adev, 1);
-   if (r) {
-   dev_err(adev->dev, "failed to deactivate ring %s\n", 
ring->name);
-   goto out_unlock;
-   }
gfx_v8_0_mqd_commit(adev, mqd);
vi_srbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
@@ -4936,12 +4875,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring 
*ring)
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(struct vi_mqd_allocation));
}
 
-   return r;
-
-out_unlock:
-   vi_srbm_select(adev, 0, 0, 0, 0);
-   mutex_unlock(>srbm_mutex);
-   return r;
+   return 0;
 }
 
 static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
@@ -5145,7 +5079,6 @@ static int gfx_v8_0_hw_fini(void *handle)
pr_debug("For SRIOV client, shouldn't do anything.\n");
return 0;
}
-   gfx_v8_0_kiq_kcq_disable(adev);
gfx_v8_0_cp_enable(adev, false);
gfx_v8_

Re: [PATCH] drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.

[Alex Deucher]

On Tue, Jul 4, 2017 at 4:42 AM, Rex Zhu <rex@amd.com> wrote:
> when hw_fini, pp will disable dpm.so remove sysfs before
> disable dpm.
>
> Change-Id: I17114f5c964b870802abbde32544b28eeb6173ab
> Signed-off-by: Rex Zhu <rex@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index f5ae871..6eaeae0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -187,6 +187,9 @@ static int amdgpu_pp_hw_fini(void *handle)
> int ret = 0;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +   if (adev->pp_enabled && adev->pm.dpm_enabled)
> +   amdgpu_pm_sysfs_fini(adev);
> +
> if (adev->powerplay.ip_funcs->hw_fini)
> ret = adev->powerplay.ip_funcs->hw_fini(
> adev->powerplay.pp_handle);
> @@ -205,9 +208,6 @@ static void amdgpu_pp_late_fini(void *handle)
> adev->powerplay.ip_funcs->late_fini(
>   adev->powerplay.pp_handle);
>
> -   if (adev->pp_enabled && adev->pm.dpm_enabled)
> -   amdgpu_pm_sysfs_fini(adev);
> -
> amd_powerplay_destroy(adev->powerplay.pp_handle);
>  }
>
> --
> 1.9.1
>
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[PATCH] drm/amdgpu: check scratch registers to see if we need post (v2)

[Alex Deucher]

Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.

v2: The scratch register is only used on CIK+

Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 63f4bed..8042a8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -722,7 +722,12 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
adev->has_hw_reset = false;
return true;
}
-   /* then check MEM_SIZE, in case the crtcs are off */
+
+   /* bios scratch used on CIK+ */
+   if (adev->asic_type >= CHIP_BONAIRE)
+   return amdgpu_atombios_scratch_need_asic_init(adev);
+
+   /* check MEM_SIZE for older asics */
reg = amdgpu_asic_get_config_memsize(adev);
 
if ((reg != 0) && (reg != 0x))
-- 
2.5.5

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Re: [PATCH][drm-next] drm/amdgpu: make arrays pctl0_data and pctl1_data static

[Alex Deucher]

On Thu, Jul 6, 2017 at 5:58 AM, Colin King  wrote:
> From: Colin Ian King 
>
> The arrays pctl0_data and pctl1_data do not need to be in global scope,
> so them both static.
>
> Cleans up sparse warnings:
> symbol 'pctl0_data' was not declared. Should it be static?
> symbol 'pctl1_data' was not declared. Should it be static?
>
> Signed-off-by: Colin Ian King 


Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 9804318f3488..4c079207d699 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -249,7 +249,7 @@ struct pctl_data {
>  uint32_t data;
>  };
>
> -const struct pctl_data pctl0_data[] = {
> +static const struct pctl_data pctl0_data[] = {
>  {0x0, 0x7a640},
>  {0x9, 0x2a64a},
>  {0xd, 0x2a680},
> @@ -274,7 +274,7 @@ const struct pctl_data pctl0_data[] = {
>  #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE  0xa640
>  #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
>
> -const struct pctl_data pctl1_data[] = {
> +static const struct pctl_data pctl1_data[] = {
>  {0x0, 0x39a000},
>  {0x3b, 0x44a040},
>  {0x81, 0x2a08d},
> --
> 2.11.0
>
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Re: [PATCH 01/11] drm/amdgpu: reserve the first 2x512 of GART

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> We want to use them as remap address space.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

2x512 pages.  With that updated:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 5 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index 1ef6255..f46a97d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -43,12 +43,15 @@ static int amdgpu_gtt_mgr_init(struct 
> ttm_mem_type_manager *man,
>unsigned long p_size)
>  {
> struct amdgpu_gtt_mgr *mgr;
> +   uint64_t start, size;
>
> mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
> if (!mgr)
> return -ENOMEM;
>
> -   drm_mm_init(>mm, 0, p_size);
> +   start = AMDGPU_GTT_MAX_TRANSFER_SIZE * 
> AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
> +   size = p_size - start;
> +   drm_mm_init(>mm, start, size);
> spin_lock_init(>lock);
> mgr->available = p_size;
> man->priv = mgr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 776a20a..c8059f0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -34,6 +34,9 @@
>  #define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
>  #define AMDGPU_PL_FLAG_OA  (TTM_PL_FLAG_PRIV << 2)
>
> +#define AMDGPU_GTT_MAX_TRANSFER_SIZE   512
> +#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS2
> +
>  struct amdgpu_mman {
> struct ttm_bo_global_refbo_global_ref;
> struct drm_global_reference mem_global_ref;
> --
> 2.7.4
>
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Re: [PATCH 02/11] drm/amdgpu: add amdgpu_gart_map function v2

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This allows us to write the mapped PTEs into
> an IB instead of the table directly.
>
> v2: fix build with debugfs enabled, remove unused assignment
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  3 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 62 
> 
>  2 files changed, 51 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 810796a..4a2b33d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -572,6 +572,9 @@ int amdgpu_gart_init(struct amdgpu_device *adev);
>  void amdgpu_gart_fini(struct amdgpu_device *adev);
>  int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
> int pages);
> +int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> +   int pages, dma_addr_t *dma_addr, uint64_t flags,
> +   void *dst);
>  int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
>  int pages, struct page **pagelist,
>  dma_addr_t *dma_addr, uint64_t flags);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 8877015..c808388 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -280,6 +280,41 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, 
> uint64_t offset,
>  }
>
>  /**
> + * amdgpu_gart_map - map dma_addresses into GART entries
> + *
> + * @adev: amdgpu_device pointer
> + * @offset: offset into the GPU's gart aperture
> + * @pages: number of pages to bind
> + * @dma_addr: DMA addresses of pages
> + *
> + * Map the dma_addresses into GART entries (all asics).
> + * Returns 0 for success, -EINVAL for failure.
> + */
> +int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> +   int pages, dma_addr_t *dma_addr, uint64_t flags,
> +   void *dst)
> +{
> +   uint64_t page_base;
> +   unsigned i, j, t;
> +
> +   if (!adev->gart.ready) {
> +   WARN(1, "trying to bind memory to uninitialized GART !\n");
> +   return -EINVAL;
> +   }
> +
> +   t = offset / AMDGPU_GPU_PAGE_SIZE;
> +
> +   for (i = 0; i < pages; i++) {
> +   page_base = dma_addr[i];
> +   for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) 
> {
> +   amdgpu_gart_set_pte_pde(adev, dst, t, page_base, 
> flags);
> +   page_base += AMDGPU_GPU_PAGE_SIZE;
> +   }
> +   }
> +   return 0;
> +}
> +
> +/**
>   * amdgpu_gart_bind - bind pages into the gart page table
>   *
>   * @adev: amdgpu_device pointer
> @@ -296,31 +331,30 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, 
> uint64_t offset,
>  int pages, struct page **pagelist, dma_addr_t *dma_addr,
>  uint64_t flags)
>  {
> -   unsigned t;
> -   unsigned p;
> -   uint64_t page_base;
> -   int i, j;
> +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> +   unsigned i,t,p;
> +#endif
> +   int r;
>
> if (!adev->gart.ready) {
> WARN(1, "trying to bind memory to uninitialized GART !\n");
> return -EINVAL;
> }
>
> +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> t = offset / AMDGPU_GPU_PAGE_SIZE;
> p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
> -
> -   for (i = 0; i < pages; i++, p++) {
> -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> +   for (i = 0; i < pages; i++, p++)
> adev->gart.pages[p] = pagelist[i];
>  #endif
> -   if (adev->gart.ptr) {
> -   page_base = dma_addr[i];
> -   for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 
> j++, t++) {
> -   amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, 
> t, page_base, flags);
> -   page_base += AMDGPU_GPU_PAGE_SIZE;
> -   }
> -   }
> +
> +   if (adev->gart.ptr) {
> +   r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
> +   adev->gart.ptr);
> +   if (r)
> +   return r;
> }
> +
> mb();
> amdgpu_gart_flush_gpu_tlb(adev, 0);
> return 0;
> --
> 2.7.4
>
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Re: [PATCH 03/11] drm/amdgpu: use the GTT windows for BO moves v2

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This way we don't need to map the full BO at a time any more.
>
> v2: use fixed windows for src/dst
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 125 
> +++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |   2 +
>  2 files changed, 108 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 15148f1..1fc9866 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -47,10 +47,15 @@
>
>  #define DRM_FILE_PAGE_OFFSET (0x1ULL >> PAGE_SHIFT)
>
> +static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
> +struct ttm_mem_reg *mem, unsigned num_pages,
> +uint64_t offset, unsigned window,
> +struct amdgpu_ring *ring,
> +uint64_t *addr);
> +
>  static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
>  static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
>
> -
>  /*
>   * Global memory.
>   */
> @@ -97,6 +102,8 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
> *adev)
> goto error_bo;
> }
>
> +   mutex_init(>mman.gtt_window_lock);
> +
> ring = adev->mman.buffer_funcs_ring;
> rq = >sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
> r = amd_sched_entity_init(>sched, >mman.entity,
> @@ -123,6 +130,7 @@ static void amdgpu_ttm_global_fini(struct amdgpu_device 
> *adev)
> if (adev->mman.mem_global_referenced) {
> amd_sched_entity_fini(adev->mman.entity.sched,
>   >mman.entity);
> +   mutex_destroy(>mman.gtt_window_lock);
> drm_global_item_unref(>mman.bo_global_ref.ref);
> drm_global_item_unref(>mman.mem_global_ref);
> adev->mman.mem_global_referenced = false;
> @@ -256,10 +264,13 @@ static uint64_t amdgpu_mm_node_addr(struct 
> ttm_buffer_object *bo,
> struct drm_mm_node *mm_node,
> struct ttm_mem_reg *mem)
>  {
> -   uint64_t addr;
> +   uint64_t addr = 0;
>
> -   addr = mm_node->start << PAGE_SHIFT;
> -   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   if (mem->mem_type != TTM_PL_TT ||
> +   amdgpu_gtt_mgr_is_allocated(mem)) {
> +   addr = mm_node->start << PAGE_SHIFT;
> +   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   }
> return addr;
>  }
>
> @@ -284,34 +295,41 @@ static int amdgpu_move_blit(struct ttm_buffer_object 
> *bo,
> return -EINVAL;
> }
>
> -   if (old_mem->mem_type == TTM_PL_TT) {
> -   r = amdgpu_ttm_bind(bo, old_mem);
> -   if (r)
> -   return r;
> -   }
> -
> old_mm = old_mem->mm_node;
> old_size = old_mm->size;
> old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
>
> -   if (new_mem->mem_type == TTM_PL_TT) {
> -   r = amdgpu_ttm_bind(bo, new_mem);
> -   if (r)
> -   return r;
> -   }
> -
> new_mm = new_mem->mm_node;
> new_size = new_mm->size;
> new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
>
> num_pages = new_mem->num_pages;
> +   mutex_lock(>mman.gtt_window_lock);
> while (num_pages) {
> -   unsigned long cur_pages = min(old_size, new_size);
> +   unsigned long cur_pages = min(min(old_size, new_size),
> + 
> (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
> +   uint64_t from = old_start, to = new_start;
> struct dma_fence *next;
>
> -   r = amdgpu_copy_buffer(ring, old_start, new_start,
> +   if (old_mem->mem_type == TTM_PL_TT &&
> +   !amdgpu_gtt_mgr_is_allocated(old_mem)) {
> +   r = amdgpu_map_buffer(bo, old_mem, cur_pages,
> + old_start, 0, ring, );
> +   if (r)
> +   goto error;
> +   }
>

Re: [PATCH 04/11] drm/amdgpu: stop mapping BOs to GTT

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> No need to map BOs to GTT on eviction and intermediate transfers any more.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 19 ++-
>  1 file changed, 2 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 1fc9866..5c7a6c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -199,7 +199,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> .lpfn = 0,
> .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
> };
> -   unsigned i;
>
> if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
> placement->placement = 
> @@ -217,20 +216,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> amdgpu_ttm_placement_from_domain(abo, 
> AMDGPU_GEM_DOMAIN_CPU);
> } else {
> amdgpu_ttm_placement_from_domain(abo, 
> AMDGPU_GEM_DOMAIN_GTT);
> -   for (i = 0; i < abo->placement.num_placement; ++i) {
> -   if (!(abo->placements[i].flags &
> - TTM_PL_FLAG_TT))
> -   continue;
> -
> -   if (abo->placements[i].lpfn)
> -   continue;
> -
> -   /* set an upper limit to force directly
> -* allocating address space for the BO.
> -*/
> -   abo->placements[i].lpfn =
> -   adev->mc.gtt_size >> PAGE_SHIFT;
> -   }
> }
> break;
> case TTM_PL_TT:
> @@ -391,7 +376,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object 
> *bo,
> placement.num_busy_placement = 1;
> placement.busy_placement = 
> placements.fpfn = 0;
> -   placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
> +   placements.lpfn = 0;
> placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
> r = ttm_bo_mem_space(bo, , _mem,
>  interruptible, no_wait_gpu);
> @@ -438,7 +423,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object 
> *bo,
> placement.num_busy_placement = 1;
> placement.busy_placement = 
> placements.fpfn = 0;
> -   placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
> +   placements.lpfn = 0;
> placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
> r = ttm_bo_mem_space(bo, , _mem,
>  interruptible, no_wait_gpu);
> --
> 2.7.4
>
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Re: [PATCH 05/11] drm/amdgpu: remove maximum BO size limitation v2

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> We can finally remove this now.
>
> v2: remove now unused max_size variable as well.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 12 
>  1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 96c4493..917ac5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -49,7 +49,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
> unsigned long size,
> struct drm_gem_object **obj)
>  {
> struct amdgpu_bo *robj;
> -   unsigned long max_size;
> int r;
>
> *obj = NULL;
> @@ -58,17 +57,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
> unsigned long size,
> alignment = PAGE_SIZE;
> }
>
> -   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS 
> | AMDGPU_GEM_DOMAIN_OA))) {
> -   /* Maximum bo size is the unpinned gtt size since we use the 
> gtt to
> -* handle vram to system pool migrations.
> -*/
> -   max_size = adev->mc.gtt_size - adev->gart_pin_size;
> -   if (size > max_size) {
> -   DRM_DEBUG("Allocation size %ldMb bigger than %ldMb 
> limit\n",
> - size >> 20, max_size >> 20);
> -   return -ENOMEM;
> -   }
> -   }
>  retry:
> r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
>  flags, NULL, NULL, );
> --
> 2.7.4
>
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Re: [PATCH 06/11] drm/amdgpu: use TTM values instead of MC values for the info queries

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> Use the TTM values instead of the hardware config here.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 00ef2fc..7a8da32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -484,7 +484,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file
> vram_gtt.vram_size -= adev->vram_pin_size;
> vram_gtt.vram_cpu_accessible_size = 
> adev->mc.visible_vram_size;
> vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
> adev->invisible_pin_size);
> -   vram_gtt.gtt_size  = adev->mc.gtt_size;
> +   vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
> +   vram_gtt.gtt_size *= PAGE_SIZE;
> vram_gtt.gtt_size -= adev->gart_pin_size;
> return copy_to_user(out, _gtt,
> min((size_t)size, sizeof(vram_gtt))) ? 
> -EFAULT : 0;
> @@ -509,9 +510,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, 
> void *data, struct drm_file
> mem.cpu_accessible_vram.max_allocation =
> mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
>
> -   mem.gtt.total_heap_size = adev->mc.gtt_size;
> -   mem.gtt.usable_heap_size =
> -   adev->mc.gtt_size - adev->gart_pin_size;
> +   mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
> +   mem.gtt.total_heap_size *= PAGE_SIZE;
> +   mem.gtt.usable_heap_size = mem.gtt.total_heap_size
> +   - adev->gart_pin_size;
> mem.gtt.heap_usage = atomic64_read(>gtt_usage);
> mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
>
> --
> 2.7.4
>
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Re: [PATCH 08/11] drm/amdgpu: move SYSVM struct and function into amdgpu_sysvm.h

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> No functional change.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

I agree with what the patch does, but I'd prefer gart to sysvm for the naming.
Acked-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 48 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h | 77 
> +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  1 +
>  3 files changed, 79 insertions(+), 47 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index abe191f..a2c0eac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -69,6 +69,7 @@
>
>  #include "gpu_scheduler.h"
>  #include "amdgpu_virt.h"
> +#include "amdgpu_sysvm.h"
>
>  /*
>   * Modules parameters.
> @@ -534,53 +535,6 @@ int amdgpu_fence_slab_init(void);
>  void amdgpu_fence_slab_fini(void);
>
>  /*
> - * GART structures, functions & helpers
> - */
> -struct amdgpu_mc;
> -
> -#define AMDGPU_GPU_PAGE_SIZE 4096
> -#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
> -#define AMDGPU_GPU_PAGE_SHIFT 12
> -#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & 
> ~AMDGPU_GPU_PAGE_MASK)
> -
> -struct amdgpu_sysvm {
> -   dma_addr_t  table_addr;
> -   struct amdgpu_bo*robj;
> -   void*ptr;
> -   unsignednum_gpu_pages;
> -   unsignednum_cpu_pages;
> -   unsignedtable_size;
> -#ifdef CONFIG_DRM_AMDGPU_SYSVM_DEBUGFS
> -   struct page **pages;
> -#endif
> -   boolready;
> -
> -   /* Asic default pte flags */
> -   uint64_tsysvm_pte_flags;
> -
> -   const struct amdgpu_sysvm_funcs *sysvm_funcs;
> -};
> -
> -void amdgpu_sysvm_set_defaults(struct amdgpu_device *adev);
> -int amdgpu_sysvm_table_ram_alloc(struct amdgpu_device *adev);
> -void amdgpu_sysvm_table_ram_free(struct amdgpu_device *adev);
> -int amdgpu_sysvm_table_vram_alloc(struct amdgpu_device *adev);
> -void amdgpu_sysvm_table_vram_free(struct amdgpu_device *adev);
> -int amdgpu_sysvm_table_vram_pin(struct amdgpu_device *adev);
> -void amdgpu_sysvm_table_vram_unpin(struct amdgpu_device *adev);
> -int amdgpu_sysvm_init(struct amdgpu_device *adev);
> -void amdgpu_sysvm_fini(struct amdgpu_device *adev);
> -int amdgpu_sysvm_unbind(struct amdgpu_device *adev, uint64_t offset,
> -   int pages);
> -int amdgpu_sysvm_map(struct amdgpu_device *adev, uint64_t offset,
> -   int pages, dma_addr_t *dma_addr, uint64_t flags,
> -   void *dst);
> -int amdgpu_sysvm_bind(struct amdgpu_device *adev, uint64_t offset,
> -int pages, struct page **pagelist,
> -dma_addr_t *dma_addr, uint64_t flags);
> -int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
> -
> -/*
>   * VMHUB structures, functions & helpers
>   */
>  struct amdgpu_vmhub {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h
> new file mode 100644
> index 000..7846765
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h
> @@ -0,0 +1,77 @@
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTR

Re: [PATCH 10/11] drm/amdgpu: setup GTT size directly from module parameter

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> Instead of relying on the sysvm_size to be the same as the module parameter.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 9240357..72dd83e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1097,6 +1097,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
>
>  int amdgpu_ttm_init(struct amdgpu_device *adev)
>  {
> +   uint64_t gtt_size;
> int r;
>
> r = amdgpu_ttm_global_init(adev);
> @@ -1143,14 +1144,19 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
> }
> DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
>  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
> -   r = ttm_bo_init_mm(>mman.bdev, TTM_PL_TT,
> -   adev->mc.sysvm_size >> PAGE_SHIFT);
> +
> +   if (amdgpu_gart_size == -1)
> +   gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
> +  adev->mc.mc_vram_size);
> +   else
> +   gtt_size = (uint64_t)amdgpu_gart_size << 20;
> +   r = ttm_bo_init_mm(>mman.bdev, TTM_PL_TT, gtt_size >> 
> PAGE_SHIFT);
> if (r) {
> DRM_ERROR("Failed initializing GTT heap.\n");
> return r;
> }
> DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
> -(unsigned)(adev->mc.sysvm_size / (1024 * 1024)));
> +(unsigned)(gtt_size / (1024 * 1024)));
>
> adev->gds.mem.total_size = adev->gds.mem.total_size << 
> AMDGPU_GDS_SHIFT;
> adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size 
> << AMDGPU_GDS_SHIFT;
> --
> 2.7.4
>
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Re: [PATCH 09/11] drm/amdgpu: move amdgpu_sysvm_location into amdgpu_sysvm.c as well

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> No intended functional change.
>
> Signed-off-by: Christian König 

I think I'd prefer to keep this together with the vram_location
function.  Maybe move both of them?

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 36 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c  | 38 
> ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h  |  2 ++
>  4 files changed, 40 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a2c0eac..1ed6b7a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1862,7 +1862,6 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
>  uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt 
> *ttm,
>  struct ttm_mem_reg *mem);
>  void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, 
> u64 base);
> -void amdgpu_sysvm_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
>  void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
>  int amdgpu_ttm_init(struct amdgpu_device *adev);
>  void amdgpu_ttm_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 46a82d3..228b262 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -666,42 +666,6 @@ void amdgpu_vram_location(struct amdgpu_device *adev, 
> struct amdgpu_mc *mc, u64
> mc->vram_end, mc->real_vram_size >> 20);
>  }
>
> -/**
> - * amdgpu_sysvm_location - try to find SYSVM location
> - * @adev: amdgpu device structure holding all necessary informations
> - * @mc: memory controller structure holding memory informations
> - *
> - * Function will place try to place SYSVM before or after VRAM.
> - *
> - * If SYSVM size is bigger than space left then we ajust SYSVM size.
> - * Thus function will never fails.
> - *
> - * FIXME: when reducing SYSVM size align new size on power of 2.
> - */
> -void amdgpu_sysvm_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
> -{
> -   u64 size_af, size_bf;
> -
> -   size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->sysvm_base_align) 
> & ~mc->sysvm_base_align;
> -   size_bf = mc->vram_start & ~mc->sysvm_base_align;
> -   if (size_bf > size_af) {
> -   if (mc->sysvm_size > size_bf) {
> -   dev_warn(adev->dev, "limiting SYSVM\n");
> -   mc->sysvm_size = size_bf;
> -   }
> -   mc->sysvm_start = 0;
> -   } else {
> -   if (mc->sysvm_size > size_af) {
> -   dev_warn(adev->dev, "limiting SYSVM\n");
> -   mc->sysvm_size = size_af;
> -   }
> -   mc->sysvm_start = (mc->vram_end + 1 + mc->sysvm_base_align) & 
> ~mc->sysvm_base_align;
> -   }
> -   mc->sysvm_end = mc->sysvm_start + mc->sysvm_size - 1;
> -   dev_info(adev->dev, "SYSVM: %lluM 0x%016llX - 0x%016llX\n",
> -   mc->sysvm_size >> 20, mc->sysvm_start, mc->sysvm_end);
> -}
> -
>  /*
>   * GPU helpers function.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> index 50fc8d7..ff436ad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> @@ -73,6 +73,44 @@ void amdgpu_sysvm_set_defaults(struct amdgpu_device *adev)
>  }
>
>  /**
> + * amdgpu_sysvm_location - try to find SYSVM location
> + * @adev: amdgpu device structure holding all necessary informations
> + * @mc: memory controller structure holding memory informations
> + *
> + * Function will place try to place SYSVM before or after VRAM.
> + *
> + * If SYSVM size is bigger than space left then we ajust SYSVM size.
> + * Thus function will never fails.
> + *
> + * FIXME: when reducing SYSVM size align new size on power of 2.
> + */
> +void amdgpu_sysvm_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
> +{
> +   u64 size_af, size_bf;
> +
> +   size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->sysvm_base_align) &
> +   ~mc->sysvm_base_align;
> +   size_bf = mc->vram_start & ~mc->sysvm_base_align;
> +   if (size_bf > size_af) {
> +   if (mc->sysvm_size > size_bf) {
> +   dev_warn(adev->dev, "limiting SYSVM\n");
> +   mc->sysvm_size = size_bf;
> +   }
> +   mc->sysvm_start = 0;
> +   } else {
> +   if (mc->sysvm_size > size_af) {
> +   dev_warn(adev->dev, "limiting SYSVM\n");

Re: [PATCH 11/11] drm/amdgpu: add sysvm_size

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> Limit the size of the SYSVM. This saves us a bunch of visible VRAM,
> but also limitates the maximum BO size we can swap out.

Update the description.  The limitation is removed now.

>
> v2: rebased and cleaned up after GART to SYSVM rename.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 6 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c   | 9 +
>  5 files changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1ed6b7a..81de31a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -77,6 +77,7 @@
>  extern int amdgpu_modeset;
>  extern int amdgpu_vram_limit;
>  extern int amdgpu_gart_size;
> +extern unsigned amdgpu_sysvm_size;
>  extern int amdgpu_moverate;
>  extern int amdgpu_benchmarking;
>  extern int amdgpu_testing;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 228b262..daded9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1086,6 +1086,12 @@ static void amdgpu_check_arguments(struct 
> amdgpu_device *adev)
> }
> }
>
> +   if (amdgpu_sysvm_size < 32) {
> +   dev_warn(adev->dev, "sysvm size (%d) too small\n",
> +amdgpu_sysvm_size);
> +   amdgpu_sysvm_size = 32;
> +   }
> +
> amdgpu_check_vm_size(adev);
>
> amdgpu_check_block_size(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 4bf4a80..56f9867 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -75,6 +75,7 @@
>
>  int amdgpu_vram_limit = 0;
>  int amdgpu_gart_size = -1; /* auto */
> +unsigned amdgpu_sysvm_size = 256;
>  int amdgpu_moverate = -1; /* auto */
>  int amdgpu_benchmarking = 0;
>  int amdgpu_testing = 0;
> @@ -124,6 +125,9 @@ module_param_named(vramlimit, amdgpu_vram_limit, int, 
> 0600);
>  MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 
> 64, etc., -1 = auto)");
>  module_param_named(gartsize, amdgpu_gart_size, int, 0600);
>
> +MODULE_PARM_DESC(sysvmsize, "Size of the system VM in megabytes (default 
> 256)");
> +module_param_named(sysvmsize, amdgpu_sysvm_size, int, 0600);
> +
>  MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
> etc., -1=auto, 0=1=disabled)");
>  module_param_named(moverate, amdgpu_moverate, int, 0600);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index f46a97d..bbf6bd0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -42,6 +42,7 @@ struct amdgpu_gtt_mgr {
>  static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
>unsigned long p_size)
>  {
> +   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> struct amdgpu_gtt_mgr *mgr;
> uint64_t start, size;
>
> @@ -50,7 +51,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
> *man,
> return -ENOMEM;
>
> start = AMDGPU_GTT_MAX_TRANSFER_SIZE * 
> AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
> -   size = p_size - start;
> +   size = (adev->mc.sysvm_size >> PAGE_SHIFT) - start;
> drm_mm_init(>mm, start, size);
> spin_lock_init(>lock);
> mgr->available = p_size;
> @@ -112,6 +113,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
>  const struct ttm_place *place,
>  struct ttm_mem_reg *mem)
>  {
> +   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> struct amdgpu_gtt_mgr *mgr = man->priv;
> struct drm_mm_node *node = mem->mm_node;
> enum drm_mm_insert_mode mode;
> @@ -129,7 +131,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
> if (place && place->lpfn)
> lpfn = place->lpfn;
>

Re: [PATCH xf86-video-amdgpu] Only call drmmode_scanout_free for non-GPU screens in LeaveVT

[Alex Deucher]

On Tue, Jun 27, 2017 at 5:18 AM, Michel Dänzer <mic...@daenzer.net> wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> Destroying the scanout buffers of GPU screens resulted in a crash when
> switching back to the Xorg VT.
>
> Fixes: b10ecdbd89b0 ("Use drmmode_crtc_scanout_* helpers for RandR 1.4
>   scanout pixmaps")
> (Ported from radeon commit c9dd28cb0c9c3de676eadac61e727732510f6b9b)
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  src/amdgpu_kms.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 143294a9f..b625250fd 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -1975,7 +1975,8 @@ void AMDGPULeaveVT_KMS(VT_FUNC_ARGS_DECL)
> amdgpu_drop_drm_master(pScrn);
>
> xf86RotateFreeShadow(pScrn);
> -   drmmode_scanout_free(pScrn);
> +   if (!pScrn->is_gpu)
> +   drmmode_scanout_free(pScrn);
>
> xf86_hide_cursors(pScrn);
>
> --
> 2.13.1
>
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Re: [PATCH xf86-video-ati 2/2] Improve drmmode_fb_reference debugging code

[Alex Deucher]

On Tue, Jun 27, 2017 at 5:38 AM, Michel Dänzer <mic...@daenzer.net> wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> If a reference count is <= 0, call FatalError with the call location
> (in case it doesn't get resolved in the backtrace printed by
> FatalError).
>
> (Ported from amdgpu commit 1b6ff5fd9933c00ec1ec90dfc62e0b531927749b)
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  src/drmmode_display.h | 29 ++---
>  1 file changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/src/drmmode_display.h b/src/drmmode_display.h
> index db68054a7..dde27a009 100644
> --- a/src/drmmode_display.h
> +++ b/src/drmmode_display.h
> @@ -141,29 +141,36 @@ enum drmmode_flip_sync {
>
>
>  static inline void
> -drmmode_fb_reference(int drm_fd, struct drmmode_fb **old, struct drmmode_fb 
> *new)
> +drmmode_fb_reference_loc(int drm_fd, struct drmmode_fb **old, struct 
> drmmode_fb *new,
> +const char *caller, unsigned line)
>  {
>  if (new) {
> -   if (new->refcnt <= 0)
> -   ErrorF("New FB's refcnt was %d in %s\n", new->refcnt, __func__);
> -   else
> -   new->refcnt++;
> +   if (new->refcnt <= 0) {
> +   FatalError("New FB's refcnt was %d at %s:%u",
> +  new->refcnt, caller, line);
> +   }
> +
> +   new->refcnt++;
>  }
>
>  if (*old) {
> if ((*old)->refcnt <= 0) {
> -   ErrorF("Old FB's refcnt was %d in %s\n", (*old)->refcnt, 
> __func__);
> -   } else {
> -   if (--(*old)->refcnt == 0) {
> -   drmModeRmFB(drm_fd, (*old)->handle);
> -   free(*old);
> -   }
> +   FatalError("Old FB's refcnt was %d at %s:%u",
> +  (*old)->refcnt, caller, line);
> +   }
> +
> +   if (--(*old)->refcnt == 0) {
> +   drmModeRmFB(drm_fd, (*old)->handle);
> +   free(*old);
> }
>  }
>
>  *old = new;
>  }
>
> +#define drmmode_fb_reference(fd, old, new) \
> +drmmode_fb_reference_loc(fd, old, new, __func__, __LINE__)
> +
>
>  extern int drmmode_page_flip_target_absolute(RADEONEntPtr pRADEONEnt,
>  drmmode_crtc_private_ptr 
> drmmode_crtc,
> --
> 2.13.1
>
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Re: [gpu-drm-radeon] question about potential dead code in vce_v2_0_enable_mgcg()

[Alex Deucher]

On Wed, Jun 28, 2017 at 7:08 PM, Gustavo A. R. Silva
 wrote:
> Hi Alex,
>
> Quoting "Deucher, Alexander" :
>
>>> -Original Message-
>>> From: Gustavo A. R. Silva [mailto:garsi...@embeddedor.com]
>>> Sent: Wednesday, June 28, 2017 10:22 AM
>>> To: Deucher, Alexander; Koenig, Christian; David Airlie
>>> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>>> linux-
>>> ker...@vger.kernel.org
>>> Subject: [gpu-drm-radeon] question about potential dead code in
>>> vce_v2_0_enable_mgcg()
>>>
>>>
>>> Hello everybody,
>>>
>>> While looking into Coverity ID 1198635 I ran into the following piece
>>> of code at drivers/gpu/drm/radeon/vce_v2_0.c:107:
>>>
>>> 107void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
>>> 108{
>>> 109bool sw_cg = false;
>>> 110
>>> 111if (enable && (rdev->cg_flags &
>>> RADEON_CG_SUPPORT_VCE_MGCG)) {
>>> 112if (sw_cg)
>>> 113vce_v2_0_set_sw_cg(rdev, true);
>>> 114else
>>> 115vce_v2_0_set_dyn_cg(rdev, true);
>>> 116} else {
>>> 117vce_v2_0_disable_cg(rdev);
>>> 118
>>> 119if (sw_cg)
>>> 120vce_v2_0_set_sw_cg(rdev, false);
>>> 121else
>>> 122vce_v2_0_set_dyn_cg(rdev, false);
>>> 123}
>>> 124}
>>>
>>> The issue here is that local variable sw_cg is never updated again
>>> after its initialization; which cause some code to be logically dead.
>>>
>>> My question here is if such variable is there for testing purposes or
>>> if it is a sort of an old code leftover that should be removed?
>>>
>>> In any case I can send a patch to add a comment or remove the dead code.
>>>
>>> I'd really appreciate any comments on this.
>>
>>
>> I wanted to leave the code in for debugging if we ran into problems with
>> dynamic clockgating.
>>
>
> Do you mind if I send a patch to add such comment and make it clear the
> purpose of that variable?

Sure.  Thanks.

Alex

>
> --- a/drivers/gpu/drm/radeon/vce_v2_0.c
> +++ b/drivers/gpu/drm/radeon/vce_v2_0.c
> @@ -104,6 +104,10 @@ static void vce_v2_0_disable_cg(struct radeon_device
> *rdev)
> WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
>  }
>
> +/*
> + * Local variable sw_cg is used for debugging purposes, in case we
> + * ran into problems with dynamic clock gating. Don't remove it.
> + */
>  void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
>  {
> bool sw_cg = false;
>
>
> Thanks for clarifying!
> --
> Gustavo A. R. Silva
>
>
>
>
>
>
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[pull] amdgpu drm-next-4.13

[Alex Deucher]

Hi Dave,

Fixes for 4.13:
- Various fixes for Raven
- Various fixes for Vega10
- Stability fixes for KIQ
- Fix reloading the driver
- Fix S3 on vega10
- Misc other fixes

The following changes since commit 12d016626f99f48edbf5b006625b4e8c0de1eec7:

  Merge tag 'drm-amdkfd-next-2017-06-25' of 
git://people.freedesktop.org/~gabbayo/linux into drm-next (2017-06-28 17:09:27 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.13

for you to fetch changes up to 593f546eee2fdbe055380ee82de568c0a1775551:

  drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu. 
(2017-07-05 13:18:50 -0400)


Alex Deucher (6):
  drm/amd/powerplay/cz: print message if smc message fails
  drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup
  drm/amdgpu: fix vblank_time when displays are off
  drm/amdgpu/cgs: always set reference clock in mode_info
  drm/amdgpu/gfx8: fix driver reload with KIQ
  drm/amdgpu/gfx9: fix driver reload with KIQ

Alex Xie (2):
  drm/amdgpu/cs: fix a typo in a comment
  drm/amdgpu: Make amdgpu_cs_parser_init static (v2)

Arnd Bergmann (1):
  drm/amdgpu: fix typo in amdgpu_debugfs_test_ib_init

Eric Huang (2):
  drm/amd/powerplay: change PPSMC_MSG_GetCurrPkgPwr for Vega10
  drm/amd/powerplay: power value format change for Vega10

Flora Cui (1):
  drm/amdgpu: Fix the exported always on CU bitmap

Hawking Zhang (4):
  drm/amdgpu: add mmhub pg init sequence on raven
  drm/amdgpu: add interface to enable/disable mmhub pg on raven
  drm/amdgpu: add new flag AMD_PG_SUPPORT_MMHUB
  drm/amdgpu: enable mmhub pg on raven

Huang Rui (1):
  drm/amdgpu: fix the memory corruption on S3

Jim Qu (1):
  drm/amd/amdgpu: move get memory type function from early init to sw init

John Brooks (2):
  drm/ttm: Fix use-after-free in ttm_bo_clean_mm
  drm/amdgpu: Don't call amd_powerplay_destroy() if we don't have powerplay

Michel Dänzer (1):
  amdgpu: Set cik/si_support to 1 by default if radeon isn't built

Nicolai Hähnle (1):
  drm/amdgpu/gfx9: support the amdgpu.disable_cu option

Rex Zhu (3):
  drm/amdgpu: fix vulkan test performance drop and hang on VI
  drm/amd/powerplay: add support for ATOM GFXCLK table v2.
  drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.

kbuild test robot (1):
  drm/amdgpu/gfx9: gfx_v9_0_enable_gfx_static_mg_power_gating() can be 
static

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|   6 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  17 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c  |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c|  19 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 100 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  81 ++-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  16 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |   9 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 218 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h|   3 +
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c |  12 +-
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  |  12 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c |   3 +-
 drivers/gpu/drm/amd/include/amd_shared.h   |   1 +
 drivers/gpu/drm/amd/include/vi_structs.h   | 268 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  23 +-
 .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h   |   9 +
 .../amd/powerplay/hwmgr/vega10_processpptables.c   |  42 +++-
 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h   |   4 +-
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   |   2 +-
 drivers/gpu/drm/ttm/ttm_bo.c   |   4 +-
 include/uapi/drm/amdgpu_drm.h  |   3 +
 28 files changed, 687 insertions(+), 197 deletions(-)
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Re: Question about porting VCE1 to amdgpu

[Alex Deucher]

On Tue, Jun 27, 2017 at 1:08 PM, Alexandre Demers
 wrote:
> Just a quick update: things a getting into shape slowly since my paternal
> vacancy is over, but I'm still progressing. I'm debugging things as I can. I
> managed to work around the missing header with the current firmware after
> analyzing what it contains and where it is used.

I'd suggest just tacking the header onto the existing firmware.  The
only thing we use it for on the multi-media firmware is the version
info which you can read out of the raw firmware and populate based on
the code in radeon_vce_init().

Alex

>
> I'm more interested than ever to have VCE and UVD ported to amdgpu, since we
> now have cards from the 300 series at work (one based on GCN 1, the other on
> GCN 2).
>
> By the way, the R7 360 (based on GCN 2, Bonaire Pro) fails to load the
> amdgpu driver because of an error in VCE 2 implementation.
>
> I'll keep you up to date.
>
> Alexandre
>
> On Wed, 14 Jun 2017 at 14:22 Deucher, Alexander 
> wrote:
>>
>>
>>
>> From: Alexandre Demers [mailto:alexandre.f.dem...@gmail.com]
>> Sent: Wednesday, June 14, 2017 1:30 PM
>> To: Deucher, Alexander; Christian König; Freedesktop - AMD-gfx
>>
>>
>> Subject: Re: Question about porting VCE1 to amdgpu
>>
>> On Wed, 14 Jun 2017 at 13:09 Deucher, Alexander
>>  wrote:
>>
>>
>>
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
>> Christian König
>> Sent: Wednesday, June 14, 2017 12:37 PM
>> To: Alexandre Demers; Freedesktop - AMD-gfx
>> Subject: Re: Question about porting VCE1 to amdgpu
>>
>>
>>
>> - Would we need a different firmware version with a different "hdr" for
>> the amdgpu driver?
>>
>> Yes, we should probably release the latest one instead of reusing the one
>> used with radeon.
>>
>> Actually, we should probably stick the same one as radeon for now until we
>> can verify the new firmware in general.  Easier to start with a known
>> working case.
>>
>>
>>
>> OK. Then,  is it expected to have a validation failure with the current
>> firmware? Is the header compatible with how the validation is done under
>> VCE2 and others or should I keep how it was done under radeon?
>>
>> There is no header on the multi-media firmware from radeon, so you'd need
>> to add one.  The header is documented in amdgpu_ucode.h,  All you'd need to
>> do is prepend the header to the existing firmware image.
>>
>>
>>
>> Alex
>>
>>
>>
>>
>>
>>
>> BTW: Does VCE work on CIK? Alex, don't we run into the same issue there as
>> well?
>>
>> VCE works on CIK.  We ported VCE and UVD to CIK as part of the initial
>> amdgpu bring up.
>>
>>
>>
>> I've been using VCE2 port as my template for VCE1. My initial intention
>> was to work on UVD, but I ended up plugging in VCE in the first place. UVD
>> is on my todo list right next, I was expecting to working on it after fixing
>> the VCE part.
>>
>>
>>
>>
>>
>> Alex
>>
>>
>>
>> - Wouldn't it be better to continue loading the driver while having VCE
>> disabled IF we fail when loading or validating the FW? Completely failing to
>> load the driver for this reason seems overkill IMO, since nothing has been
>> loaded in memory and no registry have been modified up to that point.
>>
>> UVD and VCE are actually needed for correct power management. When the
>> blocks fail to initialize you usually sooner or later run into problems with
>> power management (e.g. stuck inside a certain power level).
>>
>>
>>
>> OK, but right now it is disabled, so the situation wouldn't be worst isn't
>> it?
>>
>>
>>
>>
>>
>> - Would it be a good idea to send a patch as a RFC so some of you could
>> help me finish the job and maybe pinpoint where the last modifications need
>> to be done?
>>
>> Well you could, but to be honest without AMD releasing new firmware that
>> is most likely a futile effort.
>>
>>
>>
>> I'll send a patch then, and we'll navigate from there. This will allow me
>> to work on UVD in parallel.
>>
>>
>>
>> Alexandre Demers
>>
>>
>>
>>
>> Regards,
>> Christian.
>>
>> Am 14.06.2017 um 18:22 schrieb Alexandre Demers:
>>
>> Hi,
>>
>>
>>
>> I've been working on porting VCE1 from radeon to amdgpu in the last few
>> weeks. I'm pretty much done and I've enabled the functionality to see how it
>> goes. However, I ended up with an error on the firmware validation (size
>> doesn't seem to fit), thus failing completely in loading the driver. I'm
>> testing on a R9 280X (Tahiti).
>>
>>
>>
>> Three questions then:
>>
>> - Would we need a different firmware version with a different "hdr" for
>> the amdgpu driver?
>>
>> - Wouldn't it be better to continue loading the driver while having VCE
>> disabled IF we fail when loading or validating the FW? Completely failing to
>> load the driver for this reason seems overkill IMO, since nothing has been
>> loaded in memory and no registry have been modified up to that point.
>>
>> - Would it be a good idea to send a patch as a RFC so some of 

[PATCH 2/2] drm/amdgpu/soc15: init nbio registers for vega10

[Alex Deucher]

Call nbio init registers on hw_init to set up any
nbio registers that need initialization at hw init time.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f5669af..10cc01e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -691,6 +691,9 @@ static int soc15_common_hw_init(void *handle)
soc15_pcie_gen3_enable(adev);
/* enable aspm */
soc15_program_aspm(adev);
+   /* setup nbio registers */
+   if (!(adev->flags & AMD_IS_APU))
+   nbio_v6_1_init_registers(adev);
/* enable the doorbell aperture */
soc15_enable_doorbell_aperture(adev, true);
 
-- 
2.5.5

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[PATCH 1/2] drm/amdgpu: add nbio 6.1 register init function

[Alex Deucher]

Used for nbio registers that need to be initialized.  Currently
only used for a golden setting that got missed on some boards.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 13 +
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 61c0028..045988b 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -32,6 +32,7 @@
 
 #define smnCPM_CONTROL 
 0x11180460
 #define smnPCIE_CNTL2  
 0x11180070
+#define smnPCIE_CONFIG_CNTL
 0x11180044
 
 u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
@@ -256,3 +257,15 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
}
 }
+
+void nbio_v6_1_init_registers(struct amdgpu_device *adev)
+{
+   uint32_t def, data;
+
+   def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
+   data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 
CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+   data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 
CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+   if (def != data)
+   WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index f6f8bc0..686e4b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -50,5 +50,6 @@ void nbio_v6_1_update_medium_grain_clock_gating(struct 
amdgpu_device *adev, bool
 void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
bool enable);
 void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
 void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);
+void nbio_v6_1_init_registers(struct amdgpu_device *adev);
 
 #endif
-- 
2.5.5

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Re: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

[Alex Deucher]

On Wed, Jul 5, 2017 at 11:04 AM, Liu, Shaoyun <shaoyun@amd.com> wrote:
> Thanks .
> Split the change as suggested and pushed .

Doesn't look like the second patch landed yet.  I don't see in queued
in gerrit either.

Alex

>
> Regards
> Shaoyun.liu
>
> -Original Message-
> From: Deucher, Alexander
> Sent: Wednesday, July 05, 2017 9:17 AM
> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
>
>> -Original Message-
>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Shaoyun Liu
>> Sent: Tuesday, July 04, 2017 2:33 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Liu, Shaoyun
>> Subject: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine
>>
>> nbio hdp flush routine are called within atomic context.
>> Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register
>> since this register has its own VF copy
>>
>> Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6
>> Signed-off-by: Shaoyun Liu <shaoyun@amd.com>
>
> Please split this patch in two, one to add the new macro, the next to convert 
> the nbio code.  With that fixed:
> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c| 2 +-
>>  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c| 2 +-
>>  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 7 +++
>>  3 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 1e272f7..61c0028 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device
>> *adev, bool enable)
>>
>>  void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)  {
>> - WREG32_SOC15(NBIO, 0,
>> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>> + WREG32_SOC15_NO_KIQ(NBIO, 0,
>> mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);  }
>>
>>  u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) diff --git
>> a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> index aa04632..11b70d6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>> @@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct amdgpu_device
>> *adev, bool enable)
>>
>>  void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)  {
>> - WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL,
>> 0);
>> + WREG32_SOC15_NO_KIQ(NBIO, 0,
>> mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
>>  }
>>
>>  u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) diff --git
>> a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> index e2d330e..7a8e4e28 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> @@ -77,6 +77,13 @@ struct nbio_pcie_index_data {
>>   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
>>   (ip##_BASE__INST##inst##_SEG4 + reg), value)
>>
>> +#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
>> + WREG32_NO_KIQ( (0 == reg##_BASE_IDX ?
>> ip##_BASE__INST##inst##_SEG0 + reg : \
>> + (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 +
>> reg : \
>> + (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 +
>> reg : \
>> + (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 +
>> reg : \
>> + (ip##_BASE__INST##inst##_SEG4 + reg), value)
>> +
>>  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
>>   WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0
>> + reg : \
>>   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
>> --
>> 1.9.1
>>
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>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 3/3] drm/amdgpu/gmc9: get vram width from atom for Raven

[Alex Deucher]

Get it from the system info table.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 76 ++-
 1 file changed, 40 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 175ba5f..19f3ffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -23,6 +23,7 @@
 #include 
 #include "amdgpu.h"
 #include "gmc_v9_0.h"
+#include "amdgpu_atomfirmware.h"
 
 #include "vega10/soc15ip.h"
 #include "vega10/HDP/hdp_4_0_offset.h"
@@ -442,43 +443,46 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
u32 tmp;
int chansize, numchan;
 
-   /* hbm memory channel size */
-   chansize = 128;
-
-   tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
-   tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
-   tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
-   switch (tmp) {
-   case 0:
-   default:
-   numchan = 1;
-   break;
-   case 1:
-   numchan = 2;
-   break;
-   case 2:
-   numchan = 0;
-   break;
-   case 3:
-   numchan = 4;
-   break;
-   case 4:
-   numchan = 0;
-   break;
-   case 5:
-   numchan = 8;
-   break;
-   case 6:
-   numchan = 0;
-   break;
-   case 7:
-   numchan = 16;
-   break;
-   case 8:
-   numchan = 2;
-   break;
+   adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
+   if (!adev->mc.vram_width) {
+   /* hbm memory channel size */
+   chansize = 128;
+
+   tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
+   tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+   tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
+   switch (tmp) {
+   case 0:
+   default:
+   numchan = 1;
+   break;
+   case 1:
+   numchan = 2;
+   break;
+   case 2:
+   numchan = 0;
+   break;
+   case 3:
+   numchan = 4;
+   break;
+   case 4:
+   numchan = 0;
+   break;
+   case 5:
+   numchan = 8;
+   break;
+   case 6:
+   numchan = 0;
+   break;
+   case 7:
+   numchan = 16;
+   break;
+   case 8:
+   numchan = 2;
+   break;
+   }
+   adev->mc.vram_width = numchan * chansize;
}
-   adev->mc.vram_width = numchan * chansize;
 
/* Could aper size report 0 ? */
adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-- 
2.5.5

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[PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Alex Deucher]

Not all vbios images seem to set the version appropriately.
Switch the check based on asic type instead.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +--
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 365e735..ea3a250 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -86,19 +86,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
return false;
 }
 
-static bool is_atom_fw(uint8_t *bios)
-{
-   uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
-   uint8_t frev = bios[bios_header_start + 2];
-   uint8_t crev = bios[bios_header_start + 3];
-
-   if ((frev < 3) ||
-   ((frev == 3) && (crev < 3)))
-   return false;
-
-   return true;
-}
-
 /* If you boot an IGP board with a discrete card as the primary,
  * the IGP rom is not accessible via the rom bar as the IGP rom is
  * part of the system bios.  On boot, the system bios puts a
@@ -455,6 +442,6 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
return false;
 
 success:
-   adev->is_atom_fw = is_atom_fw(adev->bios);
+   adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;
return true;
 }
-- 
2.5.5

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[PATCH 2/3] drm/amdgpu/atomfirmware: implement vram_width for APUs

[Alex Deucher]

Implement support using the new atomfirmware system info table.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 33 
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 4bdda56..7a0212b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -130,3 +130,36 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct 
amdgpu_device *adev)
ctx->scratch_size_bytes = usage_bytes;
return 0;
 }
+
+union igp_info {
+   struct atom_integrated_system_info_v1_11 v11;
+};
+
+/*
+ * Return vram width from integrated system info table, if available,
+ * or 0 if not.
+ */
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
+{
+   struct amdgpu_mode_info *mode_info = >mode_info;
+   int index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+   integratedsysteminfo);
+   u16 data_offset, size;
+   union igp_info *igp_info;
+   u8 frev, crev;
+
+   /* get any igp specific overrides */
+   if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, ,
+  , , _offset)) {
+   igp_info = (union igp_info *)
+   (mode_info->atom_context->bios + data_offset);
+   switch (crev) {
+   case 11:
+   return igp_info->v11.umachannelnumber * 64;
+   default:
+   return 0;
+   }
+   }
+
+   return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index a2c3ebe..e37e4c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -31,5 +31,6 @@ void amdgpu_atomfirmware_scratch_regs_restore(struct 
amdgpu_device *adev);
 void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,
  bool hung);
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
 
 #endif
-- 
2.5.5

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Re: [PATCH] drm/amdgpu: add parameter to allocate high priority contexts v8

[Alex Deucher]

On Tue, Apr 25, 2017 at 4:28 PM, Andres Rodriguez  wrote:
>
>
> On 2017-04-25 02:01 PM, Nicolai Hähnle wrote:
>>
>> On 24.04.2017 18:20, Andres Rodriguez wrote:
>>>
>>> Add a new context creation parameter to express a global context
>>> priority.
>>>
>>> The priority ranking in descending order is as follows:
>>>  * AMDGPU_CTX_PRIORITY_HIGH
>>>  * AMDGPU_CTX_PRIORITY_NORMAL
>>>  * AMDGPU_CTX_PRIORITY_LOW
>>>
>>> The driver will attempt to schedule work to the hardware according to
>>> the priorities. No latency or throughput guarantees are provided by
>>> this patch.
>>>
>>> This interface intends to service the EGL_IMG_context_priority
>>> extension, and vulkan equivalents.
>>>
>>> v2: Instead of using flags, repurpose __pad
>>> v3: Swap enum values of _NORMAL _HIGH for backwards compatibility
>>> v4: Validate usermode priority and store it
>>> v5: Move priority validation into amdgpu_ctx_ioctl(), headline reword
>>> v6: add UAPI note regarding priorities requiring CAP_SYS_ADMIN
>>> v7: remove ctx->priority
>>> v8: added AMDGPU_CTX_PRIORITY_LOW, s/CAP_SYS_ADMIN/CAP_SYS_NICE
>>>
>>> Reviewed-by: Emil Velikov 
>>> Reviewed-by: Christian König 
>>> Signed-off-by: Andres Rodriguez 
>>
>>
>> I didn't follow all the discussion, so feel free to shut me up if this
>> has already been discussed, but...
>>
>>
>> [snip]
>>>
>>> +/* Context priority level */
>>> +#define AMDGPU_CTX_PRIORITY_NORMAL0
>>> +#define AMDGPU_CTX_PRIORITY_LOW1
>>> +/* Selecting a priority above NORMAL requires CAP_SYS_ADMIN */
>>> +#define AMDGPU_CTX_PRIORITY_HIGH2
>>> +#define AMDGPU_CTX_PRIORITY_NUM3
>>
>>
>> I get that normal priority needs to be 0 for backwards compatibility,
>> but having LOW between NORMAL and HIGH is still odd. Have you considered
>> using signed integers as a way to fix that?
>
>
> Thanks for the suggestion, that should make it a lot cleaner.

Maybe make the range -1023 to 1023 for consistency with the similar
proposed interface on Intel?
https://lists.freedesktop.org/archives/intel-gfx/2017-April/126155.html

Alex


>
> Regards,
> Andres
>
>
>>
>> (AMDGPU_CTX_PRIORITY_NUM doesn't seem to be used anywhere...)
>>
>> Cheers,
>> Nicolai
>>
>>
>>> +
>>>  struct drm_amdgpu_ctx_in {
>>>  /** AMDGPU_CTX_OP_* */
>>>  __u32op;
>>>  /** For future use, no flags defined so far */
>>>  __u32flags;
>>>  __u32ctx_id;
>>> -__u32_pad;
>>> +__u32priority;
>>>  };
>>>
>>>  union drm_amdgpu_ctx_out {
>>>  struct {
>>>  __u32ctx_id;
>>>  __u32_pad;
>>>  } alloc;
>>>
>>>  struct {
>>>  /** For future use, no flags defined so far */
>>>  __u64flags;
>>>  /** Number of resets caused by this context so far. */
>>>  __u32hangs;
>>>  /** Reset status since the last call of the ioctl. */
>>>  __u32reset_status;
>>>  } state;
>>>  };
>>>
>>>  union drm_amdgpu_ctx {
>>>  struct drm_amdgpu_ctx_in in;
>>>
>>
>>
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Re: [PATCH 1/2] drm/radeon: Avoid overflows/divide-by-zero in latency_watermark calculations.

[Alex Deucher]

On Sun, Apr 23, 2017 at 7:33 PM, Mario Kleiner
<mario.kleiner...@gmail.com> wrote:
> At dot clocks > approx. 250 Mhz, some of these calcs will overflow and
> cause miscalculation of latency watermarks, and for some overflows also
> divide-by-zero driver crash. Make calcs more overflow resistant.
>
> This is a direct port of the corresponding patch from amdgpu-kms,
> copy-paste for cik from dce-8 and si from dce-6, with a slightly
> simpler variant for evergreen dce-4/5.
>
> Only tested on DCE-4 evergreen with a Radeon HD-5770.
>
> Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
> Cc: Alex Deucher <alexander.deuc...@amd.com>

Applied the series.  thanks!

Alex

> ---
>  drivers/gpu/drm/radeon/cik.c   | 19 +++
>  drivers/gpu/drm/radeon/evergreen.c |  8 +---
>  drivers/gpu/drm/radeon/si.c| 19 +++
>  3 files changed, 7 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index 53710dd..4f034cb 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -9150,23 +9150,10 @@ static u32 dce8_latency_watermark(struct 
> dce8_wm_params *wm)
> a.full = dfixed_const(available_bandwidth);
> b.full = dfixed_const(wm->num_heads);
> a.full = dfixed_div(a, b);
> +   tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
> +   tmp = min(dfixed_trunc(a), tmp);
>
> -   b.full = dfixed_const(mc_latency + 512);
> -   c.full = dfixed_const(wm->disp_clk);
> -   b.full = dfixed_div(b, c);
> -
> -   c.full = dfixed_const(dmif_size);
> -   b.full = dfixed_div(c, b);
> -
> -   tmp = min(dfixed_trunc(a), dfixed_trunc(b));
> -
> -   b.full = dfixed_const(1000);
> -   c.full = dfixed_const(wm->disp_clk);
> -   b.full = dfixed_div(c, b);
> -   c.full = dfixed_const(wm->bytes_per_pixel);
> -   b.full = dfixed_mul(b, c);
> -
> -   lb_fill_bw = min(tmp, dfixed_trunc(b));
> +   lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
>
> a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * 
> wm->bytes_per_pixel);
> b.full = dfixed_const(1000);
> diff --git a/drivers/gpu/drm/radeon/evergreen.c 
> b/drivers/gpu/drm/radeon/evergreen.c
> index d1b1e0c..3c9c133 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -2188,13 +2188,7 @@ static u32 evergreen_latency_watermark(struct 
> evergreen_wm_params *wm)
> b.full = dfixed_const(wm->num_heads);
> a.full = dfixed_div(a, b);
>
> -   b.full = dfixed_const(1000);
> -   c.full = dfixed_const(wm->disp_clk);
> -   b.full = dfixed_div(c, b);
> -   c.full = dfixed_const(wm->bytes_per_pixel);
> -   b.full = dfixed_mul(b, c);
> -
> -   lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
> +   lb_fill_bw = min(dfixed_trunc(a), wm->disp_clk * wm->bytes_per_pixel 
> / 1000);
>
> a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * 
> wm->bytes_per_pixel);
> b.full = dfixed_const(1000);
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 528e5a4..3efdfd0 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -2204,23 +2204,10 @@ static u32 dce6_latency_watermark(struct 
> dce6_wm_params *wm)
> a.full = dfixed_const(available_bandwidth);
> b.full = dfixed_const(wm->num_heads);
> a.full = dfixed_div(a, b);
> +   tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
> +   tmp = min(dfixed_trunc(a), tmp);
>
> -   b.full = dfixed_const(mc_latency + 512);
> -   c.full = dfixed_const(wm->disp_clk);
> -   b.full = dfixed_div(b, c);
> -
> -   c.full = dfixed_const(dmif_size);
> -   b.full = dfixed_div(c, b);
> -
> -   tmp = min(dfixed_trunc(a), dfixed_trunc(b));
> -
> -   b.full = dfixed_const(1000);
> -   c.full = dfixed_const(wm->disp_clk);
> -   b.full = dfixed_div(c, b);
> -   c.full = dfixed_const(wm->bytes_per_pixel);
> -   b.full = dfixed_mul(b, c);
> -
> -   lb_fill_bw = min(tmp, dfixed_trunc(b));
> +   lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
>
> a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * 
> wm->bytes_per_pixel);
> b.full = dfixed_const(1000);
> --
> 2.7.4
>
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Re: [PATCH 1/2] drm/amdgpu: Add missing lb_vblank_lead_lines setup to DCE-6 path.

[Alex Deucher]

On Sun, Apr 23, 2017 at 7:02 PM, Mario Kleiner
<mario.kleiner...@gmail.com> wrote:
> This apparently got lost when implementing the new DCE-6 support
> and would cause failures in pageflip scheduling and timestamping.
>
> Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
> Cc: Alex Deucher <alexander.deuc...@amd.com>
> Cc: sta...@vger.kernel.org

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 307269b..e146d25 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -979,7 +979,7 @@ static void dce_v6_0_program_watermarks(struct 
> amdgpu_device *adev,
> u32 priority_a_mark = 0, priority_b_mark = 0;
> u32 priority_a_cnt = PRIORITY_OFF;
> u32 priority_b_cnt = PRIORITY_OFF;
> -   u32 tmp, arb_control3;
> +   u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
> fixed20_12 a, b, c;
>
> if (amdgpu_crtc->base.enabled && num_heads && mode) {
> @@ -1091,6 +1091,8 @@ static void dce_v6_0_program_watermarks(struct 
> amdgpu_device *adev,
> c.full = dfixed_div(c, a);
> priority_b_mark = dfixed_trunc(c);
> priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
> +
> +   lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, 
> mode->crtc_hdisplay);
> }
>
> /* select wm A */
> @@ -1120,6 +1122,9 @@ static void dce_v6_0_program_watermarks(struct 
> amdgpu_device *adev,
> /* save values for DPM */
> amdgpu_crtc->line_time = line_time;
> amdgpu_crtc->wm_high = latency_watermark_a;
> +
> +   /* Save number of lines the linebuffer leads before the scanout */
> +   amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
>  }
>
>  /* watermark setup */
> --
> 2.7.4
>
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Re: [PATCH] drm/amdgpu: remove unused and mostly unimplemented CGS functions v2

[Alex Deucher]

On Thu, Apr 27, 2017 at 9:22 AM, Christian König
<deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> Those functions are all unused and some not even implemented.
>
> v2: keep cgs_get_pci_resource it is used by the ACP driver.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 198 ---
>  drivers/gpu/drm/amd/include/cgs_common.h | 270 
> ---
>  2 files changed, 468 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index a1a2d44..9d22ebd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -42,82 +42,6 @@ struct amdgpu_cgs_device {
> struct amdgpu_device *adev =\
> ((struct amdgpu_cgs_device *)cgs_device)->adev
>
> -static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum 
> cgs_gpu_mem_type type,
> -  uint64_t *mc_start, uint64_t *mc_size,
> -  uint64_t *mem_size)
> -{
> -   CGS_FUNC_ADEV;
> -   switch(type) {
> -   case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
> -   case CGS_GPU_MEM_TYPE__VISIBLE_FB:
> -   *mc_start = 0;
> -   *mc_size = adev->mc.visible_vram_size;
> -   *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
> -   break;
> -   case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
> -   case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
> -   *mc_start = adev->mc.visible_vram_size;
> -   *mc_size = adev->mc.real_vram_size - 
> adev->mc.visible_vram_size;
> -   *mem_size = *mc_size;
> -   break;
> -   case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
> -   case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
> -   *mc_start = adev->mc.gtt_start;
> -   *mc_size = adev->mc.gtt_size;
> -   *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
> -   break;
> -   default:
> -   return -EINVAL;
> -   }
> -
> -   return 0;
> -}
> -
> -static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
> -   uint64_t size,
> -   uint64_t min_offset, uint64_t max_offset,
> -   cgs_handle_t *kmem_handle, uint64_t *mcaddr)
> -{
> -   CGS_FUNC_ADEV;
> -   int ret;
> -   struct amdgpu_bo *bo;
> -   struct page *kmem_page = vmalloc_to_page(kmem);
> -   int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
> -
> -   struct sg_table *sg = drm_prime_pages_to_sg(_page, npages);
> -   ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
> -  AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, );
> -   if (ret)
> -   return ret;
> -   ret = amdgpu_bo_reserve(bo, false);
> -   if (unlikely(ret != 0))
> -   return ret;
> -
> -   /* pin buffer into GTT */
> -   ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
> -  min_offset, max_offset, mcaddr);
> -   amdgpu_bo_unreserve(bo);
> -
> -   *kmem_handle = (cgs_handle_t)bo;
> -   return ret;
> -}
> -
> -static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, 
> cgs_handle_t kmem_handle)
> -{
> -   struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
> -
> -   if (obj) {
> -   int r = amdgpu_bo_reserve(obj, false);
> -   if (likely(r == 0)) {
> -   amdgpu_bo_unpin(obj);
> -   amdgpu_bo_unreserve(obj);
> -   }
> -   amdgpu_bo_unref();
> -
> -   }
> -   return 0;
> -}
> -
>  static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
> enum cgs_gpu_mem_type type,
> uint64_t size, uint64_t align,
> @@ -349,62 +273,6 @@ static void amdgpu_cgs_write_ind_register(struct 
> cgs_device *cgs_device,
> WARN(1, "Invalid indirect register space");
>  }
>
> -static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device 
> *cgs_device, unsigned addr)
> -{
> -   CGS_FUNC_ADEV;
> -   uint8_t val;
> -   int ret = pci_read_config_byte(adev->pdev, addr, );
> -   if (WARN(ret, "pci_read

Re: [PATCH umr] Avoid opening the DRM file by default

[Alex Deucher]

On Thu, Apr 27, 2017 at 12:41 PM, Tom St Denis <tom.stde...@amd.com> wrote:
> Opening the DRM file (/dev/dri/card%d) triggers all sorts of KMD
> work to happen which is not useful if the KMD is hung or not working.
>
> Since --top is the only user of the file currently we simply defer
> opening it until --top is invoked.
>
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  src/app/top.c  | 7 +++
>  src/lib/discover.c | 3 +--
>  2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/src/app/top.c b/src/app/top.c
> index 364180eb70f6..a4d3aa8e699d 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -933,8 +933,15 @@ void umr_top(struct umr_asic *asic)
> time_t tt;
> uint64_t ts;
> char hostname[64] = { 0 };
> +   char fname[64];
> pthread_t sensor_thread;
>
> +   // open drm file if not already open
> +   if (asic->fd.drm < 0) {
> +   snprintf(fname, sizeof(fname)-1, "/dev/dri/card%d", 
> asic->instance);
> +   asic->fd.drm = open(fname, O_RDWR);
> +   }
> +
> if (getenv("HOSTNAME")) strcpy(hostname, getenv("HOSTNAME"));
>
> // init stats
> diff --git a/src/lib/discover.c b/src/lib/discover.c
> index d561efafe4d4..c9c2f74a4818 100644
> --- a/src/lib/discover.c
> +++ b/src/lib/discover.c
> @@ -127,8 +127,7 @@ struct umr_asic *umr_discover_asic(struct umr_options 
> *options)
> asic->fd.vram = open(fname, O_RDWR);
> snprintf(fname, sizeof(fname)-1, 
> "/sys/kernel/debug/dri/%d/amdgpu_gpr", asic->instance);
> asic->fd.gpr = open(fname, O_RDWR);
> -   snprintf(fname, sizeof(fname)-1, "/dev/dri/card%d", 
> asic->instance);
> -   asic->fd.drm = open(fname, O_RDWR);
> +   asic->fd.drm = -1; // default to closed
> // if appending to the fd list remember to update 
> close_asic() and discover_by_did()...
>
> if (options->use_pci) {
> --
> 2.12.0
>
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[pull] radeon and amdgpu drm-next-4.12

[Alex Deucher]

Hi Dave,

Fixes for 4.12.  Mostly updates for vega10 which is new for
4.12.  Highlights:
- Lots of vega10 fixes
- fix interruptable wait mixup
- misc display fixes for radeon and amdgpu
- misc bug fixes

The following changes since commit 73ba2d5c2bd4ecfec8fe37f20e962889b8a4c972:

  Merge tag 'drm-intel-next-fixes-2017-04-27' of 
git://anongit.freedesktop.org/git/drm-intel into drm-next (2017-04-29 05:50:27 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.12

for you to fetch changes up to c81a1a74037f61c578f6b8218b079aa434e300b4:

  drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup 
(2017-04-28 17:33:16 -0400)


Alex Deucher (3):
  drm/amdgpu: fix spelling in header comment
  drm/amdgpu: bump version number to note race fix and new fence 
functionality
  Revert "drm/amd/amdgpu: Set VCE/UVD off during late init"

Alex Xie (8):
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Real return value can be over-written when clean up
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting
  drm/amdgpu: Fix use of interruptible waiting

Christian König (14):
  drm/amdgpu: add VMHUB to ring association
  drm/amdgpu: drop VMID per ring tracking
  drm/amdgpu: split VMID management by VMHUB
  drm/amdgpu: invalidate only the currently needed VMHUB v2
  drm/amdgpu: assign VM invalidation engine manually v2
  drm/amdgpu: allow concurrent VM flushes
  drm/amdgpu: trace the vmhub in grab_id as well
  drm/amdgpu: trace vm hub during flush as well v2
  drm/radeon: force the UVD DPB into VRAM as well
  drm/amdgpu: fix coding style and printing in amdgpu_doorbell_init
  drm/amdgpu: fix amdgpu_vm_clear_freed v2
  drm/amdgpu: fix amdgpu_ttm_bo_eviction_valuable
  drm/amdgpu: fix VM clearing in amdgpu_gem_object_close
  drm/amdgpu: remove unused and mostly unimplemented CGS functions v2

Chunming Zhou (6):
  drm/amdgpu: add gtt print like vram when dump mm table V2
  drm/amdgpu: increase gtt size to 3GB by default v2
  drm/amdgpu: fix no-vmid job
  drm/amdgpu: fix gpu reset crash
  drm/amdgpu: fix NULL pointer error
  drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2

Daniel Wang (2):
  drm/amdgpu/psp: skip loading SDMA/RLCG under SRIOV VF
  drm/amdgpu/vce4: fix a PSP loading VCE issue

Evan Quan (1):
  drm/amdgpu: update smu9 driver interface

Frank Min (7):
  drm/amdgpu/vce4: update VCE initialization sequence for SRIOV
  drm/amdgpu/vce4: enable ring & ib test for sriov
  drm/amdgpu/vce4: move mm table constructions functions into mmsch header 
file
  drm/amdgpu/uvd7: add sriov uvd initialization sequences
  drm/amdgpu/uvd7: add uvd doorbell initialization for sriov
  drm/amdgpu/uvd7: add UVD hw init sequences for sriov
  drm/amdgpu/soc15: enable UVD code path for sriov

Huang Rui (14):
  drm/amdgpu: split psp tmr init function
  drm/amdgpu: add psp firmware private memory
  drm/amdgpu: use private memory to store psp firmware data
  drm/amdgpu: split psp asd function
  drm/amdgpu: split psp ring init function
  drm/amdgpu: add hw_start and non-psp firmware loading into resume
  drm/amd/powerplay: fix suspend error on DPM disabled
  drm/amdgpu: do not free fence buf when driver probes.
  drm/amdgpu: fix to clear ASIC INIT COMPLETE bit on resuming phase
  drm/amdgpu: fix to add buffer funcs check
  drm/amdgpu: fix dead lock if any ip block resume failed in s3
  drm/amdgpu: fix to print incorrect wptr address
  drm/ttm: cleanup unuse ret value
  drm/amd/powerplay: add error message to remind user updating firmware

Junwei Zhang (3):
  drm/amdgpu: fix double_offchip_lds_buf for gfx v6
  drm/amdgpu: export more gpu info for gfx9
  drm/amdgpu: bump version for exporting gpu info for gfx9

Mario Kleiner (3):
  drm/amdgpu: Add missing lb_vblank_lead_lines setup to DCE-6 path.
  drm/radeon: Avoid overflows/divide-by-zero in latency_watermark 
calculations.
  drm/radeon: Make display watermark calculations more accurate

Michel Dänzer (1):
  drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup

Monk Liu (1):
  drm/amdgpu:fix race condition

Pan Bian (2):
  drm/radeon: check return value of radeon_ring_lock
  drm/radeon: check return value of radeon_fence_emit

Pixel Ding (1):
  drm/amdgpu/virt: don't check VALID bit for FLR completion message

Rex Zhu (16):
  drm/amd/powerplay: align with VBIOS to support new AVFS structure
  drm/amdgpu: Remove redundant itermediate return val in sdma_v4_0.c

Re: [PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations

[Alex Deucher]

On Fri, Jul 28, 2017 at 6:08 PM, Andy Furniss <adf.li...@gmail.com> wrote:
> Alex Deucher wrote:
>>
>> May waste a bit of memory, but simplifies the interface
>> significantly.
>
>
> Can't boot tonga with this (testing 4.14-wip)

Should be fixed with this patch.

Alex

>
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu kernel modesetting enabled.
> Jul 28 23:00:29 ph4 kernel: [drm] initializing kernel modesetting (TONGA
> 0x1002:0x6939 0x1458:0x229D 0x00).
> Jul 28 23:00:29 ph4 kernel: [drm] register mmio base: 0xFEA0
> Jul 28 23:00:29 ph4 kernel: [drm] register mmio size: 262144
> Jul 28 23:00:29 ph4 kernel: [drm] probing gen 2 caps for device 1002:5a16 =
> 31cd02/0
> Jul 28 23:00:29 ph4 kernel: [drm] probing mlw for device 1002:5a16 = 31cd02
> Jul 28 23:00:29 ph4 kernel: [drm] VCE enabled in physical mode
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: Invalid PCI ROM header
> signature: expecting 0xaa55, got 0x8b00
> Jul 28 23:00:29 ph4 kernel: ATOM BIOS: 113-xxx-Xxx
> Jul 28 23:00:29 ph4 kernel: [drm] GPU post is not needed
> Jul 28 23:00:29 ph4 kernel: [drm] Changing default dispclk from 600Mhz to
> 625Mhz
> Jul 28 23:00:29 ph4 kernel: [drm] vm size is 64 GB, block size is 13-bit
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: VRAM: 2048M
> 0x00F4 - 0x00F47FFF (2048M used)
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: GTT: 256M
> 0x - 0x0FFF
> Jul 28 23:00:29 ph4 kernel: [drm] Detected VRAM RAM=2048M, BAR=256M
> Jul 28 23:00:29 ph4 kernel: [drm] RAM width 256bits GDDR5
> Jul 28 23:00:29 ph4 kernel: [TTM] Zone  kernel: Available graphics memory:
> 4069418 kiB
> Jul 28 23:00:29 ph4 kernel: [TTM] Zone   dma32: Available graphics memory:
> 2097152 kiB
> Jul 28 23:00:29 ph4 kernel: [TTM] Initializing pool allocator
> Jul 28 23:00:29 ph4 kernel: [TTM] Initializing DMA pool allocator
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: 2048M of VRAM memory ready
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: 3072M of GTT memory ready.
> Jul 28 23:00:29 ph4 kernel: [drm] GART: num cpu pages 65536, num gpu pages
> 65536
> Jul 28 23:00:29 ph4 kernel: [drm] PCIE GART of 256M enabled (table at
> 0x00F40004).
> Jul 28 23:00:29 ph4 kernel: [drm] Supports vblank timestamp caching Rev 2
> (21.10.2013).
> Jul 28 23:00:29 ph4 kernel: [drm] Driver supports precise vblank timestamp
> query.
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: amdgpu: using MSI.
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: irq initialized.
> Jul 28 23:00:29 ph4 kernel: amdgpu: [powerplay] amdgpu: powerplay sw
> initialized
> Jul 28 23:00:29 ph4 kernel: [drm] AMDGPU Display Connectors
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 0:
> Jul 28 23:00:29 ph4 kernel: [drm]   DP-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD4
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4868 0x4868 0x4869 0x4869 0x486a
> 0x486a 0x486b 0x486b
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP1: INTERNAL_UNIPHY1
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 1:
> Jul 28 23:00:29 ph4 kernel: [drm]   HDMI-A-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD5
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4870 0x4870 0x4871 0x4871 0x4872
> 0x4872 0x4873 0x4873
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP2: INTERNAL_UNIPHY1
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 2:
> Jul 28 23:00:29 ph4 kernel: [drm]   DVI-D-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD1
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4878 0x4878 0x4879 0x4879 0x487a
> 0x487a 0x487b 0x487b
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP3: INTERNAL_UNIPHY
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 3:
> Jul 28 23:00:29 ph4 kernel: [drm]   DVI-I-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD6
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x487c 0x487c 0x487d 0x487d 0x487e
> 0x487e 0x487f 0x487f
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP4: INTERNAL_UNIPHY2
> Jul 28 23:00:29 ph4 kernel: [drm] CRT1: INTERNAL_KLDSCP_DAC1
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 0 use
> gpu addr 0x00400200, cpu addr 0x88022e059200
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 1 use
> gpu addr 0x00400600, cpu addr 0x88022e059600
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 2 use
> gpu addr 0x00400a00, cpu addr 0x88022e059a00
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 3 use
> gpu addr 0x00400e00, cpu addr 0x88022e059e00
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: (-2

[PATCH 4/9] drm/amdgpu Moving amdgpu asic types to a separate file

[Alex Deucher]

From: Akshu Agrawal <akshu.agra...@amd.com>

Amdgpu asic types will be required for other drivers too.
Hence, its better to keep it in a separate include file.

Signed-off-by: Akshu Agrawal <akshu.agra...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

New patch to share asic_type definitions between GPU and audio driver.

drivers/gpu/drm/amd/include/amd_shared.h | 29 ++
 include/drm/amd_asic_type.h  | 52 
 2 files changed, 54 insertions(+), 27 deletions(-)
 create mode 100644 include/drm/amd_asic_type.h

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 70e8c20..3a49fbd 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -23,34 +23,9 @@
 #ifndef __AMD_SHARED_H__
 #define __AMD_SHARED_H__
 
-#define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
+#include 
 
-/*
- * Supported ASIC types
- */
-enum amd_asic_type {
-   CHIP_TAHITI = 0,
-   CHIP_PITCAIRN,
-   CHIP_VERDE,
-   CHIP_OLAND,
-   CHIP_HAINAN,
-   CHIP_BONAIRE,
-   CHIP_KAVERI,
-   CHIP_KABINI,
-   CHIP_HAWAII,
-   CHIP_MULLINS,
-   CHIP_TOPAZ,
-   CHIP_TONGA,
-   CHIP_FIJI,
-   CHIP_CARRIZO,
-   CHIP_STONEY,
-   CHIP_POLARIS10,
-   CHIP_POLARIS11,
-   CHIP_POLARIS12,
-   CHIP_VEGA10,
-   CHIP_RAVEN,
-   CHIP_LAST,
-};
+#define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
 
 /*
  * Chip flags
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
new file mode 100644
index 000..599028f
--- /dev/null
+++ b/include/drm/amd_asic_type.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_ASIC_TYPE_H__
+#define __AMD_ASIC_TYPE_H__
+/*
+ * Supported ASIC types
+ */
+enum amd_asic_type {
+   CHIP_TAHITI = 0,
+   CHIP_PITCAIRN,
+   CHIP_VERDE,
+   CHIP_OLAND,
+   CHIP_HAINAN,
+   CHIP_BONAIRE,
+   CHIP_KAVERI,
+   CHIP_KABINI,
+   CHIP_HAWAII,
+   CHIP_MULLINS,
+   CHIP_TOPAZ,
+   CHIP_TONGA,
+   CHIP_FIJI,
+   CHIP_CARRIZO,
+   CHIP_STONEY,
+   CHIP_POLARIS10,
+   CHIP_POLARIS11,
+   CHIP_POLARIS12,
+   CHIP_VEGA10,
+   CHIP_RAVEN,
+   CHIP_LAST,
+};
+
+#endif /*__AMD_ASIC_TYPE_H__ */
-- 
2.5.5

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[PATCH 0/9 v2] Add ASoC support for AMD Stoney APUs

[Alex Deucher]

This patch set updates the AMD GPU and Audio CoProcessor (ACP)
audio drivers and the designware i2s driver for Stoney (ST).
ST is an APU similar to Carrizo (CZ) which already has ACP audio
support.  The i2s controller and ACP audio DMA engine are part of
the GPU and both need updating so I would like to upstream the
whole patch set via one tree if possible.

The current code is based on drm-next, but I'm happy to rebase on
whatever tree this ends up going through if there are any problems
applying.  The entire patch set can be viewed here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=stoney_acp

Thanks!

Alex

v2:
- Patch 1 is already applied to the audio tree, just including it for
  completeness since it's required for this patch set and it's not yet
  in the drm tree.
- New patch to share asic types between gpu and audio drivers
- ACPI ID changed for rt5650 machine driver
- Integrate feedback on other patches

Akshu Agrawal (2):
  drm/amdgpu Moving amdgpu asic types to a separate file
  ASoC: AMD: Add machine driver for cz rt5650

Vijendar Mukunda (7):
  ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver
  drm/amd/amdgpu: Added asic_type as ACP DMA driver platform data
  drm/amd/amdgpu: Added a quirk for Stoney platform
  ASoC: AMD: disabling memory gating in stoney platform
  ASoC: AMD: DMA driver changes for Stoney Platform
  ASoC: AMD: Audio buffer related changes for Stoney
  drm/amd/amdgpu: Disabling Power Gating for Stoney platform

 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c  |  74 ++
 drivers/gpu/drm/amd/include/amd_shared.h |  29 +---
 include/drm/amd_asic_type.h  |  52 +++
 include/sound/designware_i2s.h   |   1 +
 sound/soc/amd/Kconfig|   7 +
 sound/soc/amd/Makefile   |   2 +
 sound/soc/amd/acp-pcm-dma.c  | 243 ---
 sound/soc/amd/acp-rt5645.c   | 210 ++
 sound/soc/amd/acp.h  |   9 ++
 sound/soc/dwc/dwc-i2s.c  |   6 +
 10 files changed, 525 insertions(+), 108 deletions(-)
 create mode 100644 include/drm/amd_asic_type.h
 create mode 100644 sound/soc/amd/acp-rt5645.c

-- 
2.5.5

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[PATCH 2/9 v2] drm/amd/amdgpu: Added asic_type as ACP DMA driver platform data

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

asic_type information is passed to ACP DMA Driver as platform data.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2:Removed asic_type local variable and directly passing asic_type
instance to ACP DMA driver as platform data.

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 ++
 sound/soc/amd/acp-pcm-dma.c | 8 ++--
 sound/soc/amd/acp.h | 7 +++
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 06879d1..0fa8122 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -355,6 +355,8 @@ static int acp_hw_init(void *handle)
adev->acp.acp_cell[0].name = "acp_audio_dma";
adev->acp.acp_cell[0].num_resources = 4;
adev->acp.acp_cell[0].resources = >acp.acp_res[0];
+   adev->acp.acp_cell[0].platform_data = >asic_type;
+   adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
 
adev->acp.acp_cell[1].name = "designware-i2s";
adev->acp.acp_cell[1].num_resources = 1;
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 08b1399..dcbf997 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -73,12 +73,6 @@ static const struct snd_pcm_hardware 
acp_pcm_hardware_capture = {
.periods_max = CAPTURE_MAX_NUM_PERIODS,
 };
 
-struct audio_drv_data {
-   struct snd_pcm_substream *play_stream;
-   struct snd_pcm_substream *capture_stream;
-   void __iomem *acp_mmio;
-};
-
 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 {
return readl(acp_mmio + (reg * 4));
@@ -916,6 +910,7 @@ static int acp_audio_probe(struct platform_device *pdev)
int status;
struct audio_drv_data *audio_drv_data;
struct resource *res;
+   const u32 *pdata = pdev->dev.platform_data;
 
audio_drv_data = devm_kzalloc(>dev, sizeof(struct audio_drv_data),
GFP_KERNEL);
@@ -932,6 +927,7 @@ static int acp_audio_probe(struct platform_device *pdev)
 
audio_drv_data->play_stream = NULL;
audio_drv_data->capture_stream = NULL;
+   audio_drv_data->asic_type =  *pdata;
 
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res) {
diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h
index 330832e..28cf914 100644
--- a/sound/soc/amd/acp.h
+++ b/sound/soc/amd/acp.h
@@ -84,6 +84,13 @@ struct audio_substream_data {
void __iomem *acp_mmio;
 };
 
+struct audio_drv_data {
+   struct snd_pcm_substream *play_stream;
+   struct snd_pcm_substream *capture_stream;
+   void __iomem *acp_mmio;
+   u32 asic_type;
+};
+
 enum {
ACP_TILE_P1 = 0,
ACP_TILE_P2,
-- 
2.5.5

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[PATCH 3/9 v2] drm/amd/amdgpu: Added a quirk for Stoney platform

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Added DW_I2S_QUIRK_16BIT_IDX_OVERRIDE quirk for Stoney.

Supported format and bus width for I2S controller read
from I2S Component Parameter registers.
These are ready only registers.

For Stoney, I2S Component Parameter registers are programmed
to support 32 bit format and 4 bytes bus width only.

By setting this quirk,It will override 32 bit format with
16 bit format and 2 bytes as bus width for Stoney.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: added switch cases for handling asic types.

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 0fa8122..9c0bd6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -319,14 +319,29 @@ static int acp_hw_init(void *handle)
return -ENOMEM;
}
 
-   i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+   switch (adev->asic_type) {
+   case CHIP_STONEY:
+   i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+   DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+   break;
+   default:
+   i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+   }
i2s_pdata[0].cap = DWC_I2S_PLAY;
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
+   switch (adev->asic_type) {
+   case CHIP_STONEY:
+   i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+   DW_I2S_QUIRK_COMP_PARAM1 |
+   DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+   break;
+   default:
+   i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+   DW_I2S_QUIRK_COMP_PARAM1;
+   }
 
-   i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-   DW_I2S_QUIRK_COMP_PARAM1;
i2s_pdata[1].cap = DWC_I2S_RECORD;
i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
-- 
2.5.5

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[PATCH 4/4] drm/amdgpu/sdma4: move wptr polling setup

[Alex Deucher]

Move it up before ring enablement with all of the other
engine setup and explicitly disable it for bare metal.

Cc: Frank Min <frank@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 85b8561..79a9e44 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -662,6 +662,19 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), 
temp);
}
 
+   /* setup the wptr shadow polling */
+   wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+  lower_32_bits(wptr_gpu_addr));
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+  upper_32_bits(wptr_gpu_addr));
+   wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+   if (amdgpu_sriov_vf(adev))
+   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
+   else
+   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 
1);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
@@ -690,17 +703,6 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
if (adev->mman.buffer_funcs_ring == ring)
amdgpu_ttm_set_active_vram_size(adev, 
adev->mc.real_vram_size);
 
-   if (amdgpu_sriov_vf(adev)) {
-   wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 
4);
-   wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
-   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
-
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
-  lower_32_bits(wptr_gpu_addr));
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
-  upper_32_bits(wptr_gpu_addr));
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
-   }
}
 
return 0;
-- 
2.5.5

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[PATCH 2/4] drm/amdgpu/sdma4: drop hdp flush from wptr shadow update

[Alex Deucher]

The wb buffer is in system memory, not vram so the flush
is useless.

Cc: Frank Min <frank@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 660704d..c76727b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -313,7 +313,6 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
offset = 
adev->sdma.instance[i].poll_mem_offs;
atomic64_set((atomic64_t 
*)>wb.wb[offset],
 (ring->wptr << 2));
-   nbio_v6_1_hdp_flush(adev);
}
}
}
-- 
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[PATCH 5/9 v2] ASoC: AMD: disabling memory gating in stoney platform

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

For Stoney platform, Memory gating is disabled.i.e SRAM Banks
won't be turned off. By Default, SRAM Bank state set to ON.
Added condition checks to skip SRAM Bank state set logic for
Stoney platform.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: Added comments in code and removed locally defined macros
for STONEY and Carrizo.

sound/soc/amd/acp-pcm-dma.c | 79 +++--
 1 file changed, 55 insertions(+), 24 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index dcbf997..f00b6b9 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -20,7 +20,7 @@
 #include 
 
 #include 
-
+#include 
 #include "acp.h"
 
 #define PLAYBACK_MIN_NUM_PERIODS2
@@ -419,7 +419,7 @@ static void acp_set_sram_bank_state(void __iomem *acp_mmio, 
u16 bank,
 }
 
 /* Initialize and bring ACP hardware to default state. */
-static int acp_init(void __iomem *acp_mmio)
+static int acp_init(void __iomem *acp_mmio, u32 asic_type)
 {
u16 bank;
u32 val, count, sram_pte_offset;
@@ -493,9 +493,14 @@ static int acp_init(void __iomem *acp_mmio)
/* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
* Now, turn off all of them. This can't be done in 'poweron' of
* ACP pm domain, as this requires ACP to be initialized.
+   * For Stoney, Memory gating is disabled,i.e SRAM Banks
+   * won't be turned off. The default state for SRAM banks is ON.
+   * Setting SRAM bank state code skipped for STONEY platform.
*/
-   for (bank = 1; bank < 48; bank++)
-   acp_set_sram_bank_state(acp_mmio, bank, false);
+   if (asic_type != CHIP_STONEY) {
+   for (bank = 1; bank < 48; bank++)
+   acp_set_sram_bank_state(acp_mmio, bank, false);
+   }
 
return 0;
 }
@@ -646,14 +651,22 @@ static int acp_dma_open(struct snd_pcm_substream 
*substream)
 
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
intr_data->play_stream = substream;
-   for (bank = 1; bank <= 4; bank++)
-   acp_set_sram_bank_state(intr_data->acp_mmio, bank,
-   true);
+   /* For Stoney, Memory gating is disabled,i.e SRAM Banks
+* won't be turned off. The default state for SRAM banks is ON.
+* Setting SRAM bank state code skipped for STONEY platform.
+*/
+   if (intr_data->asic_type != CHIP_STONEY) {
+   for (bank = 1; bank <= 4; bank++)
+   acp_set_sram_bank_state(intr_data->acp_mmio,
+   bank, true);
+   }
} else {
intr_data->capture_stream = substream;
-   for (bank = 5; bank <= 8; bank++)
-   acp_set_sram_bank_state(intr_data->acp_mmio, bank,
-   true);
+   if (intr_data->asic_type != CHIP_STONEY) {
+   for (bank = 5; bank <= 8; bank++)
+   acp_set_sram_bank_state(intr_data->acp_mmio,
+   bank, true);
+   }
}
 
return 0;
@@ -869,14 +882,23 @@ static int acp_dma_close(struct snd_pcm_substream 
*substream)
 
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adata->play_stream = NULL;
-   for (bank = 1; bank <= 4; bank++)
-   acp_set_sram_bank_state(adata->acp_mmio, bank,
-   false);
-   } else {
+   /* For Stoney, Memory gating is disabled,i.e SRAM Banks
+* won't be turned off. The default state for SRAM banks is ON.
+* Setting SRAM bank state code skipped for STONEY platform.
+* added condition checks for Carrizo platform only
+*/
+   if (adata->asic_type != CHIP_STONEY) {
+   for (bank = 1; bank <= 4; bank++)
+   acp_set_sram_bank_state(adata->acp_mmio, bank,
+   false);
+   }
+   } else  {
adata->capture_stream = NULL;
-   for (bank = 5; bank <= 8; bank++)
-   acp_set_sram_bank_state(adata->acp_mmio, bank,
-   false);
+   if (adata->asic_type != CHIP_STONEY) {
+   for (bank = 5; bank <= 8; bank++)
+   acp_set_sram_bank_state(adata->acp_mmio, bank,
+  

[PATCH 6/9 v2] ASoC: AMD: DMA driver changes for Stoney Platform

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Added DMA driver changes for Stoney platform.
Below are the key differences between Stoney and CZ

In Stoney, Memory Gating is disabled.SRAM Banks won't
be turned off.No Of SRAM Banks reduced to 6.
DAGB Garlic Interface used and 16 bit resolution is supported.
SRAM bank 1 & SRAM bank 2 will be used for playback scenario.
SRAM Bank 3 & SRAM Bank 4 will be used for Capture scenario.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: Added switch cases for asic type.

sound/soc/amd/acp-pcm-dma.c | 87 +
 sound/soc/amd/acp.h |  2 ++
 2 files changed, 67 insertions(+), 22 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index f00b6b9..f16e0b8 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -137,8 +137,8 @@ static void config_dma_descriptor_in_sram(void __iomem 
*acp_mmio,
  * system memory <-> ACP SRAM
  */
 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
-  u32 size, int direction,
-  u32 pte_offset)
+   u32 size, int direction,
+   u32 pte_offset, u32 asic_type)
 {
u16 i;
u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
@@ -152,20 +152,42 @@ static void set_acp_sysmem_dma_descriptors(void __iomem 
*acp_mmio,
(size / 2) - (i * (size/2));
dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) + (i * (size/2));
-   dmadscr[i].xfer_val |=
-   (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) |
-   (size / 2);
+   switch (asic_type) {
+   case CHIP_STONEY:
+   dmadscr[i].xfer_val |=
+   (ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM  
<< 16) |
+   (size / 2);
+   break;
+   default:
+   dmadscr[i].xfer_val |=
+   (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM  << 
16) |
+   (size / 2);
+   }
} else {
dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
-   dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
-   (i * (size/2));
-   dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
-   + (pte_offset * SZ_4K) +
-   (i * (size/2));
-   dmadscr[i].xfer_val |=
-   BIT(22) |
-   (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
-   (size / 2);
+   switch (asic_type) {
+   case CHIP_STONEY:
+   dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS +
+   (i * (size/2));
+   dmadscr[i].dest =
+   ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+   (pte_offset * SZ_4K) + (i * (size/2));
+   dmadscr[i].xfer_val |=
+   BIT(22) |
+   (ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC 
<< 16) |
+   (size / 2);
+   break;
+   default:
+   dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
+   (i * (size/2));
+   dmadscr[i].dest =
+   ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+   (pte_offset * SZ_4K) + (i * (size/2));
+   dmadscr[i].xfer_val |=
+   BIT(22) |
+   (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 
16) |
+   (size / 2);
+   }
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
[i]);
@@ -186,7 +208,8 @@ static void set_acp_sysmem_dma_descriptors(void __iomem 
*acp_mmio,
  * ACP SRAM <-> I2S
  */
 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
-  u32 size, int direction)
+   u32 size, int direction,
+

[PATCH 1/9] ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Added quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to Designware
driver. This quirk will set idx value to 1.

By setting this quirk, it will override supported format
as 16 bit resolution and bus width as 2 Bytes.

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

This patch is already applied to the audio tree, I'm just
including it here for completeness since it's not yet in
the drm tree.

include/sound/designware_i2s.h | 1 +
 sound/soc/dwc/dwc-i2s.c| 6 ++
 2 files changed, 7 insertions(+)

diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h
index 5681855..830f5ca 100644
--- a/include/sound/designware_i2s.h
+++ b/include/sound/designware_i2s.h
@@ -47,6 +47,7 @@ struct i2s_platform_data {
 
#define DW_I2S_QUIRK_COMP_REG_OFFSET(1 << 0)
#define DW_I2S_QUIRK_COMP_PARAM1(1 << 1)
+   #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
unsigned int quirks;
unsigned int i2s_reg_comp1;
unsigned int i2s_reg_comp2;
diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c
index 9c46e41..9160676 100644
--- a/sound/soc/dwc/dwc-i2s.c
+++ b/sound/soc/dwc/dwc-i2s.c
@@ -496,6 +496,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
idx = COMP1_TX_WORDSIZE_0(comp1);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
+   if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+   idx = 1;
dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->playback.channels_max =
1 << (COMP1_TX_CHANNELS(comp1) + 1);
@@ -508,6 +510,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
idx = COMP2_RX_WORDSIZE_0(comp2);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
+   if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+   idx = 1;
dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->capture.channels_max =
1 << (COMP1_RX_CHANNELS(comp1) + 1);
@@ -543,6 +547,8 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
if (ret < 0)
return ret;
 
+   if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+   idx = 1;
/* Set DMA slaves info */
dev->play_dma_data.pd.data = pdata->play_dma_data;
dev->capture_dma_data.pd.data = pdata->capture_dma_data;
-- 
2.5.5

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[PATCH 7/9 v2] ASoC: AMD: Audio buffer related changes for Stoney

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Stoney uses 16kb SRAM memory for playback and 16Kb
for capture.Modified Max buffer size to have the
correct mapping between System Memory and SRAM.

Added snd_pcm_hardware structures for playback
and capture for Stoney.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: Added switch cases for asic type.

sound/soc/amd/acp-pcm-dma.c | 73 +
 1 file changed, 68 insertions(+), 5 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index f16e0b8..a6def3b 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -35,6 +35,10 @@
 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
 #define MIN_BUFFER MAX_BUFFER
 
+#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
+#define ST_CAPTURE_MAX_PERIOD_SIZE  8192
+#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
+#define ST_MIN_BUFFER ST_MAX_BUFFER
 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
@@ -73,6 +77,44 @@ static const struct snd_pcm_hardware 
acp_pcm_hardware_capture = {
.periods_max = CAPTURE_MAX_NUM_PERIODS,
 };
 
+static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
+   SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+   .formats = SNDRV_PCM_FMTBIT_S16_LE |
+   SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+   .channels_min = 1,
+   .channels_max = 8,
+   .rates = SNDRV_PCM_RATE_8000_96000,
+   .rate_min = 8000,
+   .rate_max = 96000,
+   .buffer_bytes_max = ST_MAX_BUFFER,
+   .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
+   .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
+   .periods_min = PLAYBACK_MIN_NUM_PERIODS,
+   .periods_max = PLAYBACK_MAX_NUM_PERIODS,
+};
+
+static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
+   SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+   .formats = SNDRV_PCM_FMTBIT_S16_LE |
+   SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+   .channels_min = 1,
+   .channels_max = 2,
+   .rates = SNDRV_PCM_RATE_8000_48000,
+   .rate_min = 8000,
+   .rate_max = 48000,
+   .buffer_bytes_max = ST_MAX_BUFFER,
+   .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
+   .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
+   .periods_min = CAPTURE_MIN_NUM_PERIODS,
+   .periods_max = CAPTURE_MAX_NUM_PERIODS,
+};
+
 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 {
return readl(acp_mmio + (reg * 4));
@@ -664,10 +706,23 @@ static int acp_dma_open(struct snd_pcm_substream 
*substream)
if (adata == NULL)
return -ENOMEM;
 
-   if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-   runtime->hw = acp_pcm_hardware_playback;
-   else
-   runtime->hw = acp_pcm_hardware_capture;
+   if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+   switch (intr_data->asic_type) {
+   case CHIP_STONEY:
+   runtime->hw = acp_st_pcm_hardware_playback;
+   break;
+   default:
+   runtime->hw = acp_pcm_hardware_playback;
+   }
+   } else {
+   switch (intr_data->asic_type) {
+   case CHIP_STONEY:
+   runtime->hw = acp_st_pcm_hardware_capture;
+   break;
+   default:
+   runtime->hw = acp_pcm_hardware_capture;
+   }
+   }
 
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
@@ -905,7 +960,15 @@ static int acp_dma_trigger(struct snd_pcm_substream 
*substream, int cmd)
 
 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
 {
-   return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
+   struct audio_drv_data *adata = dev_get_drvdata(rtd->platform->dev);
+
+   if (adata->asic_type == CHIP_STONEY)
+   return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
+   SNDRV_DMA_TYPE_DEV,
+   NULL, ST_MIN_BUFFER,
+   ST_MAX_BUFFER);
+   else
+ 

[PATCH 8/9 v2] drm/amd/amdgpu: Disabling Power Gating for Stoney platform

[Alex Deucher]

From: Vijendar Mukunda <vijendar.muku...@amd.com>

Power Gating is disabled in Stoney platform.

Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v2: added missing changes required for power gating and
removed local variable.

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 51 ++---
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 9c0bd6c..ebca223 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -285,19 +285,20 @@ static int acp_hw_init(void *handle)
return 0;
else if (r)
return r;
+   if (adev->asic_type != CHIP_STONEY) {
+   adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), 
GFP_KERNEL);
+   if (adev->acp.acp_genpd == NULL)
+   return -ENOMEM;
 
-   adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
-   if (adev->acp.acp_genpd == NULL)
-   return -ENOMEM;
-
-   adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
-   adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
-   adev->acp.acp_genpd->gpd.power_on = acp_poweron;
+   adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
+   adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
+   adev->acp.acp_genpd->gpd.power_on = acp_poweron;
 
 
-   adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
+   adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
 
-   pm_genpd_init(>acp.acp_genpd->gpd, NULL, false);
+   pm_genpd_init(>acp.acp_genpd->gpd, NULL, false);
+   }
 
adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS,
GFP_KERNEL);
@@ -390,12 +391,14 @@ static int acp_hw_init(void *handle)
if (r)
return r;
 
-   for (i = 0; i < ACP_DEVS ; i++) {
-   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-   r = pm_genpd_add_device(>acp.acp_genpd->gpd, dev);
-   if (r) {
-   dev_err(dev, "Failed to add dev to genpd\n");
-   return r;
+   if (adev->asic_type != CHIP_STONEY) {
+   for (i = 0; i < ACP_DEVS ; i++) {
+   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+   r = pm_genpd_add_device(>acp.acp_genpd->gpd, dev);
+   if (r) {
+   dev_err(dev, "Failed to add dev to genpd\n");
+   return r;
+   }
}
}
 
@@ -415,20 +418,22 @@ static int acp_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
/* return early if no ACP */
-   if (!adev->acp.acp_genpd)
+   if (!adev->acp.acp_cell)
return 0;
 
-   for (i = 0; i < ACP_DEVS ; i++) {
-   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-   ret = pm_genpd_remove_device(>acp.acp_genpd->gpd, dev);
-   /* If removal fails, dont giveup and try rest */
-   if (ret)
-   dev_err(dev, "remove dev from genpd failed\n");
+   if (adev->acp.acp_genpd) {
+   for (i = 0; i < ACP_DEVS ; i++) {
+   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+   ret = pm_genpd_remove_device(>acp.acp_genpd->gpd, 
dev);
+   /* If removal fails, dont giveup and try rest */
+   if (ret)
+   dev_err(dev, "remove dev from genpd failed\n");
+   }
+   kfree(adev->acp.acp_genpd);
}
 
mfd_remove_devices(adev->acp.parent);
kfree(adev->acp.acp_res);
-   kfree(adev->acp.acp_genpd);
kfree(adev->acp.acp_cell);
 
return 0;
-- 
2.5.5

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[PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations (v2)

[Alex Deucher]

May waste a bit of memory, but simplifies the interface
significantly.

v2: convert internal accounting to use 256bit slots

Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 77 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 65 +++--
 3 files changed, 20 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d492ff7..19ee2a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1131,10 +1131,6 @@ struct amdgpu_wb {
 
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb);
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
 
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fc6f8d5..62afe3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -504,7 +504,8 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
int r;
 
if (adev->wb.wb_obj == NULL) {
-   r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 
sizeof(uint32_t),
+   /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit 
slots */
+   r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 
sizeof(uint32_t) * 8,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>wb.wb_obj, 
>wb.gpu_addr,
(void **)>wb.wb);
@@ -535,47 +536,10 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 {
unsigned long offset = find_first_zero_bit(adev->wb.used, 
adev->wb.num_wb);
-   if (offset < adev->wb.num_wb) {
-   __set_bit(offset, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
 
-/**
- * amdgpu_wb_get_64bit - Allocate a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Allocate a wb slot for use by the driver (all asics).
- * Returns 0 on success or -EINVAL on failure.
- */
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
-{
-   unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
-   adev->wb.num_wb, 0, 2, 7, 0);
-   if ((offset + 1) < adev->wb.num_wb) {
+   if (offset < adev->wb.num_wb) {
__set_bit(offset, adev->wb.used);
-   __set_bit(offset + 1, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
-
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb)
-{
-   int i = 0;
-   unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
-   adev->wb.num_wb, 0, 8, 63, 0);
-   if ((offset + 7) < adev->wb.num_wb) {
-   for (i = 0; i < 8; i++)
-   __set_bit(offset + i, adev->wb.used);
-   *wb = offset;
+   *wb = offset * 8; /* convert to dw offset */
return 0;
} else {
return -EINVAL;
@@ -597,39 +561,6 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 }
 
 /**
- * amdgpu_wb_free_64bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
-{
-   if ((wb + 1) < adev->wb.num_wb) {
-   __clear_bit(wb, adev->wb.used);
-   __clear_bit(wb + 1, adev->wb.used);
-   }
-}
-
-/**
- * amdgpu_wb_free_256bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb)
-{
-   int i = 0;
-
-   if ((wb + 7) < adev->wb.num_wb)
-   for (i = 0; i < 8; i++)
-   __clear_bit(wb + i, adev->wb.used);
-}
-
-/**
  * amdgpu_vram_location - try to find VRAM location
  * @adev: amdgpu device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ri

Re: [PATCH libdrm 2/2] drm: merge and cleanup amdgpu_bo_free

[Alex Deucher]

On Tue, Aug 8, 2017 at 10:10 PM, Liu, Monk <monk@amd.com> wrote:
> I pushed it to amd-staging-upstream

that branch is long dead.  master tracks upstream now in internal git IIRC.

>
> What else branch did you refer to ?

The upstream tree on freedesktop.org:
https://cgit.freedesktop.org/mesa/drm

Alex


>
> BR Monk
>
>
> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Wednesday, August 9, 2017 12:19 AM
> To: Christian König <deathsim...@vodafone.de>
> Cc: Liu, Monk <monk@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH libdrm 2/2] drm: merge and cleanup amdgpu_bo_free
>
> On Tue, Aug 8, 2017 at 3:54 AM, Christian König <deathsim...@vodafone.de> 
> wrote:
>> Am 08.08.2017 um 09:34 schrieb Monk Liu:
>>>
>>> From: Monk Liu <monk@amd.com>
>>>
>>> since bo_reference and bo_internal_free are all only used by bo_free,
>>> so we just merge them together
>>>
>>> Change-Id: I72ebc9c8bcfcd23f4d52a1385db871a95c23859e
>>> Signed-off-by: Monk Liu <monk@amd.com>
>>
>>
>> Reviewed-by: Christian König <christian.koe...@amd.com>
>
> Pushed both upstream.  Thanks!
>
> Alex
>
>>
>>
>>> ---
>>>   amdgpu/amdgpu_bo.c   | 52
>>> +++-
>>>   amdgpu/amdgpu_internal.h | 33 --
>>>   2 files changed, 29 insertions(+), 56 deletions(-)
>>>
>>> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index
>>> 82f38c0..901673a 100644
>>> --- a/amdgpu/amdgpu_bo.c
>>> +++ b/amdgpu/amdgpu_bo.c
>>> @@ -52,27 +52,6 @@ static void
>>> amdgpu_close_kms_handle(amdgpu_device_handle dev,
>>> drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
>>>   }
>>>   -void amdgpu_bo_free_internal(amdgpu_bo_handle bo) -{
>>> -   /* Remove the buffer from the hash tables. */
>>> -   util_hash_table_remove(bo->dev->bo_handles,
>>> -  (void*)(uintptr_t)bo->handle);
>>> -   if (bo->flink_name) {
>>> -   util_hash_table_remove(bo->dev->bo_flink_names,
>>> -  (void*)(uintptr_t)bo->flink_name);
>>> -   }
>>> -
>>> -   /* Release CPU access. */
>>> -   if (bo->cpu_map_count > 0) {
>>> -   bo->cpu_map_count = 1;
>>> -   amdgpu_bo_cpu_unmap(bo);
>>> -   }
>>> -
>>> -   amdgpu_close_kms_handle(bo->dev, bo->handle);
>>> -   pthread_mutex_destroy(>cpu_access_mutex);
>>> -   free(bo);
>>> -}
>>> -
>>>   int amdgpu_bo_alloc(amdgpu_device_handle dev,
>>> struct amdgpu_bo_alloc_request *alloc_buffer,
>>> amdgpu_bo_handle *buf_handle) @@ -415,8 +394,35
>>> @@ int amdgpu_bo_import(amdgpu_device_handle dev,
>>> int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
>>>   {
>>> -   /* Just drop the reference. */
>>> -   amdgpu_bo_reference(_handle, NULL);
>>> +   struct amdgpu_device *dev;
>>> +   struct amdgpu_bo *bo = buf_handle;
>>> +
>>> +   assert(bo != NULL);
>>> +   dev = bo->dev;
>>> +   pthread_mutex_lock(>bo_table_mutex);
>>> +
>>> +   if (update_references(>refcount, NULL)) {
>>> +   /* Remove the buffer from the hash tables. */
>>> +   util_hash_table_remove(dev->bo_handles,
>>> +
>>> + (void*)(uintptr_t)bo->handle);
>>> +
>>> +   if (bo->flink_name) {
>>> +   util_hash_table_remove(dev->bo_flink_names,
>>> +
>>> (void*)(uintptr_t)bo->flink_name);
>>> +   }
>>> +
>>> +   /* Release CPU access. */
>>> +   if (bo->cpu_map_count > 0) {
>>> +   bo->cpu_map_count = 1;
>>> +   amdgpu_bo_cpu_unmap(bo);
>>> +   }
>>> +
>>> +   amdgpu_close_kms_handle(dev, bo->handle);
>>> +   pthread_mutex_destroy(>cpu_access_mutex);
>>> +   free(bo);
>>> +   }
>>> +
>>> +   pthread_mutex_unlock(>bo_table_mutex);
>>> return 0;
>>>   }
>>>   diff --git a/amdgpu/amdg

Re: [PATCH xf86-video-ati v2 1/3] Use root window (pixmap) instead of screen pixmap for scanout updates

[Alex Deucher]

On Tue, Aug 1, 2017 at 5:19 AM, Michel Dänzer <mic...@daenzer.net> wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> Preparation for following changes, no functional change intended yet.
>
> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> # v1
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
> ---
>
> v2: Add drmmode_screen_damage_destroy to prevent use-after-free on
> server shutdown

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

>
>  src/drmmode_display.c | 21 ++---
>  src/radeon_kms.c  |  2 +-
>  2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index 245a92fb0..309ccbd6d 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -529,11 +529,8 @@ drmmode_crtc_scanout_free(drmmode_crtc_private_ptr 
> drmmode_crtc)
>  _crtc->scanout[1]);
> }
>
> -   if (drmmode_crtc->scanout_damage) {
> +   if (drmmode_crtc->scanout_damage)
> DamageDestroy(drmmode_crtc->scanout_damage);
> -   drmmode_crtc->scanout_damage = NULL;
> -   RegionUninit(_crtc->scanout_last_region);
> -   }
>  }
>
>  void
> @@ -605,6 +602,15 @@ radeon_screen_damage_report(DamagePtr damage, RegionPtr 
> region, void *closure)
> damage->damage.data = NULL;
>  }
>
> +static void
> +drmmode_screen_damage_destroy(DamagePtr damage, void *closure)
> +{
> +   drmmode_crtc_private_ptr drmmode_crtc = closure;
> +
> +   drmmode_crtc->scanout_damage = NULL;
> +   RegionUninit(_crtc->scanout_last_region);
> +}
> +
>  static Bool
>  drmmode_can_use_hw_cursor(xf86CrtcPtr crtc)
>  {
> @@ -793,9 +799,10 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, 
> DisplayModePtr mode,
> if (!drmmode_crtc->scanout_damage) {
> drmmode_crtc->scanout_damage =
> DamageCreate(radeon_screen_damage_report,
> -NULL, DamageReportRawRegion,
> -TRUE, screen, NULL);
> -   
> DamageRegister(>GetScreenPixmap(screen)->drawable,
> +drmmode_screen_damage_destroy,
> +DamageReportRawRegion,
> +TRUE, screen, drmmode_crtc);
> +   DamageRegister(>root->drawable,
>drmmode_crtc->scanout_damage);
> }
>
> diff --git a/src/radeon_kms.c b/src/radeon_kms.c
> index b22c98406..f76d76a91 100644
> --- a/src/radeon_kms.c
> +++ b/src/radeon_kms.c
> @@ -981,7 +981,7 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int 
> scanout_id)
> GCPtr gc = GetScratchGC(pDraw->depth, pScreen);
>
> ValidateGC(pDraw, gc);
> -   (*gc->ops->CopyArea)(>GetScreenPixmap(pScreen)->drawable,
> +   
> (*gc->ops->CopyArea)(>GetWindowPixmap(pScreen->root)->drawable,
>  pDraw, gc,
>  xf86_crtc->x + extents.x1, xf86_crtc->y + 
> extents.y1,
>  extents.x2 - extents.x1, extents.y2 - extents.y1,
> --
> 2.13.3
>
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Re: [PATCH libdrm 1/2] drm: fix missing mutex unlock before return

[Alex Deucher]

On Mon, Aug 7, 2017 at 10:46 AM, Christian König
 wrote:
> Am 07.08.2017 um 16:35 schrieb Monk Liu:
>>
>> From: Monk Liu 
>>
>> Change-Id: I377dde976648d53bc9a3a2d5ba294c284910b109
>> Signed-off-by: Monk Liu 
>
>
> Reviewed-by: Christian König  for this one.

Applied upstream.  thanks!

Alex

>
>> ---
>>   amdgpu/amdgpu_bo.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
>> index ec99488..07eb743 100644
>> --- a/amdgpu/amdgpu_bo.c
>> +++ b/amdgpu/amdgpu_bo.c
>> @@ -297,6 +297,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
>> /* Get a KMS handle. */
>> r = drmPrimeFDToHandle(dev->fd, shared_handle, );
>> if (r) {
>> +   pthread_mutex_unlock(>bo_table_mutex);
>> return r;
>> }
>>
>
>
>
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Re: [PATCH libdrm 2/2] drm: merge and cleanup amdgpu_bo_free

[Alex Deucher]

On Tue, Aug 8, 2017 at 3:54 AM, Christian König  wrote:
> Am 08.08.2017 um 09:34 schrieb Monk Liu:
>>
>> From: Monk Liu 
>>
>> since bo_reference and bo_internal_free are
>> all only used by bo_free, so we just merge them
>> together
>>
>> Change-Id: I72ebc9c8bcfcd23f4d52a1385db871a95c23859e
>> Signed-off-by: Monk Liu 
>
>
> Reviewed-by: Christian König 

Pushed both upstream.  Thanks!

Alex

>
>
>> ---
>>   amdgpu/amdgpu_bo.c   | 52
>> +++-
>>   amdgpu/amdgpu_internal.h | 33 --
>>   2 files changed, 29 insertions(+), 56 deletions(-)
>>
>> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
>> index 82f38c0..901673a 100644
>> --- a/amdgpu/amdgpu_bo.c
>> +++ b/amdgpu/amdgpu_bo.c
>> @@ -52,27 +52,6 @@ static void
>> amdgpu_close_kms_handle(amdgpu_device_handle dev,
>> drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, );
>>   }
>>   -void amdgpu_bo_free_internal(amdgpu_bo_handle bo)
>> -{
>> -   /* Remove the buffer from the hash tables. */
>> -   util_hash_table_remove(bo->dev->bo_handles,
>> -  (void*)(uintptr_t)bo->handle);
>> -   if (bo->flink_name) {
>> -   util_hash_table_remove(bo->dev->bo_flink_names,
>> -  (void*)(uintptr_t)bo->flink_name);
>> -   }
>> -
>> -   /* Release CPU access. */
>> -   if (bo->cpu_map_count > 0) {
>> -   bo->cpu_map_count = 1;
>> -   amdgpu_bo_cpu_unmap(bo);
>> -   }
>> -
>> -   amdgpu_close_kms_handle(bo->dev, bo->handle);
>> -   pthread_mutex_destroy(>cpu_access_mutex);
>> -   free(bo);
>> -}
>> -
>>   int amdgpu_bo_alloc(amdgpu_device_handle dev,
>> struct amdgpu_bo_alloc_request *alloc_buffer,
>> amdgpu_bo_handle *buf_handle)
>> @@ -415,8 +394,35 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
>> int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
>>   {
>> -   /* Just drop the reference. */
>> -   amdgpu_bo_reference(_handle, NULL);
>> +   struct amdgpu_device *dev;
>> +   struct amdgpu_bo *bo = buf_handle;
>> +
>> +   assert(bo != NULL);
>> +   dev = bo->dev;
>> +   pthread_mutex_lock(>bo_table_mutex);
>> +
>> +   if (update_references(>refcount, NULL)) {
>> +   /* Remove the buffer from the hash tables. */
>> +   util_hash_table_remove(dev->bo_handles,
>> +   (void*)(uintptr_t)bo->handle);
>> +
>> +   if (bo->flink_name) {
>> +   util_hash_table_remove(dev->bo_flink_names,
>> +
>> (void*)(uintptr_t)bo->flink_name);
>> +   }
>> +
>> +   /* Release CPU access. */
>> +   if (bo->cpu_map_count > 0) {
>> +   bo->cpu_map_count = 1;
>> +   amdgpu_bo_cpu_unmap(bo);
>> +   }
>> +
>> +   amdgpu_close_kms_handle(dev, bo->handle);
>> +   pthread_mutex_destroy(>cpu_access_mutex);
>> +   free(bo);
>> +   }
>> +
>> +   pthread_mutex_unlock(>bo_table_mutex);
>> return 0;
>>   }
>>   diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
>> index 79da0e7..a6bf831 100644
>> --- a/amdgpu/amdgpu_internal.h
>> +++ b/amdgpu/amdgpu_internal.h
>> @@ -133,8 +133,6 @@ struct amdgpu_semaphore {
>> void amdgpu_device_free_internal(amdgpu_device_handle dev);
>>   -void amdgpu_bo_free_internal(amdgpu_bo_handle bo);
>> -
>>   void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start,
>>uint64_t max, uint64_t alignment);
>>   @@ -177,37 +175,6 @@ static inline bool update_references(atomic_t *dst,
>> atomic_t *src)
>>   }
>> /**
>> - * Assignment between two amdgpu_bo pointers with reference counting.
>> - *
>> - * Usage:
>> - *struct amdgpu_bo *dst = ... , *src = ...;
>> - *
>> - *dst = src;
>> - *// No reference counting. Only use this when you need to move
>> - *// a reference from one pointer to another.
>> - *
>> - *amdgpu_bo_reference(, src);
>> - *// Reference counters are updated. dst is decremented and src is
>> - *// incremented. dst is freed if its reference counter is 0.
>> - */
>> -static inline void amdgpu_bo_reference(struct amdgpu_bo **dst,
>> -   struct amdgpu_bo *src)
>> -{
>> -   pthread_mutex_t *mlock;
>> -   struct amdgpu_bo* bo = *dst;
>> -
>> -   assert(bo != NULL);
>> -   mlock = >dev->bo_table_mutex;
>> -   pthread_mutex_lock(mlock);
>> -
>> -   if (update_references(>refcount, src?>refcount:NULL))
>> -   amdgpu_bo_free_internal(bo);
>> -
>> -   pthread_mutex_unlock(mlock);
>> -   *dst = src;
>> -}
>> -
>> -/**
>>* Assignment between two amdgpu_device pointers with reference
>> counting.
>>*
>>* Usage:
>
>
>
> 

[PATCH 1/3] dma-buf: dma_fence_put is NULL safe

[Alex Deucher]

From: Christian König <christian.koe...@amd.com>

No need to check.

Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/dma-buf/reservation.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/dma-buf/reservation.c b/drivers/dma-buf/reservation.c
index 393817e..87f8f57 100644
--- a/drivers/dma-buf/reservation.c
+++ b/drivers/dma-buf/reservation.c
@@ -195,8 +195,7 @@ reservation_object_add_shared_replace(struct 
reservation_object *obj,
if (old)
kfree_rcu(old, rcu);
 
-   if (old_fence)
-   dma_fence_put(old_fence);
+   dma_fence_put(old_fence);
 }
 
 /**
@@ -258,8 +257,7 @@ void reservation_object_add_excl_fence(struct 
reservation_object *obj,
dma_fence_put(rcu_dereference_protected(old->shared[i],
reservation_object_held(obj)));
 
-   if (old_fence)
-   dma_fence_put(old_fence);
+   dma_fence_put(old_fence);
 }
 EXPORT_SYMBOL(reservation_object_add_excl_fence);
 
-- 
2.5.5

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[PATCH 0/3] dma-buf changes for ttm and amdgpu

[Alex Deucher]

We have some changes in ttm and amdgpu that depend on these patches.
Sumit, can you pull these in via dma-buf or should I roll them up
through my amdgpu tree?

Christian König (3):
  dma-buf: dma_fence_put is NULL safe
  dma-buf: add reservation_object_copy_fences
  dma-buf: fix reservation_object_wait_timeout_rcu to wait correctly v2

 drivers/dma-buf/reservation.c | 97 +--
 include/linux/reservation.h   |  3 ++
 2 files changed, 78 insertions(+), 22 deletions(-)

-- 
2.5.5

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[PATCH 2/3] dma-buf: add reservation_object_copy_fences

[Alex Deucher]

From: Christian König <christian.koe...@amd.com>

Allows us to copy all the fences in a reservation object to another one.

Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/dma-buf/reservation.c | 58 +++
 include/linux/reservation.h   |  3 +++
 2 files changed, 61 insertions(+)

diff --git a/drivers/dma-buf/reservation.c b/drivers/dma-buf/reservation.c
index 87f8f57..e2eff86 100644
--- a/drivers/dma-buf/reservation.c
+++ b/drivers/dma-buf/reservation.c
@@ -262,6 +262,64 @@ void reservation_object_add_excl_fence(struct 
reservation_object *obj,
 EXPORT_SYMBOL(reservation_object_add_excl_fence);
 
 /**
+* reservation_object_copy_fences - Copy all fences from src to dst.
+* @dst: the destination reservation object
+* @src: the source reservation object
+*
+* Copy all fences from src to dst. Both src->lock as well as dst-lock must be
+* held.
+*/
+int reservation_object_copy_fences(struct reservation_object *dst,
+  struct reservation_object *src)
+{
+   struct reservation_object_list *src_list, *dst_list;
+   struct dma_fence *old, *new;
+   size_t size;
+   unsigned i;
+
+   src_list = reservation_object_get_list(src);
+
+   /*
+* resize dst->fence or allocate if it doesn't exist,
+* noop if already correct size
+*/
+   size = offsetof(typeof(*src_list), shared[src_list->shared_count]);
+   dst_list = kmalloc(size, GFP_KERNEL);
+   if (!dst_list)
+   return -ENOMEM;
+
+   kfree(dst->staged);
+   dst->staged = NULL;
+
+   dst_list->shared_count = src_list->shared_count;
+   dst_list->shared_max = src_list->shared_count;
+   for (i = 0; i < src_list->shared_count; ++i)
+   dst_list->shared[i] = dma_fence_get(src_list->shared[i]);
+
+   src_list = reservation_object_get_list(dst);
+
+   old = reservation_object_get_excl(dst);
+   new = reservation_object_get_excl(src);
+
+   dma_fence_get(new);
+
+   preempt_disable();
+   write_seqcount_begin(>seq);
+   /* write_seqcount_begin provides the necessary memory barrier */
+   RCU_INIT_POINTER(dst->fence_excl, new);
+   RCU_INIT_POINTER(dst->fence, dst_list);
+   write_seqcount_end(>seq);
+   preempt_enable();
+
+   if (src_list)
+   kfree_rcu(src_list, rcu);
+   dma_fence_put(old);
+
+   return 0;
+}
+EXPORT_SYMBOL(reservation_object_copy_fences);
+
+/**
  * reservation_object_get_fences_rcu - Get an object's shared and exclusive
  * fences without update side lock held
  * @obj: the reservation object
diff --git a/include/linux/reservation.h b/include/linux/reservation.h
index 156cfd3..21fc84d 100644
--- a/include/linux/reservation.h
+++ b/include/linux/reservation.h
@@ -254,6 +254,9 @@ int reservation_object_get_fences_rcu(struct 
reservation_object *obj,
  unsigned *pshared_count,
  struct dma_fence ***pshared);
 
+int reservation_object_copy_fences(struct reservation_object *dst,
+  struct reservation_object *src);
+
 long reservation_object_wait_timeout_rcu(struct reservation_object *obj,
 bool wait_all, bool intr,
 unsigned long timeout);
-- 
2.5.5

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[pull] radeon and amdgpu drm-next-4.14

[Alex Deucher]

Hi Dave,

More changes for 4.14.  Highlights:
- command submission overhead improvements
- Huge page support for vega10
- physical mode support for mjpeg for asics that don't support UVD vm
- improve ttm_mem_type_manager_func debug
- misc ttm fixes, cleanups
- misc gpuvm cleanups

The following changes since commit 8824c751eb61ebffb053c291199932845bac88b4:

  Merge tag 'omapdrm-4.14' of 
git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next 
(2017-08-18 05:41:32 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.14

for you to fetch changes up to df9bcb0652bbfde1b37bda98f0ad1fa7fda46d67:

  drm/ttm: use reservation_object_trylock in ttm_bo_individualize_resv v2 
(2017-08-18 12:02:58 -0400)


Christian König (18):
  drm/ttm: remove nonsense wait in ttm_bo_cleanup_refs_and_unlock
  drm/ttm: individualize BO reservation obj when they are freed
  drm/amdgpu: only move VM BOs in the LRU during validation v2
  drm/amdgpu: only bind VM shadows after validation v2
  drm/amdgpu: fix Vega10 HW config for 2MB pages
  drm/ttm: make ttm_mem_type_manager_func debug more useful
  drm/radeon: fix incorrect use of the lru_lock
  drm/amdgpu: fix incorrect use of the lru_lock
  drm/amdgpu: move debug print into the MM managers
  drm/amdgpu: move gtt usage tracking into the gtt manager v2
  drm/amdgpu: move vram usage tracking into the vram manager v2
  drm/amdgpu: SHADOW and VRAM_CONTIGUOUS flags shouldn't be used by 
userspace
  drm/amdgpu: cleanup static CSA handling
  drm/amdgpu: remove superflous amdgpu_bo_kmap in the VM
  drm/amdgpu: drop the extra VM huge page flag v2
  drm/amdgpu: separate bo_va structure
  drm/amdgpu: rename VM invalidated to moved
  drm/ttm: use reservation_object_trylock in ttm_bo_individualize_resv v2

Chunming Zhou (1):
  drm/amdgpu: save list length when fence is signaled

Ken Wang (1):
  drm/amdgpu: fix vega10 graphic hang issue in S3 test

Leo Liu (2):
  drm/amdgpu: add MJPEG check for UVD physical mode msg buffer
  drm/amdgpu: bump version for support of UVD MJPEG decode

Roger He (2):
  drm/amd/amdgpu: store fragment_size in vm_manager
  drm/amd/amdgpu: expose fragment size as module parameter (v2)

Tom St Denis (1):
  drm/amd/amdgpu: Add tracepoint for DMA page mapping (v4)

Xiangliang.Yu (1):
  drm/ttm: Fix accounting error when fail to get pages for pool

 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c|  29 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   7 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c   |  48 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |  25 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c|  52 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c  |  13 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h |  60 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  76 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  25 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 248 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h|  34 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  |  77 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c  |   7 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |   9 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  11 +-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   |   7 +-
 drivers/gpu/drm/amd/amdgpu/soc15d.h   |   1 +
 drivers/gpu/drm/nouveau/nouveau_ttm.c |   6 +-
 drivers/gpu/drm/radeon/radeon_ttm.c   |  10 +-
 drivers/gpu/drm/ttm/ttm_bo.c  |  64 +--
 drivers/gpu/drm/ttm/ttm_bo_manager.c  |   5 +-
 drivers/gpu/drm/ttm/ttm_page_alloc.c  |   2 +-
 drivers/gpu/drm/virtio/virtgpu_ttm.c  |   2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c |   4 +-
 include/drm/ttm/ttm_bo_driver.h   |   5 +-
 35 files changed, 521 insertions(+), 381 deletions(-)
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[PATCH 0/6 v3] Add ASoC support for AMD Stoney APUs

[Alex Deucher]

This patch set updates the AMD GPU and Audio CoProcessor (ACP)
audio drivers and the designware i2s driver for Stoney (ST).
ST is an APU similar to Carrizo (CZ) which already has ACP audio
support.  The i2s controller and ACP audio DMA engine are part of
the GPU and both need updating so I would like to upstream the
whole patch set via one tree if possible.

The current code is based on drm-next, but I'm happy to rebase on
whatever tree this ends up going through if there are any problems
applying.  These patches touch both audio and drm.

The entire patch set can be viewed here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=stoney_acp2

Thanks!

Alex

v2:
- Patch 1 is already applied to the audio tree, just including it for
  completeness since it's required for this patch set and it's not yet
  in the drm tree.
- New patch to share asic types between gpu and audio drivers
- ACPI ID changed for rt5650 machine driver
- Integrate feedback on other patches

v3:
- resend remaining patches that have not been applied yet

Akshu Agrawal (2):
  drm/amdgpu Moving amdgpu asic types to a separate file
  ASoC: AMD: Add machine driver for cz rt5650

Vijendar Mukunda (4):
  drm/amd/amdgpu: Added asic_type as ACP DMA driver platform data
  ASoC: AMD: disabling memory gating in stoney platform
  ASoC: AMD: DMA driver changes for Stoney Platform
  ASoC: AMD: Audio buffer related changes for Stoney

 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c  |   2 +
 drivers/gpu/drm/amd/include/amd_shared.h |  29 +---
 include/drm/amd_asic_type.h  |  52 +++
 sound/soc/amd/Kconfig|   7 +
 sound/soc/amd/Makefile   |   2 +
 sound/soc/amd/acp-pcm-dma.c  | 243 ---
 sound/soc/amd/acp-rt5645.c   | 210 ++
 sound/soc/amd/acp.h  |   9 ++
 8 files changed, 472 insertions(+), 82 deletions(-)
 create mode 100644 include/drm/amd_asic_type.h
 create mode 100644 sound/soc/amd/acp-rt5645.c

-- 
2.5.5

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[PATCH 2/6 v2] drm/amdgpu Moving amdgpu asic types to a separate file

[Alex Deucher]

From: Akshu Agrawal <akshu.agra...@amd.com>

Amdgpu asic types will be required for other drivers too.
Hence, its better to keep it in a separate include file.

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Akshu Agrawal <akshu.agra...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---

v1: New patch to share asic_type definitions between GPU and audio driver.
v2: add R-b, resend

 drivers/gpu/drm/amd/include/amd_shared.h | 29 ++
 include/drm/amd_asic_type.h  | 52 
 2 files changed, 54 insertions(+), 27 deletions(-)
 create mode 100644 include/drm/amd_asic_type.h

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 70e8c20..3a49fbd 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -23,34 +23,9 @@
 #ifndef __AMD_SHARED_H__
 #define __AMD_SHARED_H__
 
-#define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
+#include 
 
-/*
- * Supported ASIC types
- */
-enum amd_asic_type {
-   CHIP_TAHITI = 0,
-   CHIP_PITCAIRN,
-   CHIP_VERDE,
-   CHIP_OLAND,
-   CHIP_HAINAN,
-   CHIP_BONAIRE,
-   CHIP_KAVERI,
-   CHIP_KABINI,
-   CHIP_HAWAII,
-   CHIP_MULLINS,
-   CHIP_TOPAZ,
-   CHIP_TONGA,
-   CHIP_FIJI,
-   CHIP_CARRIZO,
-   CHIP_STONEY,
-   CHIP_POLARIS10,
-   CHIP_POLARIS11,
-   CHIP_POLARIS12,
-   CHIP_VEGA10,
-   CHIP_RAVEN,
-   CHIP_LAST,
-};
+#define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
 
 /*
  * Chip flags
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
new file mode 100644
index 000..599028f
--- /dev/null
+++ b/include/drm/amd_asic_type.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_ASIC_TYPE_H__
+#define __AMD_ASIC_TYPE_H__
+/*
+ * Supported ASIC types
+ */
+enum amd_asic_type {
+   CHIP_TAHITI = 0,
+   CHIP_PITCAIRN,
+   CHIP_VERDE,
+   CHIP_OLAND,
+   CHIP_HAINAN,
+   CHIP_BONAIRE,
+   CHIP_KAVERI,
+   CHIP_KABINI,
+   CHIP_HAWAII,
+   CHIP_MULLINS,
+   CHIP_TOPAZ,
+   CHIP_TONGA,
+   CHIP_FIJI,
+   CHIP_CARRIZO,
+   CHIP_STONEY,
+   CHIP_POLARIS10,
+   CHIP_POLARIS11,
+   CHIP_POLARIS12,
+   CHIP_VEGA10,
+   CHIP_RAVEN,
+   CHIP_LAST,
+};
+
+#endif /*__AMD_ASIC_TYPE_H__ */
-- 
2.5.5

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[PATCH] drm/amdgpu: fix a bogus warning

[Alex Deucher]

Don't validate the default value.  Prevents a needless
warning. Also fix a spelling typo in the warning message.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2554ddf..1a459ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1077,8 +1077,9 @@ static void amdgpu_check_arguments(struct amdgpu_device 
*adev)
}
 
/* valid range is between 4 and 9 inclusive */
-   if (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4) {
-   dev_warn(adev->dev, "valid rang is between 4 and 9\n");
+   if (amdgpu_vm_fragment_size != -1 &&
+   (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
+   dev_warn(adev->dev, "valid range is between 4 and 9\n");
amdgpu_vm_fragment_size = -1;
}
 
-- 
2.5.5

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[pull] radeon and amdgpu drm-next-4.14

[Alex Deucher]

Hi Dave,

More features for 4.14.  Nothing too major here.  I have a few more additional
patches for large page support in vega10 among other things, but they require
some resevation object patches from drm-misc-next, so I'll send that request
once you've pulled the latest drm-misc-next.  Highlights:
- Fixes for ACP audio on stoney
- SR-IOV fixes for vega10
- various powerplay fixes
- lots of code clean up

The following changes since commit 09ef2378dc42339f3871584dc26d27da220277cb:

  Merge tag 'drm-misc-next-2017-08-08' of 
git://anongit.freedesktop.org/git/drm-misc into drm-next (2017-08-10 10:47:33 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.14

for you to fetch changes up to 37899a5254917e17418bbb23086d55e38faaa659:

  drm/amdgpu/gfx7: fix function name (2017-08-15 14:46:23 -0400)


Alex Deucher (10):
  drm/amdgpu: make wb 256bit function names consistent
  drm/amdgpu: drop old ip definitions for gfxhub and mmhub
  drm/amdgpu/sdma4: drop unused register header
  drm/amdgpu/sdma4: set wptr shadow atomically (v2)
  drm/amdgpu/sdma4: drop hdp flush from wptr shadow update
  drm/amdgpu/sdma4: drop allocation of poll_mem_offs
  drm/amdgpu/sdma4: move wptr polling setup
  drm/amdgpu: use 256 bit buffers for all wb allocations (v2)
  drm/amd/powerplay: add CZ profile support
  drm/amdgpu/gfx7: fix function name

Christian König (8):
  drm/amdgpu: cleanup kptr handling
  drm/amdgpu: consistent use u64_to_user_ptr
  drm/amdgpu: move some defines around
  drm/amdgpu: shadow and mn list are mutually exclusive
  drm/amdgpu: improve amdgpu_bo_create_kernel
  drm/amdgpu: add amdgpu_bo_create_reserved
  drm/amdgpu: use amdgpu_bo_create_kernel more often
  drm/amdgpu: use amdgpu_bo_free_kernel more often

Cihangir Akturk (2):
  drm/amdgpu: switch to drm_*{get,put} helpers
  drm/radeon: switch to drm_*{get,put} helpers

Dan Carpenter (1):
  drm/amdgpu: Uninitialized variable in amdgpu_ttm_backend_bind()

Evan Quan (5):
  drm/amdgpu: update vega10 golden setting
  drm/amd/powerplay: updated vega10 fan control
  drm/amd/powerplay: update didt configs
  drm/amdgpu: fix missing endian-safe guard
  drm/amdgpu: jt_size was wrongly counted twice

Felix Kuehling (1):
  drm/amdgpu: Fix KFD initialization for multi-GPU systems

Frank Min (8):
  drm/amdgpu: Clear vce ring wptr for SRIOV
  drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu reset
  drm/amdgpu/vce4: Remove vce interrupt enable related code for sriov
  drm/amdgpu: Skip uvd and vce ring test for SRIOV
  drm/amdgpu: According hardware design revert vce and uvd doorbell 
assignment
  drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOV
  drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOV
  drm/amdgpu/sdma4: Enable sdma poll mem addr on vega10 for SRIOV

Hawking Zhang (1):
  drm/amdgpu: ignore digest_size when loading sdma fw for raven

Huang Rui (1):
  drm/amdgpu: set gfx_v9_0_ip_funcs as static

Jean Delvare (5):
  drm/amdgpu: Fix undue fallthroughs in golden registers initialization
  drm/amdgpu: Fix dce_v6_0_disable_dce warning
  drm/amdgpu: Fix amdgpu_pm_acpi_event_handler warning
  drm/radeon: Make radeon_atif_handler static
  drm/amdgpu: Make amdgpu_atif_handler static

Junwei Zhang (1):
  drm/amd/powerplay: add vclk/dclkSoftMin support for raven

Kent Russell (4):
  drm/amdgpu: Fix stolen typo
  drm/radeon: Fix stolen typo
  drm/amdgpu: Fix preferred typo
  drm/radeon: Fix preferred typo

Leo Liu (1):
  drm/amdgpu: disable vcn power control for now

Rex Zhu (7):
  drm/amd/powerplay: delete PCC error message in smu7_hwmgr.c
  drm/amd/powerplay: fix force dpm level failed on CZ
  drm/amd/powerplay: fix set highest mclk level failed on Vega10
  drm/amd/powerplay: fix PSI not enabled by kmd
  drm/amd/powerplay: fix coccinelle warnings in vega10_hwmgr.c
  drm/amd/powerplay: refine dmesg info under powerplay.
  drm/amd/powerplay: fix coding style in hwmgr.c

Trigger Huang (1):
  drm/amdgpu: don't finish the ring if not initialized

Vijendar Mukunda (2):
  drm/amd/amdgpu: Added a quirk for Stoney platform
  drm/amd/amdgpu: Disabling Power Gating for Stoney platform

Xiangliang.Yu (1):
  drm/amdgpu/dce_virtual: remove error message for vega10

Yong Zhao (3):
  drm/amdgpu: Add support for filling a buffer with 64 bit value
  drm/amdgpu: Add a parameter to amdgpu_bo_create()
  drm/amdgpu: Support IOMMU on Raven

 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 100 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c|  72 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c   |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  40 ++--
 drivers

[PATCH 1/3] drm/amdgpu/gfx8: fix spelling typo in mqd allocation

[Alex Deucher]

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 12 ++--
 drivers/gpu/drm/amd/include/vi_structs.h |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0710b0b..10fa2c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4578,9 +4578,9 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
mqd->compute_misc_reserved = 0x0003;
if (!(adev->flags & AMD_IS_APU)) {
mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
-+ offsetof(struct 
vi_mqd_allocation, dyamic_cu_mask));
++ offsetof(struct 
vi_mqd_allocation, dynamic_cu_mask));
mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
-+ offsetof(struct 
vi_mqd_allocation, dyamic_cu_mask));
++ offsetof(struct 
vi_mqd_allocation, dynamic_cu_mask));
}
eop_base_addr = ring->eop_gpu_addr >> 8;
mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
@@ -4767,8 +4767,8 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring 
*ring)
mutex_unlock(>srbm_mutex);
} else {
memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
-   ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0x;
-   ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0x;
+   ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
+   ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
mutex_lock(>srbm_mutex);
vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v8_0_mqd_init(ring);
@@ -4791,8 +4791,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring 
*ring)
 
if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
-   ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0x;
-   ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0x;
+   ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
+   ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
mutex_lock(>srbm_mutex);
vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v8_0_mqd_init(ring);
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h 
b/drivers/gpu/drm/amd/include/vi_structs.h
index ca93b51..3e606a7 100644
--- a/drivers/gpu/drm/amd/include/vi_structs.h
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -419,8 +419,8 @@ struct vi_mqd_allocation {
struct vi_mqd mqd;
uint32_t wptr_poll_mem;
uint32_t rptr_report_mem;
-   uint32_t dyamic_cu_mask;
-   uint32_t dyamic_rb_mask;
+   uint32_t dynamic_cu_mask;
+   uint32_t dynamic_rb_mask;
 };
 
 struct cz_mqd {
-- 
2.5.5

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[PATCH 3/3] drm/amdgpu/gfx9: adjust mqd allocation size

[Alex Deucher]

to allocate additional space for the dynamic cu masks.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 25 ++---
 drivers/gpu/drm/amd/include/v9_structs.h |  8 
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 69182ee..7c06d1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1346,7 +1346,7 @@ static int gfx_v9_0_sw_init(void *handle)
return r;
 
/* create MQD for all compute queues as wel as KIQ for SRIOV case */
-   r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
+   r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct 
v9_mqd_allocation));
if (r)
return r;
 
@@ -2463,6 +2463,13 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
mqd->compute_static_thread_mgmt_se3 = 0x;
mqd->compute_misc_reserved = 0x0003;
 
+   mqd->dynamic_cu_mask_addr_lo =
+   lower_32_bits(ring->mqd_gpu_addr
+ + offsetof(struct v9_mqd_allocation, 
dynamic_cu_mask));
+   mqd->dynamic_cu_mask_addr_hi =
+   upper_32_bits(ring->mqd_gpu_addr
+ + offsetof(struct v9_mqd_allocation, 
dynamic_cu_mask));
+
eop_base_addr = ring->eop_gpu_addr >> 8;
mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
@@ -2695,7 +2702,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
if (adev->gfx.in_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
-   memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(*mqd));
+   memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(struct v9_mqd_allocation));
 
/* reset ring buffer */
ring->wptr = 0;
@@ -2707,7 +2714,9 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
soc15_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
} else {
-   memset((void *)mqd, 0, sizeof(*mqd));
+   memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
+   ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
+   ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
mutex_lock(>srbm_mutex);
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v9_0_mqd_init(ring);
@@ -2716,7 +2725,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
mutex_unlock(>srbm_mutex);
 
if (adev->gfx.mec.mqd_backup[mqd_idx])
-   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
+   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(struct v9_mqd_allocation));
}
 
return 0;
@@ -2729,7 +2738,9 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring 
*ring)
int mqd_idx = ring - >gfx.compute_ring[0];
 
if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
-   memset((void *)mqd, 0, sizeof(*mqd));
+   memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
+   ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
+   ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
mutex_lock(>srbm_mutex);
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v9_0_mqd_init(ring);
@@ -2737,11 +2748,11 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring 
*ring)
mutex_unlock(>srbm_mutex);
 
if (adev->gfx.mec.mqd_backup[mqd_idx])
-   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
+   memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, 
sizeof(struct v9_mqd_allocation));
} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
-   memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(*mqd));
+   memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], 
sizeof(struct v9_mqd_allocation));
 
/* reset ring buffer */
ring->wptr = 0;
diff --git a/drivers/gpu/drm/amd/include/v9_structs.h 
b/drivers/gpu/drm/amd/include/v9_structs.h
index 56d79db..2fb25ab 100644
--- a/drivers/gpu/drm/amd/include/v9_structs.h
+++ b/drivers/gpu/drm/amd/include/v9_struct

[PATCH 2/3] drm/amdgpu/gfx9: update mqd to include dynamic CU mask

[Alex Deucher]

Necessary for proper operation with KIQ.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/include/v9_structs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/v9_structs.h 
b/drivers/gpu/drm/amd/include/v9_structs.h
index 9a9e6c7..56d79db 100644
--- a/drivers/gpu/drm/amd/include/v9_structs.h
+++ b/drivers/gpu/drm/amd/include/v9_structs.h
@@ -284,8 +284,8 @@ struct v9_mqd {
uint32_t gds_save_mask_hi;
uint32_t ctx_save_base_addr_lo;
uint32_t ctx_save_base_addr_hi;
-   uint32_t reserved_126;
-   uint32_t reserved_127;
+   uint32_t dynamic_cu_mask_addr_lo;
+   uint32_t dynamic_cu_mask_addr_hi;
uint32_t cp_mqd_base_addr_lo;
uint32_t cp_mqd_base_addr_hi;
uint32_t cp_hqd_active;
-- 
2.5.5

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[PATCH] drm/amdgpu: set sched_hw_submission higher for KIQ (v2)

[Alex Deucher]

KIQ doesn't really use the GPU scheduler.  The base
drivers generally use the KIQ ring directly rather than
submitting IBs.  However, amdgpu_sched_hw_submission
(which defaults to 2) limits the number of outstanding
fences to 2.  KFD uses the KIQ for TLB flushes and the
2 fence limit hurts performance when there are several KFD
processes running.

v2: move some expressions to one line
change KIQ sched_hw_submission to at least 16

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 6c5646b..7c251ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -170,6 +170,16 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
 unsigned irq_type)
 {
int r;
+   int sched_hw_submission = amdgpu_sched_hw_submission;
+
+   /* Set the hw submission limit higher for KIQ because
+* it's used for a number of gfx/compute tasks by both
+* KFD and KGD which may have outstanding fences and
+* it doesn't really use the gpu scheduler anyway;
+* KIQ tasks get submitted directly to the ring.
+*/
+   if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+   sched_hw_submission = max(sched_hw_submission, 16);
 
if (ring->adev == NULL) {
if (adev->num_rings >= AMDGPU_MAX_RINGS)
@@ -178,8 +188,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
ring->adev = adev;
ring->idx = adev->num_rings++;
adev->rings[ring->idx] = ring;
-   r = amdgpu_fence_driver_init_ring(ring,
-   amdgpu_sched_hw_submission);
+   r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
if (r)
return r;
}
@@ -218,8 +227,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
return r;
}
 
-   ring->ring_size = roundup_pow_of_two(max_dw * 4 *
-amdgpu_sched_hw_submission);
+   ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
 
ring->buf_mask = (ring->ring_size / 4) - 1;
ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
-- 
2.5.5

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[PATCH 2/2] drm/amdgpu: move default gart size setting into gmc modules

[Alex Deucher]

Move the asic specific code into the IP modules.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 52 
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c| 19 +++-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c| 22 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c| 21 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 16 +-
 6 files changed, 74 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 2027eb0..f437008 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -57,58 +57,6 @@
  */
 
 /**
- * amdgpu_gart_set_defaults - set the default gart_size
- *
- * @adev: amdgpu_device pointer
- *
- * Set the default gart_size based on parameters and available VRAM.
- */
-void amdgpu_gart_set_defaults(struct amdgpu_device *adev)
-{
-   u64 gart_size;
-
-   if (amdgpu_gart_size == -1) {
-   switch (adev->asic_type) {
-#ifdef CONFIG_DRM_AMDGPU_SI
-   case CHIP_HAINAN:/* no MM engines */
-#endif
-   case CHIP_TOPAZ: /* no MM engines */
-   case CHIP_POLARIS11: /* all engines support GPUVM */
-   case CHIP_POLARIS10: /* all engines support GPUVM */
-   case CHIP_POLARIS12: /* all engines support GPUVM */
-   case CHIP_VEGA10:/* all engines support GPUVM */
-   default:
-   gart_size = 256;
-   break;
-#ifdef CONFIG_DRM_AMDGPU_SI
-   case CHIP_VERDE:/* UVD, VCE do not support GPUVM */
-   case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
-   case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
-   case CHIP_OLAND:/* UVD, VCE do not support GPUVM */
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
-   case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
-   case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
-   case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
-   case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
-   case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
-#endif
-   case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
-   case CHIP_FIJI:/* UVD, VCE do not support GPUVM */
-   case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG 
support */
-   case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG 
support */
-   case CHIP_RAVEN:   /* DCE SG support */
-   gart_size = 1024;
-   break;
-   }
-   } else {
-   gart_size = amdgpu_gart_size;
-   }
-
-   adev->mc.gart_size = gart_size << 20;
-}
-
-/**
  * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
  *
  * @adev: amdgpu_device pointer
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index d4cce69..afbe803 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -56,7 +56,6 @@ struct amdgpu_gart {
const struct amdgpu_gart_funcs *gart_funcs;
 };
 
-void amdgpu_gart_set_defaults(struct amdgpu_device *adev);
 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 6e68579..58fe8cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -332,7 +332,24 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.visible_vram_size = adev->mc.aper_size;
 
-   amdgpu_gart_set_defaults(adev);
+   /* set the gart size */
+   if (amdgpu_gart_size == -1) {
+   switch (adev->asic_type) {
+   case CHIP_HAINAN:/* no MM engines */
+   default:
+   adev->mc.gart_size = 256ULL << 20;
+   break;
+   case CHIP_VERDE:/* UVD, VCE do not support GPUVM */
+   case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
+   case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
+   case CHIP_OLAND:/* UVD, VCE do not support GPUVM */
+   adev->mc.gart_size = 1024ULL << 20;
+   break;
+   }
+   } else {
+   adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+   }
+
gmc_v6_0_vram_gtt_location(adev, >mc);
 
  

[PATCH 1/2] drm/amdgpu: refine default gart size

[Alex Deucher]

Be more explicit and add comments explaining each case.
Also s/gart/GART/ in the parameter string as per Felix'
suggestion.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 38 +++-
 2 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7d5b008..21116fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -129,7 +129,7 @@ module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
-MODULE_PARM_DESC(gartsize, "Size of gart to setup in megabytes (32, 64, etc., 
-1=auto)");
+MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index b9b9f68..2027eb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -68,13 +68,39 @@ void amdgpu_gart_set_defaults(struct amdgpu_device *adev)
u64 gart_size;
 
if (amdgpu_gart_size == -1) {
-   /* make the GART larger for chips that
-* dont' support VM for all rings
-*/
-   if (adev->asic_type <= CHIP_STONEY)
-   gart_size = 1024;
-   else
+   switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+   case CHIP_HAINAN:/* no MM engines */
+#endif
+   case CHIP_TOPAZ: /* no MM engines */
+   case CHIP_POLARIS11: /* all engines support GPUVM */
+   case CHIP_POLARIS10: /* all engines support GPUVM */
+   case CHIP_POLARIS12: /* all engines support GPUVM */
+   case CHIP_VEGA10:/* all engines support GPUVM */
+   default:
gart_size = 256;
+   break;
+#ifdef CONFIG_DRM_AMDGPU_SI
+   case CHIP_VERDE:/* UVD, VCE do not support GPUVM */
+   case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
+   case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
+   case CHIP_OLAND:/* UVD, VCE do not support GPUVM */
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+   case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
+   case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
+   case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
+   case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
+   case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
+#endif
+   case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
+   case CHIP_FIJI:/* UVD, VCE do not support GPUVM */
+   case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG 
support */
+   case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG 
support */
+   case CHIP_RAVEN:   /* DCE SG support */
+   gart_size = 1024;
+   break;
+   }
} else {
gart_size = amdgpu_gart_size;
}
-- 
2.5.5

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Re: [PATCH] drm/amd/include: Add hdmi_redriver_set to atomfirmware

[Alex Deucher]

On Tue, Aug 22, 2017 at 9:35 AM, Harry Wentland <harry.wentl...@amd.com> wrote:
> We'll need this for a some upcoming display changes
>
> Signed-off-by: Harry Wentland <harry.wentl...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/include/atomfirmware.h | 19 ++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
> b/drivers/gpu/drm/amd/include/atomfirmware.h
> index 837296db9628..7c92f4707085 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -1017,6 +1017,19 @@ struct atom_14nm_combphy_tmds_vs_set
>uint8_t margin_deemph_lane0__deemph_sel_val;
>  };
>
> +struct atom_i2c_reg_info {
> +  uint8_t ucI2cRegIndex;
> +  uint8_t ucI2cRegVal;
> +};
> +
> +struct atom_hdmi_retimer_redriver_set {
> +  uint8_t HdmiSlvAddr;
> +  uint8_t HdmiRegNum;
> +  uint8_t Hdmi6GRegNum;
> +  struct atom_i2c_reg_info HdmiRegSetting[9];//For non 6G Hz use
> +  struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];//For 6G Hz use.
> +};
> +
>  struct atom_integrated_system_info_v1_11
>  {
>struct  atom_common_table_header  table_header;
> @@ -1052,7 +1065,11 @@ struct atom_integrated_system_info_v1_11
>struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
>struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
>struct atom_camera_data  camera_info;
> -  uint32_t  reserved[138];
> +  struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
> +  struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
> +  struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
> +  struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
> +  uint32_t  reserved[108];
>  };
>
>
> --
> 2.11.0
>
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[PATCH] drm/amdgpu: set sched_hw_submission higher for KIQ

[Alex Deucher]

KIQ doesn't really use the GPU scheduler.  The base
drivers generally use the KIQ ring directly rather than
submitting IBs.  However, amdgpu_sched_hw_submission
(which defaults to 2) limits the number of outstanding
fences to 2.  KFD uses the KIQ for TLB flushes and the
2 fence limit hurts performance when there are several KFD
processes running.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 6c5646b..f39b851 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -170,6 +170,16 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
 unsigned irq_type)
 {
int r;
+   int sched_hw_submission = amdgpu_sched_hw_submission;
+
+   /* Set the hw submission limit higher for KIQ because
+* it's used for a number of gfx/compute tasks by both
+* KFD and KGD which may have outstanding fences and
+* it doesn't really use the gpu scheduler anyway;
+* KIQ tasks get submitted directly to the ring.
+*/
+   if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+   sched_hw_submission *= 2;
 
if (ring->adev == NULL) {
if (adev->num_rings >= AMDGPU_MAX_RINGS)
@@ -179,7 +189,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
ring->idx = adev->num_rings++;
adev->rings[ring->idx] = ring;
r = amdgpu_fence_driver_init_ring(ring,
-   amdgpu_sched_hw_submission);
+ sched_hw_submission);
if (r)
return r;
}
@@ -219,7 +229,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
}
 
ring->ring_size = roundup_pow_of_two(max_dw * 4 *
-amdgpu_sched_hw_submission);
+sched_hw_submission);
 
ring->buf_mask = (ring->ring_size / 4) - 1;
ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
-- 
2.5.5

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[PATCH] drm/amdgpu: disable DC on KB/ML for now

[Alex Deucher]

Until I've had time to test it better.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=102372

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 119542f..158c1ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1954,8 +1954,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type 
asic_type)
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
-   case CHIP_KABINI:
-   case CHIP_MULLINS:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
@@ -1965,6 +1963,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type 
asic_type)
case CHIP_FIJI:
case CHIP_VEGA10:
return amdgpu_dc != 0;
+   case CHIP_KABINI:
+   case CHIP_MULLINS:
+   return amdgpu_dc > 0;
 #endif
 #if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
-- 
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Re: [PATCH] drm/amdgpu/gfx: drop max_gs_waves_per_vgt

[Alex Deucher]

On Wed, May 3, 2017 at 8:41 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> On 02.05.2017 21:50, Alex Deucher wrote:
>>
>> We already have this info: max_gs_threads.  Drop the duplicate.
>
>
> max_gs_waves_per_vgt seems to be the better name for this number though.
> Threads is usually what we call an item, of which each wave has 64.

I could change it, but it'd more invasive since I'd have to change all
the previous asics.

Alex

>
> Cheers,
> Nicolai
>
>
>>
>> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 1 -
>>  3 files changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 0ee4d87..e7fe649 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -972,7 +972,6 @@ struct amdgpu_gfx_config {
>> unsigned num_rbs;
>> unsigned gs_vgt_table_depth;
>> unsigned gs_prim_buffer_depth;
>> -   unsigned max_gs_waves_per_vgt;
>>
>> uint32_t tile_mode_array[32];
>> uint32_t macrotile_mode_array[16];
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> index d40b8ac..8d7e4d4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> @@ -560,7 +560,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>> void *data, struct drm_file
>> dev_info.num_tcc_blocks =
>> adev->gfx.config.max_texture_channel_caches;
>> dev_info.gs_vgt_table_depth =
>> adev->gfx.config.gs_vgt_table_depth;
>> dev_info.gs_prim_buffer_depth =
>> adev->gfx.config.gs_prim_buffer_depth;
>> -   dev_info.max_gs_waves_per_vgt =
>> adev->gfx.config.max_gs_waves_per_vgt;
>> +   dev_info.max_gs_waves_per_vgt =
>> adev->gfx.config.max_gs_threads;
>>
>> return copy_to_user(out, _info,
>> min((size_t)size, sizeof(dev_info))) ?
>> -EFAULT : 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 2b2a2c2..8b281df 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -796,7 +796,6 @@ static void gfx_v9_0_gpu_early_init(struct
>> amdgpu_device *adev)
>> adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
>> adev->gfx.config.gs_vgt_table_depth = 32;
>> adev->gfx.config.gs_prim_buffer_depth = 1792;
>> -   adev->gfx.config.max_gs_waves_per_vgt = 32;
>> gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
>> break;
>> default:
>>
>
>
> --
> Lerne, wie die Welt wirklich ist,
> Aber vergiss niemals, wie sie sein sollte.
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Re: [PATCH 1/6] drm/amdgpu:fix cannot receive rcv/ack irq bug

[Alex Deucher]

On Tue, May 2, 2017 at 11:48 PM, Monk Liu <monk@amd.com> wrote:
> Change-Id: Ie8672e0c9358d9542810ce05c822d9367249bbd7
> Signed-off-by: Monk Liu <monk@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
> index 1493301..712f36e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
> @@ -296,11 +296,11 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device 
> *adev)
>  {
> int r;
>
> -   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, 
> >virt.rcv_irq);
> +   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 135, 
> >virt.rcv_irq);
> if (r)
> return r;
>
> -   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, 
> >virt.ack_irq);
> +   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, 
> >virt.ack_irq);
> if (r) {
> amdgpu_irq_put(adev, >virt.rcv_irq, 0);
> return r;
> --
> 2.7.4
>
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Re: [PATCH 2/6] drm/amdgpu:need som change on vega10 mailbox

[Alex Deucher]

On Wed, May 3, 2017 at 5:05 AM, Christian König <deathsim...@vodafone.de> wrote:
> Am 03.05.2017 um 05:48 schrieb Monk Liu:
>>
>> if sriov gpu reset is invoked by job timeout, it is run
>> in a global work-queue which is very slow and better not call
>> msleep ortherwise it takes long time to get back CPU.
>>
>> so make below changes:
>>
>> 1: Change msleep 1 to mdelay 5
>> 2: Ignore the ack fail from pf after time out,
>> because VF FLR will clear ack, sometime VF FLR is done
>> prior to the beginning of poll_ack so we can ignore this ack
>>
>> TODO:
>> Put job_timedout (and the following gpu reset) in a driver thread,
>> instead of the global work_struct.
>>
>> Change-Id: I4608c67b55c67c88597e03eee35a126d7e850839
>> Signed-off-by: Monk Liu <monk@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 18 ++
>>   drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 10 +-
>>   2 files changed, 15 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>> index 712f36e..e967a7b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>> @@ -124,8 +124,8 @@ static int xgpu_ai_poll_ack(struct amdgpu_device
>> *adev)
>> r = -ETIME;
>> break;
>> }
>> -   msleep(1);
>> -   timeout -= 1;
>> +   mdelay(5);
>> +   timeout -= 5;
>> reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
>>
>> mmBIF_BX_PF0_MAILBOX_CONTROL));
>> @@ -141,12 +141,12 @@ static int xgpu_ai_poll_msg(struct amdgpu_device
>> *adev, enum idh_event event)
>> r = xgpu_ai_mailbox_rcv_msg(adev, event);
>> while (r) {
>> if (timeout <= 0) {
>> -   pr_err("Doesn't get ack from pf.\n");
>> +   pr_err("Doesn't get msg:%d from pf.\n", event);
>> r = -ETIME;
>> break;
>> }
>> -   msleep(1);
>> -   timeout -= 1;
>> +   mdelay(5);
>> +   timeout -= 5;
>> r = xgpu_ai_mailbox_rcv_msg(adev, event);
>> }
>> @@ -165,7 +165,7 @@ static int xgpu_ai_send_access_requests(struct
>> amdgpu_device *adev,
>> /* start to poll ack */
>> r = xgpu_ai_poll_ack(adev);
>> if (r)
>> -   return r;
>> +   pr_err("Doesn't get ack from pf, continue\n");
>> xgpu_ai_mailbox_set_valid(adev, false);
>>   @@ -174,8 +174,10 @@ static int xgpu_ai_send_access_requests(struct
>> amdgpu_device *adev,
>> req == IDH_REQ_GPU_FINI_ACCESS ||
>> req == IDH_REQ_GPU_RESET_ACCESS) {
>> r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
>> -   if (r)
>> +   if (r) {
>> +   pr_err("Doesn't get READY_TO_ACCESS_GPU from pf,
>> give up\n");
>> return r;
>> +   }
>> }
>> return 0;
>> @@ -211,7 +213,7 @@ static int xgpu_ai_mailbox_ack_irq(struct
>> amdgpu_device *adev,
>> struct amdgpu_irq_src *source,
>> struct amdgpu_iv_entry *entry)
>>   {
>> -   DRM_DEBUG("get ack intr and do nothing.\n");
>> +   printk("get ack intr and do nothing.\n");
>
>
> Changing a DRM_DEBUG to a printk looks odd. How about using pr_warn or
> pr_info instead?
>
> Apart from that patch looks good to me, but I don't deeply into that stuff.
>
> So with the printk fixed feel free to add an Acked-by: Christian König
> <christian.koe...@amd.com> to it.

Same here.  with that fixed:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>

>
> Regards,
> Christian.
>
>
>> return 0;
>>   }
>>   diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>> index 7bdc51b..f0d64f1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>> @@ -398,8 +398,8 @@ static int xgpu_vi_poll_ack(struct amdgpu_device
>> *adev)
>> r = -ETIME;
>> break;
>>

Re: [PATCH 3/6] drm/amdgpu:re-write sriov_reinit_early/late

[Alex Deucher]

On Wed, May 3, 2017 at 5:10 AM, Liu, Monk <monk@amd.com> wrote:
> It's correct and already working  on vega10/tonga for days,
> In fact the guilty context already works at my side

Need to use ARRAY_SIZE for the the loops rather than open coding it.
Beyond that, if it works for sr-iov, it's fine.  Maybe we can look at
unifying things for sr-iov and bare metal in this case in the future.
With the ARRAY_SIZE change:

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

Alex

>
> BR Monk
>
>
>
> -Original Message-
> From: Christian König [mailto:deathsim...@vodafone.de]
> Sent: Wednesday, May 03, 2017 5:02 PM
> To: Liu, Monk <monk@amd.com>; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 3/6] drm/amdgpu:re-write sriov_reinit_early/late
>
> Am 03.05.2017 um 05:48 schrieb Monk Liu:
>> 1,this way we make those routines compatible with the sequence
>>requirment for both Tonga and Vega10 2,ignore PSP hw init when
>> doing TDR, because for SR-IOV device the ucode won't get lost after VF
>> FLR, so no need to invoke PSP doing the ucode reloading again.
>>
>> Signed-off-by: Monk Liu <monk@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 63 
>> ++
>>   1 file changed, 39 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 5161c20..5573792 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1718,19 +1718,27 @@ static int amdgpu_sriov_reinit_early(struct 
>> amdgpu_device *adev)
>>   {
>>   int i, r;
>>
>> - for (i = 0; i < adev->num_ip_blocks; i++) {
>> - if (!adev->ip_blocks[i].status.valid)
>> - continue;
>> -
>> - if (adev->ip_blocks[i].version->type == 
>> AMD_IP_BLOCK_TYPE_COMMON ||
>> - adev->ip_blocks[i].version->type == 
>> AMD_IP_BLOCK_TYPE_GMC ||
>> - adev->ip_blocks[i].version->type == 
>> AMD_IP_BLOCK_TYPE_IH)
>> - r = adev->ip_blocks[i].version->funcs->hw_init(adev);
>> + static enum amd_ip_block_type ip_order[] = {
>> + AMD_IP_BLOCK_TYPE_GMC,
>> + AMD_IP_BLOCK_TYPE_COMMON,
>> + AMD_IP_BLOCK_TYPE_GFXHUB,
>> + AMD_IP_BLOCK_TYPE_MMHUB,
>> + AMD_IP_BLOCK_TYPE_IH,
>> + };
>> +
>> + for (i = 0; i < sizeof(ip_order)/sizeof(ip_order[0]); i++) {
>
> You should use ARRAY_SIZE here instead.
>
>> + int j;
>> + struct amdgpu_ip_block *block;
>> +
>> + for (j = 0; j < adev->num_ip_blocks; j++) {
>> + block = >ip_blocks[j];
>> +
>> + if (block->version->type != ip_order[i] ||
>> + !block->status.valid)
>> + continue;
>>
>> - if (r) {
>> - DRM_ERROR("resume of IP block <%s> failed %d\n",
>> -   adev->ip_blocks[i].version->funcs->name, r);
>> - return r;
>> + r = block->version->funcs->hw_init(adev);
>> + DRM_INFO("RE-INIT: %s %s\n", 
>> block->version->funcs->name,
>> +r?"failed":"successed");
>>   }
>>   }
>>
>> @@ -1741,20 +1749,27 @@ static int amdgpu_sriov_reinit_late(struct 
>> amdgpu_device *adev)
>>   {
>>   int i, r;
>>
>> - for (i = 0; i < adev->num_ip_blocks; i++) {
>> - if (!adev->ip_blocks[i].status.valid)
>> - continue;
>> + static enum amd_ip_block_type ip_order[] = {
>> + AMD_IP_BLOCK_TYPE_SMC,
>> + AMD_IP_BLOCK_TYPE_DCE,
>> + AMD_IP_BLOCK_TYPE_GFX,
>> + AMD_IP_BLOCK_TYPE_SDMA,
>> + AMD_IP_BLOCK_TYPE_VCE,
>> + };
>>
>> - if (adev->ip_blocks[i].version->type == 
>> AMD_IP_BLOCK_TYPE_COMMON ||
>> - adev->ip_blocks[i].version->type == 
>> AMD_IP_BLOCK_TYPE_GMC ||
>> - adev->ip_blocks[i].version->type == 
>> AMD_IP_BLOCK_TYPE_IH )
>> - continue;
>> + for (i = 0; i < sizeof(ip_orde

Re: [PATCH 4/6] drm/amdgpu:cleanups KIQ ring_funcs emit_frame_size

[Alex Deucher]

On Tue, May 2, 2017 at 11:48 PM, Monk Liu <monk@amd.com> wrote:
> since we don't need hdp flush/inval for KIQ anymore
>
> Change-Id: I8518f479afebb73c68ef922880f92dae53b665b9
> Signed-off-by: Monk Liu <monk@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 --
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
>  2 files changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 9629f3a..022a319 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6988,8 +6988,6 @@ static const struct amdgpu_ring_funcs 
> gfx_v8_0_ring_funcs_kiq = {
> .set_wptr = gfx_v8_0_ring_set_wptr_compute,
> .emit_frame_size =
> 20 + /* gfx_v8_0_ring_emit_gds_switch */
> -   7 + /* gfx_v8_0_ring_emit_hdp_flush */
> -   5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
> 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
> 17 + /* gfx_v8_0_ring_emit_vm_flush */
> 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, 
> vm fence */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2b2a2c2..6d5b66c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3620,8 +3620,6 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_kiq = {
> .set_wptr = gfx_v9_0_ring_set_wptr_compute,
> .emit_frame_size =
> 20 + /* gfx_v9_0_ring_emit_gds_switch */
> -   7 + /* gfx_v9_0_ring_emit_hdp_flush */
> -   5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
> 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
> 24 + /* gfx_v9_0_ring_emit_vm_flush */
> 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, 
> vm fence */
> --
> 2.7.4
>
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Re: [PATCH 6/6] drm/amdgpu:PTE flag should be 64 bit width

[Alex Deucher]

On Tue, May 2, 2017 at 11:48 PM, Monk Liu <monk@amd.com> wrote:
> otherwise we'll lost the high 32 bit for pte, which lead
> to incorrect MTYPE for vega10.
>
> Change-Id: I1b0c7b8df14e340a36d4d2a72c6c03f469fdc29c
> Signed-off-by: Monk Liu <monk@amd.com>
> Reviewed-by: Christian König <christian.koe...@amd.com>

Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 11c6c44..c3fb2f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -765,7 +765,7 @@ int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
>  {
> struct amdgpu_ttm_tt *gtt, *tmp;
> struct ttm_mem_reg bo_mem;
> -   uint32_t flags;
> +   uint64_t flags;
> int r;
>
> bo_mem.mem_type = TTM_PL_TT;
> --
> 2.7.4
>
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[PATCH] drm/amdgpu: properly byteswap gpu_info firmware

[Alex Deucher]

It's stored in LE format.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d95d4c9..8a5bb42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1459,19 +1459,19 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
(const struct gpu_info_firmware_v1_0 *)(fw->data +

le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 
-   adev->gfx.config.max_shader_engines = gpu_info_fw->gc_num_se;
-   adev->gfx.config.max_cu_per_sh = gpu_info_fw->gc_num_cu_per_sh;
-   adev->gfx.config.max_sh_per_se = gpu_info_fw->gc_num_sh_per_se;
-   adev->gfx.config.max_backends_per_se = 
gpu_info_fw->gc_num_rb_per_se;
+   adev->gfx.config.max_shader_engines = 
le32_to_cpu(gpu_info_fw->gc_num_se);
+   adev->gfx.config.max_cu_per_sh = 
le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
+   adev->gfx.config.max_sh_per_se = 
le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
+   adev->gfx.config.max_backends_per_se = 
le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
adev->gfx.config.max_texture_channel_caches =
-   gpu_info_fw->gc_num_tccs;
-   adev->gfx.config.max_gprs = gpu_info_fw->gc_num_gprs;
-   adev->gfx.config.max_gs_threads = 
gpu_info_fw->gc_num_max_gs_thds;
-   adev->gfx.config.gs_vgt_table_depth = 
gpu_info_fw->gc_gs_table_depth;
-   adev->gfx.config.gs_prim_buffer_depth = 
gpu_info_fw->gc_gsprim_buff_depth;
+   le32_to_cpu(gpu_info_fw->gc_num_tccs);
+   adev->gfx.config.max_gprs = 
le32_to_cpu(gpu_info_fw->gc_num_gprs);
+   adev->gfx.config.max_gs_threads = 
le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
+   adev->gfx.config.gs_vgt_table_depth = 
le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
+   adev->gfx.config.gs_prim_buffer_depth = 
le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
adev->gfx.config.double_offchip_lds_buf =
-   gpu_info_fw->gc_double_offchip_lds_buffer;
-   adev->gfx.cu_info.wave_front_size = gpu_info_fw->gc_wave_size;
+   le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
+   adev->gfx.cu_info.wave_front_size = 
le32_to_cpu(gpu_info_fw->gc_wave_size);
break;
}
default:
-- 
2.5.5

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Re: [PATCH 2/2] drm/amdgpu: export test ring debugfs interface

[Alex Deucher]

On Wed, May 10, 2017 at 10:56 PM, Huang Rui <ray.hu...@amd.com> wrote:
> On Thu, May 11, 2017 at 10:41:42AM +0800, Deucher, Alexander wrote:
>> > -Original Message-
>> > From: Deucher, Alexander
>> > Sent: Wednesday, May 10, 2017 10:38 PM
>> > To: Huang, Ray; amd-gfx@lists.freedesktop.org; Koenig, Christian
>> > Cc: Zhou, David(ChunMing); Wang, Ken; Huan, Alvin; Huang, Ray
>> > Subject: RE: [PATCH 2/2] drm/amdgpu: export test ring debugfs interface
>> >
>> > > -Original Message-
>> > > From: Huang Rui [mailto:ray.hu...@amd.com]
>> > > Sent: Wednesday, May 10, 2017 10:29 PM
>> > > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
>> > > Cc: Zhou, David(ChunMing); Wang, Ken; Huan, Alvin; Huang, Ray
>> > > Subject: [PATCH 2/2] drm/amdgpu: export test ring debugfs interface
>> > >
>> > > Signed-off-by: Huang Rui <ray.hu...@amd.com>
>> >
>> > Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
>>
>> Not sure if it's important for this since it's debugfs, but we don't have any
>> sort of ring locks anymore (since everything should go through the scheduler
>> once it's started) so we could theoretically get collisions if there are 
>> active
>> apps using the GPU and you run these tests.
>>
>
> Right. Any idea to hold on scheduler when I try to run this test?

Park the scheduler thread for each ring like we do for GPU reset?
That said, I think the expectation is that you should only run these
tests when the GPU is idle.

Alex
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[PATCH 2/4] drm/radeon/ci: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/radeon/ci_dpm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 7ba4508..5ced733 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -776,6 +776,12 @@ bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
u32 vblank_time = r600_dpm_get_vblank_time(rdev);
u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 
+   /* disable mclk switching if the refresh is >120Hz, even if the
+* blanking period would allow it
+*/
+   if (r600_dpm_get_vrefresh(rdev) > 120)
+   return false;
+
if (vblank_time < switch_limit)
return true;
else
-- 
2.5.5

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[PATCH 2/5] drm/amdgpu/gfx9: wait once for all KCQs to be created

[Alex Deucher]

Rather than waiting for each queue.

Reviewed-by: monk liu <monk@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 60 +--
 1 file changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2881e1c..7be71fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2530,11 +2530,9 @@ static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
return r;
 }
 
-static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
-struct amdgpu_ring *ring)
+static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev)
 {
-   struct amdgpu_device *adev = kiq_ring->adev;
-   uint64_t mqd_addr, wptr_addr;
+   struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
uint32_t scratch, tmp = 0;
int r, i;
 
@@ -2545,33 +2543,36 @@ static int gfx_v9_0_map_queue_enable(struct amdgpu_ring 
*kiq_ring,
}
WREG32(scratch, 0xCAFEDEAD);
 
-   r = amdgpu_ring_alloc(kiq_ring, 10);
+   r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 3);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
amdgpu_gfx_scratch_free(adev, scratch);
return r;
}
 
-   mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
-   wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-
-   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
-   /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
-   amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
- PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
- PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
- PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
- PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
- PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
- PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: 
normal compute queue */
- PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: 
all_on_one_pipe */
- PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: 
compute */
- PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: 
must be 1 */
-   amdgpu_ring_write(kiq_ring, 
PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
-   amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
-   amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+   struct amdgpu_ring *ring = >gfx.compute_ring[i];
+   uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+   uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+
+   amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
+   /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
+   amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, 
num_Q: 1 */
+ PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* 
Queue_Sel */
+ PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
+ PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
+ PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
+ PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 
1)) |
+ PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 
/*queue_type: normal compute queue */
+ PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc 
format: all_on_one_pipe */
+ PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* 
engine_sel: compute */
+ PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* 
num_queues: must be 1 */
+   amdgpu_ring_write(kiq_ring, 
PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
+   amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
+   amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
+   amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
+   amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+   }
/* write to scratch for completion */
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
@@ -2874,10 +2875,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring 
*ring)
 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 {
struct amdgpu_device *a

[PATCH 4/4] drm/amd/powerplay/smu7: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index d745065..98a1463 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2793,7 +2793,8 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
 
disable_mclk_switching = ((1 < info.display_count) ||
  disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us));
+ smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us) ||
+ (mode_info.refresh_rate > 120));
 
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.5.5

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[PATCH 1/4] drm/amdgpu/ci: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 6dc1410..eb5d03b 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -906,6 +906,12 @@ static bool ci_dpm_vblank_too_short(struct amdgpu_device 
*adev)
u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 
300;
 
+   /* disable mclk switching if the refresh is >120Hz, even if the
+* blanking period would allow it
+*/
+   if (amdgpu_dpm_get_vrefresh(adev) > 120)
+   return false;
+
if (vblank_time < switch_limit)
return true;
else
-- 
2.5.5

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[PATCH 3/4] drm/amd/powerplay/smu7: add vblank check for mclk switching

[Alex Deucher]

Check to make sure the vblank period is long enough to support
mclk switching.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 31 +---
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a74a3db..d745065 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2655,6 +2655,28 @@ static int smu7_get_power_state_size(struct pp_hwmgr 
*hwmgr)
return sizeof(struct smu7_power_state);
 }
 
+static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
+uint32_t vblank_time_us)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   uint32_t switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
+
+   switch (hwmgr->chip_id) {
+   case CHIP_POLARIS10:
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS12:
+   switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
+   break;
+   default:
+   switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
+   break;
+   }
+
+   if (vblank_time_us < switch_limit_us)
+   return true;
+   else
+   return false;
+}
 
 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *request_ps,
@@ -2669,6 +2691,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
bool disable_mclk_switching;
bool disable_mclk_switching_for_frame_lock;
struct cgs_display_info info = {0};
+   struct cgs_mode_info mode_info = {0};
const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -2677,6 +2700,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
int32_t count;
int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
 
+   info.mode_info = _info;
data->battery_state = (PP_StateUILabel_Battery ==
request_ps->classification.ui_label);
 
@@ -2703,8 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
 
cgs_get_active_displays_info(hwmgr->device, );
 
-   /*TO DO result = PHM_CheckVBlankTime(hwmgr, );*/
-
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
 
@@ -2769,8 +2791,9 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,

PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
 
-   disable_mclk_switching = (1 < info.display_count) ||
-   disable_mclk_switching_for_frame_lock;
+   disable_mclk_switching = ((1 < info.display_count) ||
+ disable_mclk_switching_for_frame_lock ||
+ smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us));
 
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.5.5

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[PATCH libdrm 1/3] amdgpu: add raven family id

[Alex Deucher]

From: Hawking Zhang <hawking.zh...@amd.com>

Signed-off-by: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Chunming Zhou <david1.z...@amd.com>
Reviewed-by: Junwei Zhang <jerry.zh...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 include/drm/amdgpu_drm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 516a9f2..0de4cf6 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -816,6 +816,7 @@ struct drm_amdgpu_info_vce_clock_table {
 #define AMDGPU_FAMILY_VI   130 /* Iceland, Tonga */
 #define AMDGPU_FAMILY_CZ   135 /* Carrizo, Stoney */
 #define AMDGPU_FAMILY_AI   141 /* Vega10 */
+#define AMDGPU_FAMILY_RV   142 /* Raven */
 
 #if defined(__cplusplus)
 }
-- 
2.5.5

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[PATCH libdrm 2/3] amdgpu/drm: add AMDGPU_HW_IP_VCN_DEC

[Alex Deucher]

From: Leo Liu <leo@amd.com>

Signed-off-by: Leo Liu <leo@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 include/drm/amdgpu_drm.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 0de4cf6..add5163 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -406,7 +406,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_HW_IP_UVD  3
 #define AMDGPU_HW_IP_VCE  4
 #define AMDGPU_HW_IP_UVD_ENC  5
-#define AMDGPU_HW_IP_NUM  6
+#define AMDGPU_HW_IP_VCN_DEC  6
+#define AMDGPU_HW_IP_NUM  7
 
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 
-- 
2.5.5

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[PATCH 090/117] drm/amdgpu: add vcn enc ring type and functions

[Alex Deucher]

From: Leo Liu <leo@amd.com>

Add the ring function callbacks for the encode rings.

Signed-off-by: Leo Liu <leo@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h  |   8 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 170 +++
 3 files changed, 180 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7ee501f..b6a2272 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -48,7 +48,8 @@ enum amdgpu_ring_type {
AMDGPU_RING_TYPE_VCE,
AMDGPU_RING_TYPE_KIQ,
AMDGPU_RING_TYPE_UVD_ENC,
-   AMDGPU_RING_TYPE_VCN_DEC
+   AMDGPU_RING_TYPE_VCN_DEC,
+   AMDGPU_RING_TYPE_VCN_ENC
 };
 
 struct amdgpu_device;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 444fed5..d50ba06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -37,6 +37,14 @@
 #define VCN_DEC_CMD_PACKET_START   0x000a
 #define VCN_DEC_CMD_PACKET_END 0x000b
 
+#define VCN_ENC_CMD_NO_OP  0x
+#define VCN_ENC_CMD_END0x0001
+#define VCN_ENC_CMD_IB 0x0002
+#define VCN_ENC_CMD_FENCE  0x0003
+#define VCN_ENC_CMD_TRAP   0x0004
+#define VCN_ENC_CMD_REG_WRITE  0x000b
+#define VCN_ENC_CMD_REG_WAIT   0x000c
+
 struct amdgpu_vcn {
struct amdgpu_bo*vcpu_bo;
void*cpu_addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index b8f4e77..e15a81f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -38,6 +38,7 @@
 static int vcn_v1_0_start(struct amdgpu_device *adev);
 static int vcn_v1_0_stop(struct amdgpu_device *adev);
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
 
 /**
@@ -54,6 +55,7 @@ static int vcn_v1_0_early_init(void *handle)
adev->vcn.num_enc_rings = 2;
 
vcn_v1_0_set_dec_ring_funcs(adev);
+   vcn_v1_0_set_enc_ring_funcs(adev);
vcn_v1_0_set_irq_funcs(adev);
 
return 0;
@@ -688,6 +690,141 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
 }
 
+/**
+ * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc read pointer
+ */
+static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   if (ring == >vcn.ring_enc[0])
+   return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR));
+   else
+   return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2));
+}
+
+ /**
+ * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc write pointer
+ */
+static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   if (ring == >vcn.ring_enc[0])
+   return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR));
+   else
+   return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2));
+}
+
+ /**
+ * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the enc write pointer to the hardware
+ */
+static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   if (ring == >vcn.ring_enc[0])
+   WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR),
+   lower_32_bits(ring->wptr));
+   else
+   WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2),
+   lower_32_bits(ring->wptr));
+}
+
+/**
+ * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write enc a fence and a trap command to the ring.
+ */
+static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+   u64 seq, unsigned flags)
+{
+   WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+   amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
+   amdgpu_ring_write(ring, addr);
+   amdgpu_ring_write(ring, upper_32_bits(addr));
+   amdgpu_ring_write(ring, seq);
+   amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
+}
+
+