Same as other asics. If enabled, exposes a user selectable
number of virtual displays.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/d
Hi Dave,
Just one fix for VCE3.
The following changes since commit 5ed02dbb497422bf225783f46e6eadd237d23d6b:
Linux 4.12-rc3 (2017-05-28 17:20:53 -0700)
are available in the git repository at:
git://people.freedesktop.org/~agd5f/linux drm-fixes-4.12
for you to fetch changes up to
On Thu, Jun 1, 2017 at 4:27 AM, Florian Echtler <f...@butterbrot.org> wrote:
> On 31.05.2017 14:57, Alex Deucher wrote:
>> On Wed, May 31, 2017 at 5:21 AM, Lukas Wunner <lu...@wunner.de> wrote:
>>> On Wed, May 31, 2017 at 10:48:37AM +0200, Florian Echtler
gt; We probably shouldn't really try building this on architectures
>> other than x86.
>
> Does it mean our card including DCN cannot run on other platform like ARM?
The only DCN asics at the moment are APUs so they are only x86.
Alex
>
> Regards,
> David Zhou
>>
>&g
On Wed, May 31, 2017 at 11:10 PM, Ken Wang <qingqing.w...@amd.com> wrote:
> Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
> Signed-off-by: Ken Wang <qingqing.w...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/
LAY].enabled = true;
> + false,
> data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
> + "Attempt to diable LED DPM feature Failed!", return -EINVAL);
"disable"
With that fixed:
Reviewed-by: Alex Deucher <alexander.deuc...
at:
git://people.freedesktop.org/~agd5f/linux drm-next-4.13
for you to fetch changes up to b58c11314a1706bf094c489ef5cb28f76478c704:
drm/amdgpu: drop deprecated drm_get_pci_dev and drm_put_dev (2017-06-08
10:54:39 -0400)
Alex
On Tue, Jun 6, 2017 at 10:03 AM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> On Tue, Jun 6, 2017 at 7:22 AM, Christian König
> <christian.koe...@amd.com> wrote:
>>> Yes, I agree with you. That's also my orignal opinion.
>>> But we encountered
On Tue, Jun 6, 2017 at 7:51 AM, Christian König wrote:
> Am 02.06.2017 um 22:26 schrieb Bjorn Helgaas:
>>
>> On Fri, Jun 02, 2017 at 11:32:21AM +0200, Christian König wrote:
>>>
>>> Hi Bjorn,
>>>
>>> sorry for not responding earlier and thanks for picking this thread
>>>
On Tue, Jun 6, 2017 at 7:22 AM, Christian König
wrote:
>> Yes, I agree with you. That's also my orignal opinion.
>> But we encountered a random buggy when we were calling
>> device_cache_fw_images.
>
> That looks like an upstream bug in device_cache_fw_images.
>
> We
On Tue, Jun 6, 2017 at 10:52 AM, Huang Rui <ray.hu...@amd.com> wrote:
> On Tue, Jun 06, 2017 at 10:45:42PM +0800, Alex Deucher wrote:
>> On Tue, Jun 6, 2017 at 10:03 AM, Alex Deucher <alexdeuc...@gmail.com> wrote:
>> > On Tue, Jun 6, 2017 at 7:22 AM, Christian König
On Mon, Jun 5, 2017 at 10:05 PM, Michel Dänzer wrote:
> On 03/06/17 07:46 AM, Luke Miller wrote:
>>
>> I have a recurring problem with one 3D program (UE4editor) crashing my
>> computer during a particular operation.
>>
>> I believe the problem is at the DRM layer.
>
> It's
The same function was duplicated in all the gfx IPs. Use
a single implementation for all.
Suggested-by: Andres Rodriguez <andre...@gmail.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 13 +
drivers/gpu/dr
The same function was duplicated in all the gfx IPs. Use
a single implementation for all.
v2: use static inline (Alex Xie)
Suggested-by: Andres Rodriguez <andre...@gmail.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgp
silence uninitialized variable warnings.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgp
; * Check and bump table_max_size at the beginning of the while loop [Emil
> Velikov]
> * Initialize table_max_size to the number of entries in data/amdgpu.ids
> v8: [Michel Dänzer]
> * Make sure amdgpu_asic_id.c gets rebuilt when amdgpu.ids changes
>
> Reviewed-by: Alex De
)
Alex Deucher (3):
drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0
drm/amdgpu/gfx9: fix compute ring doorbell index
drm/amdgpu: add virtual display support for raven
Alex Xie (3):
drm/amdgpu: remove duplicate function prototypes
drm/amdgpu: fix a typo
Not used.
Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 --
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 -
drivers
Now that interrupts are properly enabled for all pipes, this
should be function properly.
Cc: Shirish S <shiris...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
Shirish,
Can you test this change on your Stoney setup?
drivers/gpu/drm/amd/amdgpu/amdgp
The interrupt registers are not indexed.
Fixes: 763a47b8e (drm/amdgpu: teach amdgpu how to enable interrupts for any
pipe v3)
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 57 +++--
drivers/gpu/drm/amd/
On Wed, Jun 14, 2017 at 5:43 AM, Rex Zhu <rex@amd.com> wrote:
> Change-Id: I987a53e5185934bdf6926f9d6065d2ec6aca05bb
> Signed-off-by: Rex Zhu <rex@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/powerp
to debug issue.
>
> Thanks,
> Ray
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> b/driv
9a6c84b93 ("drm/radeon: Make display watermark calculations more
> accurate")
> Cc: Ben Hutchings <ben.hutchi...@codethink.co.uk>
> Cc: Alex Deucher <alexander.deuc...@amd.com>
> Cc: sta...@vger.kernel.org
Applied the series. Thanks!
Alex
> ---
> drivers
On Fri, Jun 9, 2017 at 4:59 AM, Christian König wrote:
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
>
> v2: rebased, style cleanups, disable mem decode before resize,
> handle gmc_v9 as well, round size up to
Hi Dave,
A few fixes for 4.12:
- fix a UVD regression on SI
- fix overflow in watermark calcs on large modes
The following changes since commit 6e88007e224ce51969ccf9afeec645146c638816:
Merge branch 'vmwgfx-fixes-4.12' of
git://people.freedesktop.org/~thomash/linux into drm-fixes (2017-06-09
Not used.
v2: include DC as well
v3: handle vega10/RV
Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h |
These are no longer needed now that we use the fb_location
programmed by the vbios.
v2: update DC as well
v3: handle vega10/RV
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_de
Now that the mc_access functions are gone, we no longer
need separate structs for all the different dce families
in dm.
v2: rebase on vega10/RV
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 105 +-
Avoids printing spurious messages like this:
[3.102059] amdgpu :01:00.0: VM size (-1) must be a power of 2
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/d
We were using the wrong structure which lead to an overflow
on some boards.
bug: https://bugs.freedesktop.org/show_bug.cgi?id=101387
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 4 ++--
1 file chan
Increase the default display clock on newer asics to
accomodate some high res modes with really high refresh
rates.
bug: https://bugs.freedesktop.org/show_bug.cgi?id=93826
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/
mr_asic *asic, uint64_t addr)
> {
> - uint32_t value=0;
> - if (addr == 0x)
> - fprintf(stderr, "[BUG]: reading from addr==0x is
> likely a bug\n");
> -
> - if (asic->pci.mem &&am
We are getting the patches out in preparation for open source vulkan.
Additionally Christian has plans to use them in mesa as well.
Alex
On Fri, Jun 16, 2017 at 4:47 AM, He, Roger wrote:
> What is the background or what is it for?
>
>
>
> Thanks
>
> Roger(Hongbo.He)
>
>
On Thu, Jun 15, 2017 at 6:02 PM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> Not used.
>
> v2: include DC as well
> v3: handle vega10/RV
>
> Reviewed-by: Christian König <christian.koe...@amd.com>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com&g
On Wed, Jun 7, 2017 at 5:53 PM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> Same as other asics. If enabled, exposes a user selectable
> number of virtual displays.
>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Ping?
> ---
> drivers/gpu/drm/amd/a
On Mon, Jun 12, 2017 at 1:54 PM, Tom St Denis <tom.stde...@amd.com> wrote:
> These replace some of the more verbose patterns with new SOC15 macros. Should
> be no functional change to anything.
Series is:
Reviewed-by: Alex Deucher <alexander.
On Fri, Jun 9, 2017 at 5:47 PM, Harish Kasiviswanathan
<harish.kasiviswanat...@amd.com> wrote:
> Signed-off-by: Harish Kasiviswanathan <harish.kasiviswanat...@amd.com>
Series is:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/
On Mon, May 1, 2017 at 2:34 AM, Monk Liu <monk@amd.com> wrote:
> Change-Id: Ie8672e0c9358d9542810ce05c822d9367249bbd7
> Signed-off-by: Monk Liu <monk@amd.com>
A couple of comments on patch 3. The rest are:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
_TYPE_COMMON ||
> - adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_GMC ||
> - adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_IH )
> - continue;
> + for (i = 0
Rather than using a hardcoded value.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
Add new RIDs.
Acked-by: Alex Xie <alexbin@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amd
rather than hardcoding it.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8
We already have this info: max_gs_threads. Drop the duplicate.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
3 files changed, 1 ins
Need to use the atomfirmware interface rather than atombios since
soc15 is atomfirmware based.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
Update the scratch reg for when the engine is hung.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/d
it makes sense to change the order globally so we can
avoid things like this and unify the sr-iov code as well. series is:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57
> ++
> 1 file changed,
On Mon, May 8, 2017 at 9:25 AM, Christian König <deathsim...@vodafone.de> wrote:
> From: Christian König <christian.koe...@amd.com>
>
> This kind of reset handling was removed a long time ago.
>
> Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed
On Fri, May 5, 2017 at 10:27 AM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> Update the scratch reg for when the engine is hung.
>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
ping on this series.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu
On Fri, May 5, 2017 at 1:10 PM, Andres Rodriguez wrote:
> Hey Everyone,
>
> On one of the previous comments for this series I received feedback that
> the register programming should be done through the KIQ. This series has
> the relevant changes.
>
> However, register writes
On Thu, May 4, 2017 at 9:14 AM, Christian König
wrote:
> Am 04.05.2017 um 14:52 schrieb Nikola Pajkovsky:
>>
>> else branch is pointless if it's right at the end of function and use
>> unlikely() on err path.
>>
>> Signed-off-by: Nikola Pajkovsky
>
>
> Fixes: bce23e00f3369 ("drm/amdgpu: add NGG parameters")
> Cc: Christian König <christian.koe...@amd.com>
> Cc: Alex Deucher <alexander.deuc...@amd.com>
> Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Applied. thanks!
Alex
> ---
> Another opti
rather than defining it locally.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/d
rom: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Alex Deucher
> Sent: Tuesday, May 02, 2017 6:29 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <alexander.deuc...@amd.com>
> Subject: [PATCH 08/12] drm/amdgpu: split gfx_v9_0_ki
ng PPTable causing a violation.
>
> Change-Id: Ieff3c7ffe58b8ec83127d90ca2bb1761a5c71462
> Signed-off-by: Rex Zhu <rex@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 28
> +++
On Tue, May 2, 2017 at 5:49 AM, Rex Zhu <rex@amd.com> wrote:
> SMU not support FanTargetTemperature in pptable,
> so send msg instand.
>
> Change-Id: Idc9cec95fb8d4f1479f727c8693c1186d28b5435
> Signed-off-by: Rex Zhu <rex@amd.com>
Reviewed-by: Alex Deucher
On Tue, May 2, 2017 at 2:41 AM, Rex Zhu <rex@amd.com> wrote:
> Change-Id: Iae711f1a33264c44a6819f78e345aba50456861f
> Signed-off-by: Rex Zhu <rex@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/ve
On Tue, May 2, 2017 at 2:49 AM, Rex Zhu <rex@amd.com> wrote:
> this value is used by avfs to adjust inversion voltage.
>
> Change-Id: Ic6520c184ae938384d9f5e1590ecaf864fa9f95a
> Signed-off-by: Rex Zhu <rex@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...
in the
driver to support and is required for MEC powergating.
v2: drop gfx_v9_0_cp_compute_fini() as well
v3: rebase on latest changes derived from gfx8, add unmap queues on
hw_fini
v4: fix copy/paste typo in error message (Rex)
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drive
We need to make sure the various init sequences submitted
to KIQ complete before testing the rings.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 89 +++
1 file changed, 79 insertions(+), 10 deletions(-)
One for KIQ and one for the KCQ. This simplifies the logic and
allows for future optimizations.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 63 +++
1 file changed, 42 insertions(+), 21 deletions(-)
Will be used in subsequent commits rather rather than
magic numbers.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15d.h | 82 +
1 file changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15
Rather than waiting for each queue.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 60 +--
1 file changed, 29 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/g
Need to properly set the ROQ space setting.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b
Integrate a fix for gfx8, should apply to 4.11 and drm-next.
Can someone with vega10 access test this?
Thanks,
Alex
Alex Deucher (12):
drm/amdgpu/gfx9: fix typo in mpd init
drm/amdgpu/gfx9: add additional MQD initialization
drm/amdgpu/gfx9: create mqd backups
drm/amdgpu/gfx9: clear
Using the wrong macro for soc15 register access.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
To be consistent with gfx8.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5c9c2bf..842f11e
And properly synchronize them with the master during
queue init.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_
As the KCQ setup. This way we only have to wait once for the
entire MEC.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 73 +++
1 file changed, 14 insertions(+), 59 deletions(-)
diff --git a/drivers/g
Rather than magic numbers.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gf
No need to reset the wptr and clear the rings. The UNMAP_QUEUES
packet writes the current MQD state back the MQD on suspend,
so there is no need to reset it as well.
v2: fix from gfx8 (Rex)
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.
. (2017-05-25 12:53:25
-0400)
Alex Deucher (4):
drm/amdgpu/ci: disable mclk switching for high refresh rates (v2)
drm/radeon/ci: disable mclk switching for high refresh rates (v2)
drm/amd/powerplay/smu7: add vblank
On Wed, May 31, 2017 at 1:15 AM, Michel Dänzer wrote:
> On 31/05/17 07:31 AM, Li, Samuel wrote:
>> From: Michel Dänzer [mailto:mic...@daenzer.net]
>>> On 30/05/17 06:16 AM, Samuel Li wrote:
>>>
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c new
file
On Wed, May 31, 2017 at 7:19 AM, Emil Velikov wrote:
> On 30 May 2017 at 22:59, Li, Samuel wrote:
>>> - Marketing can make mistakes or have IT glitches The inconsistent use of
>>> "(TM)" and using a 67C2:00 is something one wants to double-check
Always use the max for the family rather than the per sku limits.
This makes sure the mask is always the max size to avoid reporting
the wrong number of CUs.
Cc: sta...@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.
0ef1ba9
> Reviewed-by: Junwei Zhang <jerry.zh...@amd.com>
> Signed-off-by: Samuel Li <samuel...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> Makefile.am | 3 +
> amdgpu/Makefile.am
@amd.com>
The code is kind of hard to follow, but it looks good to me:
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> tests/kms_setmode.c | 24 ++--
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/tests/kms_s
On Mon, Jun 5, 2017 at 2:36 PM, Harry Wentland wrote:
> Hi Luke,
>
> the first things to check would be the saved kern.log and Xorg.0.log from
> before the crash occured. Both should be in /var/log. These logs will keep a
> long record but you should be able to find the
On Wed, May 31, 2017 at 10:16 AM, Alex Deucher <alexdeuc...@gmail.com> wrote:
> Always use the max for the family rather than the per sku limits.
> This makes sure the mask is always the max size to avoid reporting
> the wrong number of CUs.
>
> Cc: sta...@vger.kernel.org
On Fri, Sep 8, 2017 at 11:41 AM, Darren Salt wrote:
> Noticed while playing “Valley”, which was causing some 8MB of leakage per
> second. kmemleak listed many entries looking like this:
>
> unreferenced object 0x8802c2951800 (size 1024):
> comm "Xorg", pid
On Wed, Sep 13, 2017 at 4:01 AM, Allen Pais wrote:
> Signed-off-by: Allen Pais
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Wed, Sep 13, 2017 at 2:12 PM, Mark Brown <broo...@kernel.org> wrote:
> On Wed, Sep 13, 2017 at 01:57:49PM -0400, Alex Deucher wrote:
>
>> I just need acks from audio on the remaining patches that touch audio
>> (1, 5, 6), and then I can send a pull request.
>
&
On Tue, Sep 12, 2017 at 7:05 PM, Felix Kuehling <felix.kuehl...@amd.com> wrote:
> Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/radeon/radeon_kfd.c | 31 ++
ace.
>
> PASIDs of different sizes can be requested. On APUs, the PASID size
> is deterined by the capabilities of the IOMMU. So KFD must be able
> to allocate PASIDs in a smaller range.
>
> Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
Acked-by: Alex Deucher <alexander.
lution is supported.
SRAM bank 1 & SRAM bank 2 will be used for playback scenario.
SRAM Bank 3 & SRAM Bank 4 will be used for Capture scenario.
Acked-by: Mark Brown <broo...@kernel.org>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vij
From: Vijendar Mukunda <vijendar.muku...@amd.com>
asic_type information is passed to ACP DMA Driver as platform data.
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deu
From: Vijendar Mukunda <vijendar.muku...@amd.com>
Stoney uses 16kb SRAM memory for playback and 16Kb
for capture.Modified Max buffer size to have the
correct mapping between System Memory and SRAM.
Added snd_pcm_hardware structures for playback
and capture for Stoney.
Reviewed-by: Alex D
From: Akshu Agrawal <akshu.agra...@amd.com>
The driver is used for AMD board using rt5650 codec.
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Akshu Agrawal <akshu.agra...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed
From: Akshu Agrawal <akshu.agra...@amd.com>
Amdgpu asic types will be required for other drivers too.
Hence, its better to keep it in a separate include file.
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Akshu Agrawal <akshu.agra...@amd.com>
Signed-of
ernel.org>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.muku...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
v2: Added comments in code and removed locally defined macros
for STONEY and Carrizo.
v3: add
This patch set updates the AMD GPU and Audio CoProcessor (ACP)
audio drivers and the designware i2s driver for Stoney (ST).
ST is an APU similar to Carrizo (CZ) which already has ACP audio
support. The i2s controller and ACP audio DMA engine are part of
the GPU and both need updating so I would
nt this before patches 2 and 3?
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 -
> drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 50
> +--
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h
On Tue, Sep 12, 2017 at 7:05 PM, Felix Kuehling <felix.kuehl...@amd.com> wrote:
> Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_module.c | 6 ---
> drivers/gpu/dr
On Tue, Sep 12, 2017 at 7:05 PM, Felix Kuehling <felix.kuehl...@amd.com> wrote:
> Make sure vm->root.bo is not left reserved if amdgpu_bo_kmap fails.
>
> Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
On Tue, Sep 12, 2017 at 7:05 PM, Felix Kuehling <felix.kuehl...@amd.com> wrote:
> To filter out high-frequency interrupts that can be safely ignored.
>
> Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
&
t; should be quite cache-friendly, too.
>
> It uses linear probing and lazy deletion. During lookups free space
> is reclaimed and entries relocated to speed up future lookups.
>
> Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
> Acked-by: Christian König <chris
f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
>> Cc: Flora Cui <flora@amd.com>
>> Cc: Junwei Zhang <jerry.zh...@amd.com>
>> Cc: Alex Deucher <alexander.deuc...@amd.com>
>> Cc: Marek Olšák <mar...@gmail.com>
>> ---
>
I6a72d5fc9b653b21c3c98167515a511c5edeb91c
>> Signed-off-by: Horace Chen <horace.c...@amd.com>
>> Signed-off-by: Monk Liu <monk@amd.com>
>
>
> Acked-by: Christian König <christian.koe...@amd.com>, but better wait for
> Alex to have a look as we
On Tue, Sep 19, 2017 at 4:30 AM, Christian König
wrote:
> I don't know why, but the HDP is generally not part of the register spec.
>
> So you can neither find HDP_DEBUG0 nor HDP_READ_CACHE_INVALIDATE in it as
> far as I know.
>
> Point is that the HDP invalidates it's
On Tue, Sep 19, 2017 at 2:41 AM, Monk Liu wrote:
> previously a patch has typo error, correct it
Please squash this into the previous broken patch before committing it.
Alex
>
> Change-Id: I91bcefd7148b5db1c7d957c868e13a46ca40ef74
> Signed-off-by: Monk Liu
It was not clear. The rest of the driver is MIT/X11.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
Dave, any objections?
drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/
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