[Why]
All the HDCP transactions should be verified using PSP
[How]
This patch adds the psp calls we need to verify the steps
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 44 ++
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 502
in the following files:
* clk_mgr/clk_mgr.c: dc_clk_mgr_create()
* core/dc_resources.c: dc_create_resource_pool()
* gpio/hw_factory.c: dal_hw_factory_init()
* gpio/hw_translate.c: dal_hw_translate_init()
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/Kconfig| 18
Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.
Change it to "dcn" to make it generic
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/Kconfig | 4 ++--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
drivers/g
From: abdoulaye berthe
[Why]
The aux timeout value is not default before reading link cap.
Setting it to default when lttpr is not enabled causes some monitor
not to light up.
[How]
Read the aux engine timeout value before setting it to extended.
Set the aux engine timeout to its previous value
FW.
[How]
Add psp version mask 0x00FF00FF for checking version.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Acked-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: David Galiffi
[WHY]
V.Active dram clock change workaround need a small modification for DMLv2
to ensure that the dummy p-state check doesn't fail.
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dml/dcn20
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0416a17b0897..d931e5878b4c 100644
From: Yongqiang Sun
[Why]
DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize
sequence.
[How]
Change dmcu init sequece to meet dmcub initilize.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce
, there is a change for no
flip coming causing display count is 1 in SMU side.
Add optimize bandwidth after commit stream.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions(+)
diff --git
From: abdoulaye berthe
1-If at least one repeater is present in the link and we are in non
transparent mode, perform clock recovery then channel equalization
with all repeaters one by one before training DPRX.
2-Mark the end of LT with a repeater by setting training pattern 0
at the end of
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +--
.../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ---
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
3 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: abdoulaye berthe
[Description]
1-Grant extended timeout request. Done once after detection
2-Configure lttpr mode based on lttpr support before LT
3-Account for lttpr cap when determining max link settings
Signed-off-by: abdoulaye berthe
Reviewed-by: Aric Cyr
---
Summary Of Changes
*configure and init lttpr
*DSC sanity check
*Bandwidth optimization
*Some assert fixes
Anthony Koo (1):
drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC
SDP
Aric Cyr (2):
drm/amd/display: 3.2.57
drm/amd/display: 3.2.58
David Galiffi (2):
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7bf0241999c7..32eafff6b043 100644
us, since DCN2 and greater reports it on the OPP
instead of OTG, we patch it in after calling optc1_read_otg_states.
Ideally, this should be done in the DCN version specific function hooks.
It has been left as a TODO item.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Mikita Lipski
Acked-by: Bhawanpree
From: Jun Lei
[why]
Need it for some OEM I2C devices in Nv10
[how]
Link up code to parse OEM table and expose DC interface
to access the pins
Signed-off-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/bios/bios_parser2.c| 63
is not user visible since it is in
blank region.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 65 ++-
.../drm/amd/display/dc/dcn21
.
[how]
Read back the enable state of DSC HW and report an error if duplicate
enable or disable was attempted.
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 25 ---
1 file changed, 22
From: abdoulaye berthe
1-Read lttpr caps in 5-bytes
2-Parse caps
3-Validate caps and set lttpr_mode
4-Use hw default timeout when lttpr is disabled.
Signed-off-by: abdoulaye berthe
Reviewed-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 90 ++-
From: abdoulaye berthe
[Why]
LTTPR was introduced after DP1.2. Reading LTTPR registers 0xF
on some DP 1.2 display is causing an unexpected behavior.
[How]
Make sure that we don't read any lttpr registers on 1.2 displays.
Signed-off-by: abdoulaye berthe
Reviewed-by: Aric Cyr
---
From: abdoulaye berthe
[Description]
When reading link, update the procedure as follows:
1-Set aux timeout to extended: 3.2ms
2-Start with reading lttpr caps
3-Determine if lttpr support should be enabled. Reset aux timeout to
400us if no repeater is found.
Signed-off-by: abdoulaye berthe
translate into
p_state_change_support: false.
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
.../gpu/drm/amd/display/dc
6.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
.../amd/display/dc/dce/dce_stream_encoder.c
signal_type to SIGNAL_TYPE_NONE unless it is eDP.
Signed-off-by: Sung Lee
Reviewed-by: Yongqiang Sun
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110
The values for bounding box and res_caps were incorrect. So
Fix them
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++-
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
From: Eric Yang
[Why]
Renoir is gfx9, same as dcn10, not dcn20.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
be based only on MP0_BASE data.
[How]
Change MP1_BASE to MP0_BASE
Signed-off-by: joseph gravenor
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h| 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
index
Use requested_dispclk_khz / 1000 directly
Signed-off-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
b/drivers
unnecessary.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers/gpu/drm/amd
Handle 18 DecimalBPP like other cases
Signed-off-by: Bhawanpreet Lakha
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers
it allows us to do urgent latency programming
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 16
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 39 +--
.../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17
.../gpu/drm/amd
From: Dmytro Laktyushkin
Renoir can use vm contexes as long as HOSTVM is off so
this should be initialized.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
fix and check lightup on renoir
*fix aux timeout regression
new patches
drm/amd/display: handle dp is usb-c
drm/amd/display: null check pp_smu clock table before using it
drm/amd/display: disable ext aux support for vega
Bhawanpreet Lakha
From: Lewis Huang
[why]
driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box
[How]
Move the patch function before calculate wm.
Signed-off-by: Lewis Huang
Signed-off-by: joseph graveno
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 25
From: Dmytro Laktyushkin
1 vmid limitation only exists for HOSTVM which is a custom
use case anyway.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: abdoulaye berthe
[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14
From: Lewis Huang
[Why]
Watermarks not propagated to DCHUBP after it is powered on
[How]
Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20
[Why]
DCN20 and DCN21 have different phy programming sequences.
[How]
Create a separate dcn21_link_encoder for Renoir
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +-
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 +
drivers/gpu/drm/amd/display
Detile buffer size affects dcc caps, it was already added for
dcn2. Now add it for dcn21
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
b/drivers
DPM level is 8 these were incorrect before. Fix them
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
This patch adds handling of dp is usb-c, it is not tested but is
needed to support dp over usb-c
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 14 +++
.../amd/display/dc/dcn21/dcn21_link_encoder.c | 93 ++-
.../amd/display/dc/dcn21
From: Eric Yang
[Why]
Handle the case where we don't get a valid table. Also fixes compiler
warning for variable potentially used before assignment.
[How]
If the entire table has no valid fclk, reject the table and use our own
hard code.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/include/renoir_ip_offset.h| 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
index 094648cac392..07633e22e99a 100644
units
Signed-off-by: Michael Strauss
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc
use dcn20 common regs define to share some regs with dcn20
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
b/drivers
Incorrect page table address and programming sys aperture for
stutter gather, so fix it.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 23 ++-
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc
From: Sung Lee
[Why]
Previously only dummy functions were added in Diags for FPGA.
On silicon, this would lead to a segmentation fault on silicon diags.
[How]
Check if diags silicon and if so, add dummy functions.
Signed-off-by: Sung Lee
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd
From: Roman Li
[Why]
Earlier changes to support configurable aux timeout
caused dc init failure on vega due to missing reg defs.
Needs to be disabled until implemented for vega.
[How]
Set extended aux timeout cap for vega to false.
fixes: drm/amd/display: configurable aux timeout support
From: Dmytro Laktyushkin
Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 40
From: abdoulaye berthe
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
drivers
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index
This change adds renoir hw_seq, needed to do renoir
specific hw programing
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
.../drm/amd
From: Lewis Huang
[Why]
SMU fixed this issue after version 0x370c00
[How]
enable smu send message to set dcfclk after smu version 0x370c00
Signed-off-by: Lewis Huang
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4 ++--
1 file changed, 2
From: Eric Yang
[Why]
Handle the case where we don't get a valid table. Also fixes compiler
warning for variable potentially used before assignment.
[How]
If the entire table has no valid fclk, reject the table and use our own
hard code.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
be based only on MP0_BASE data.
[How]
Change MP1_BASE to MP0_BASE
Signed-off-by: joseph gravenor
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr
Hi all,
There was a delta betwwen internal dcn21 code and upstream dcn21 code.
These changes bring them inline.
Summary of Changes
*Add RN registors
*Add dcn12 hwseq and link_encoder
*RN specific fixes
*aux timeout support
*bounding box changes
Bhawanpreet Lakha (12):
drm/amd/display: Add
From: Lewis Huang
[Why]
Watermarks not propagated to DCHUBP after it is powered on
[How]
Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20
This change adds renoir hw_seq, needed to do renoir
specific hw programing
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
.../drm/amd
From: Dmytro Laktyushkin
1 vmid limitation only exists for HOSTVM which is a custom
use case anyway.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
unnecessary.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers/gpu/drm/amd
From: Lewis Huang
[why]
driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box
[How]
Move the patch function before calculate wm.
Signed-off-by: Lewis Huang
Signed-off-by: joseph graveno
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 25
From: Dmytro Laktyushkin
Renoir can use vm contexes as long as HOSTVM is off so
this should be initialized.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
it allows us to do urgent latency programming
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 16
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 39 +--
.../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17
.../gpu/drm/amd
From: Eric Yang
[Why]
Renoir is gfx9, same as dcn10, not dcn20.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/include/renoir_ip_offset.h| 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
index 094648cac392..07633e22e99a 100644
From: abdoulaye berthe
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
drivers
The values for bounding box and res_caps were incorrect. So
Fix them
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++-
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h| 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
index
[Why]
DCN20 and DCN21 have different phy programming sequences.
[How]
Create a separate dcn21_link_encoder for Renoir
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +-
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 +
drivers/gpu/drm/amd/display
DPM level is 8 these were incorrect before. Fix them
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
units
Signed-off-by: Michael Strauss
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc
From: Lewis Huang
[Why]
SMU fixed this issue after version 0x370c00
[How]
enable smu send message to set dcfclk after smu version 0x370c00
Signed-off-by: Lewis Huang
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4 ++--
1 file changed, 2
Handle 18 DecimalBPP like other cases
Signed-off-by: Bhawanpreet Lakha
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers
From: Sung Lee
[Why]
Previously only dummy functions were added in Diags for FPGA.
On silicon, this would lead to a segmentation fault on silicon diags.
[How]
Check if diags silicon and if so, add dummy functions.
Signed-off-by: Sung Lee
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd
Incorrect page table address and programming sys aperture for
stutter gather, so fix it.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 23 ++-
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc
From: abdoulaye berthe
[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14
use dcn20 common regs define to share some regs with dcn20
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
b/drivers
Detile buffer size affects dcc caps, it was already added for
dcn2. Now add it for dcn21
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
b/drivers
Use requested_dispclk_khz / 1000 directly
Signed-off-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
b/drivers
From: Dmytro Laktyushkin
Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 40
).
So this method should be good enough to report HDCP status.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +--
.../gpu/drm/amd/display/modules/hdcp/hdcp.c| 18 ++
.../gpu/drm/amd/display/modules/inc/mod_hdcp.h | 4 ++--
3 files
before executing the current and fix watchdog
event being canceled by callback event
Change-Id: I3c595901d63f3393c83d898cdb2d7dfc1a769142
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
[Why]
We need to log the state changes for 2.2
This patch extends the existing logging functions to handle
HDCP2.2.
[How]
We do this by adding if/else in the defines, and output the log
based on the hdcp version
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/modules/hdcp/hdcp_log.c
e property if the
requirements are met
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 17 +
.../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 4 ++--
.../gpu/drm/amd/display/mo
-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 53 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 9 ++--
3 files changed, 40 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd
[Why]
HDCP 2.2 was disabled, we need to enable it
[How]
-Update display topology to support 2.2
-Unset hdcp2.disable in update_config
-Change logic of event_update_property, now we set the property to be
ENABLED for any level of encryption (2.2 or 1.4).
Signed-off-by: Bhawanpreet Lakha
[Why]
Before we had a disable_type1 flag, this forced HDCP 2.2 to type0
There was no way to force type1.
[How]
Remove disable_type1 flag and instead add a flag to force type0/1.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../drm/amd/display
: Add HDCP module" for 2.2
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/modules/hdcp/Makefile | 3 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 86 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 127 +++
.../display/modules/hdcp/hdcp2_execution.c| 881 +
to the module
*Enabled HDCP 2.2 authentication/encryption
*Add type0/1 selection for 2.2
*Add MST support (Only tested single daisy chain usecase)
Bhawanpreet Lakha (11):
drm/amd/display: Add PSP block to verify HDCP2.2 steps
drm/amd/display: Add DDC handles for HDCP2.2
drm/amd/display: Add
[Why]
All the HDCP transactions should be verified using PSP
[How]
This patch adds the psp calls we need to verify the steps
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 44 ++
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 502
shown in dmesg
to know what went wrong.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
b/drivers/gpu/drm/amd/display/modules/hdcp
[Why]
We need these to read and write to aux/i2c, during
authentication
[How]
Create read/write functions for all the steps
(Eg, h_prime, paring_info etc)
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/modules/hdcp/hdcp_ddc.c | 326 ++
1 file changed, 326 insertions
Signed-off-by: Sivapiriyan Kumarasamy
Reviewed-by: Wenjing Liu
Acked-by: Abdoulaye Berthe
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b
From: Wesley Chalmers
[WHY]
dpp2_get_optimal_number_of_taps is incorrect, and dcn2 should be using
dpp1_get_optimal_number_of_taps instead
Change-Id: I421c9b8d9dc244d37f2bd9f99027ce2cca2b8817
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
k->dpcd_caps->dongle_type instead.
Change-Id: Ie93769353ccf209b4af0b87c1a143422c88df92d
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 +
2 files cha
: Iccbc64335628247e92814bdebcd8c78439e4814c
Signed-off-by: Sung Lee
Reviewed-by: Yongqiang Sun
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21
From: Charlene Liu
[Description]
use vbios message to call smu for dpm level
also only program dmdata in vsyncflip as HW requirement.
Change-Id: Iaad00db1a5f8e203b708d2605ff16e8b3b323b2b
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../amd
1183 |_crtc_timing.display_color_depth))
[How]
Initialize se to NULL.
Change-Id: I79d89ea518f862a9479581529dbbe8977e224ce2
Signed-off-by: Leo Li
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Aric Cyr
Change-Id: I8ccb02411c552f679cb08ace8652f5c9d4fe3b4f
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b
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