[PATCH] Add freesync ioctl interface

Change-Id: I38cb3a80e75a904cee875ae47bc0a39a3d471aca Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- include/drm/amdgpu_drm.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 46a3c40..a4f816c

[PATCH] drm/amd/powerplay: bypass fan table setup if no fan connected

If vBIOS noFan bit is set, the fan table parameters in thermal controller will not get initialized. The driver should avoid to use these uninitialized parameter to do calculation. Otherwise, it may trigger divide 0 error. Change-Id: I985119837ec818e2101835f79aa4fe6e0e247797 Signed-off-by: Hawking

[PATCH] drm/amd/powerplay: bypass fan table setup if no fan connected

If vBIOS noFan bit is set, the fan table parameters in thermal controller will not get initialized. The driver should avoid to use these uninitialized parameter to do calculation. Otherwise, it may trigger divide 0 error. Change-Id: I76680a5ec5411f59742b65bb70eb7b4a08bda3ef Signed-off-by: Hawking

[PATCH] drm/amdgpu: rename gfxhub_v1_0 to gfxhub_v9_0

Change-Id: Ib721fdefede870ff7ada1efbd57d4f744790f31e Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 343 --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h

[PATCH] drm/amdgpu: rename gfxhub_v1_0 to gchub_v9_0

Change-Id: I32d98b77b8da6b180dd365ff7f99c08e8aa061b1 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- drivers/gpu/drm/amd/

[PATCH] drm/amdgpu: correct vmhub for vcn dec/enc ring

Change-Id: I63002c95c25cc3e2df3931d7d0e6b886b1b7e373 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 6

[PATCH 3/6] drm/amd/powerplay: update magic number for rv hw backend

Change-Id: If51c5a5e4c534769b95105a1dd5ed76b4ec4bbf3 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 +- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drive

[PATCH 1/6] drm/amd/powerplay: initialize rv vq table

Change-Id: I64696e3b5418bcdb24a2c359677506d87769afaf Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 47 +- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 18 +- 2 files changed, 48 insertions(

[PATCH 5/6] drm/amd/powerplay: bypass pptable process on raven

Change-Id: I550c70144213f9a7490be4df04f7efd286c4d05b Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/g

[PATCH 6/6] drm/amd/powerplay: set powerplay support cap on raven

Change-Id: I9aa5e78c1cf19b9069d37215bfd2517980bdf2a6 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay

[PATCH 2/6] drm/amd/powerplay: using MinFClock/MaxFclock to report Min/Max memory clock limits

Change-Id: I713031dced6e1d5a449cb07a53b644d1014c120c Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/pow

[PATCH 1/2] drm/amd/powerplay: fix memory leak in rv_hwmgr backend

vddc_dep_on_dal_pwrl and vq_budgeting_table are allocated and initialized in rv_hwmgr_backend_init. Thus free the memory in rv_hwmgr_backend_fini Change-Id: I15878ccb6a39848b764844e45f2ac375164906ad Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay

[PATCH] drm/amdgpu: switch to use new SOC15 reg read/write macros for soc15 ih

Change-Id: I53b62020a30a827140b03f5986992cbd294d3fa8 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 46 +- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_i

[PATCH libdrm 2/3] tests/amdgpu: execute const fill on all the available rings

Change-Id: I4499cb44c478f1a1acf96e21d844bee7a1975561 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> Acked-by: Christian König <christian.koe...@amd.com> --- tests/amdgpu/b

[PATCH libdrm 1/3] tests/amdgpu: execute write linear on all the available rings

Change-Id: I53a1d1dc0df4b7a4ddfd2edaaf3733806faa7d6d Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> Acked-by: Christian König <christian.koe...@amd.com> --- tests/amdgpu/b

[PATCH libdrm 3/3] tests/amdgpu: execute copy linear on all the available rings

Change-Id: Iab950fe55b889d439a45087b3bb839b5d41ac270 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> Acked-by: Christian König <christian.koe...@amd.com> --- tests/amdgpu/b

[PATCH 5/5] drm/amdgpu: retire soc15ip.h

Change-Id: Ieaa45fa9cfcdb9dec68dd777d27daac675d94a00 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/include/soc15ip.h | 1343 - 1 file changed, 1343 deletions(-) delete mode 100644 drivers/gpu/drm/amd/include/soc15ip.h diff

[PATCH 3/5] drm/amd/pp: include new ip and ip offset headers

Change-Id: I9b3a56147dfc00830a0229bf59990bfe9e8a7e95 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/d

[PATCH 4/5] drm/amd/dc: include new ip and ip_offset headers

Change-Id: I886747dbfea9eec4f3f7f8af8ce99f04c2a8f1b7 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 3 ++- drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 3 ++- drivers/gpu/drm/amd/display/dc/

[PATCH 2/5] drm/amdgpu: include new ip and ip offset headers

Change-Id: I4abff0cc4cd1ffcbc7a571d3eed9df12b3ff7b7c Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/d

[PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header

ip base could be different per ASIC since from soc15. split soc15 header into common ip/hw_id header and asic specific ip offset header Change-Id: I54e5856e1b99d4e313e61328c0fcd85cdd3b3267 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/include/soc15_h

[PATCH] drm/amdgpu: query vram type from atombios

The vram type for dGPU is stored in umc_info while sys mem type for APU is stored in integratedsysteminfo Change-Id: Iec14a0cac407f3da37245786c8f1b688968f8726 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.

[PATCH] drm/amdgpu: query vram type from atombios

The vram type info for dGPU is saved in umc_info while sys mem type info for APU is saved in integratedsysteminfo Change-Id: I08b84c65e4e31c65e2e5a277a1acdf032ec04d2e Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.

[PATCH] drm/amdgpu/nbio6: Correct PCIE_INDEX/DATA pair used for smn register accessing

PCIE_INDEX2/DATA2 pair will be used for smn register accessing since from vega. PCIE_INDEX/DATA pair should be reserved for smu Change-Id: Ie597d89001e706225521c94161d2b40443ec3c48 Signed-off-by: Hawking Zhang <hawking.zh...@amd.com> --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++--

[PATCH] drm/amdgpu: fix frame size of amdgpu_xgmi_add_devices excceed 1024 bytes

Instead of stack-allocated psp_xgmi_topology_info in function amdgpu_xgmi_add_device, dynamically allocated this structure to avoid the frame size of this function excceed 1024 bytes. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 11 ++- 1 file changed, 6

[PATCH 1/2] drm/amdgpu: update vram_info structure in atomfirmware.h

atomfirmware has structure changes in varm_info. Updated it to the latest one. Change-Id: Ie5d60413e5db1dfb4aaf23dc94bc5fd4ed0a01cd Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 2 +- drivers/gpu/drm/amd/include/atomfirmware.h

[PATCH 2/2] drm/amdgpu: fix unknown vram mem type for vega20

. Change-Id: If8d22b687ec5d0f4445527e69841df83479cc485 Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b

[PATCH] drm/amdgpu/psp: udpate ta_ras interface header

ras ta interface header need to be updated to match with latest ta fw updates Change-Id: I4ccc0dbba820221b5074e2bfc2902819a1e3f4d4 Signed-off-by: Hawking Zhang Reviewed-by: James Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ta_ras_if.h | 108

[PATCH 1/2] drm/amdkfd: initialize mqd_manager_init function for navi10

Change-Id: I43c50769557a9be932891e923f669f7993eeedf9 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c b/drivers/gpu/drm/amd/amdkfd

[PATCH] drm/amdgpu: fix modprobe failure for uvd_4/5/6

, if the new SMU driver is supported, invoke new power gate helper function smu_dpm_set_power_gate, otherwise, fallback to legacy powerplay helper function pp_set_powergating_by_smu. For other IP blocks always invoke legacy powerplay helper function. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd

[PATCH libdrm 1/4] amdgpu: add navi family id

From: Huang Rui Signed-off-by: Huang Rui Reviewed-by: Hawking Zhang --- include/drm/amdgpu_drm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 3d0318e..b28fee4 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h

[PATCH libdrm 4/4] tests/amdgpu/vcn: add VCN2.0 decode support

From: Leo Liu With different register offsets from VCN1.0 Signed-off-by: Leo Liu Reviewed-by: James Zhu --- tests/amdgpu/vcn_tests.c | 50 +++- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/tests/amdgpu/vcn_tests.c

[PATCH libdrm 2/4] libdrm/amdgpu: add new member in drm_amdgpu_device_info for navi10

pa_sc_tile_steering_override is a new member introduced for gfx10 Change-Id: I1482a5ef22cc4564eea63e09b1c40e9be3900e1f Signed-off-by: Hawking Zhang Reviewed-by: Marek Olšák --- include/drm/amdgpu_drm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm

[PATCH libdrm 3/4] libdrm/amdgpu: add new vram type (GDDR6) for navi10

From: Tao Zhou AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10 Change-Id: I6789230f8f7f5bdcb0aec82cc764d10d72c4cba8 Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- include/drm/amdgpu_drm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm

[PATCH] drm/amdgpu: fix -Wswitch warning due to missing of default case

Change-Id: I40ed446b8f7431efd73ef09938ec5e2b5ab09f04 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c index d2acfcce7150..201c00411720

[PATCH 1/2] drm/amdgpu: switch to macro for psp bootloader command

Change-Id: Ief4c1e5ca01df0a028a784c0faf37544939733a3 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 9 + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++-- 3 files changed, 13 insertions(+), 4 deletions(-) diff

[PATCH 2/2] drm/amdgpu: support key database loading for navi10

Starting from navi10, driver should send Key Database Load command to Bootloader before loading sys_drv and sos Change-Id: Ib82d21840fb77da2217dd8b8f013177e61d72990 Signed-off-by: John Clements Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 +++ drivers/gpu

[PATCH] drm/amdgpu: correct in_suspend setting for navi series

in_suspend flag should be set in amdgpu_device_suspend/resume in pairs, instead of gfx10 ip suspend/resume function. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH 7/7] drm/amdgpu: switch to ras_late_init callback for nbio v7_4

invoke nbio ras_late_init callback function to do nbio ras init Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/soc15.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index

[PATCH 1/7] drm/amdgpu: add helper function to do common ras_late_init

In late_init for ras, the helper function will be used to 1). disable ras feature if the IP block is masked as disabled 2). send enable feature command if the ip block was masked as enabled 3). create debugfs/sysfs node per IP block 4). register interrupt handler Signed-off-by: Hawking Zhang

[PATCH 5/7] drm/amdgpu: add mmhub ras_late_init callback function

The function will be called in late init phase to do mmhub ras init Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 ++--- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 28

[PATCH 2/7] drm/amdgpu: switch to amdgpu_ras_late_init for gfx v9 block

call helper function in late init phase to handle ras init for gfx ip block Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 90 --- 1 file changed, 19 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b

[PATCH 3/7] drm/amdgpu: switch to ras_late_init for sdma v4 block

call ras_late_init helper function to do ras init for sdma block Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 96 -- 1 file changed, 22 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu

[PATCH 4/7] drm/amdgpu: switch to ras_late_init for gmc v9

call amdgpu_ras_late_init to do ras init for gmc v9 block Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 155 ++ 1 file changed, 43 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm

[PATCH 6/7] drm/amdgpu: add ras_late_init callback function for nbio v7_4

ras_late_init callback function will be used to do common ras init in late init phase. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 41 2 files changed, 43 insertions(+) diff --git

[PATCH 6/7] drm/amdgpu: add ras_late_init callback function for nbio v7_4 (v3)

ras_late_init callback function will be used to do common ras init in late init phase. v2: call ras_late_fini to do cleanup when fails to enable interrupt v3: rename sysfs/debugfs node name to pcie_bif_xxx Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2

[PATCH 7/7] drm/amdgpu: switch to amdgpu_ras_late_init for nbio v7_4 (v2)

call helper function in late init phase to handle ras init for nbio ip block v2: init local var r to 0 in case the function return failure on asics that don't have ras_late_init implementation Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/soc15.c | 13 - 1 file

[PATCH 5/7] drm/amdgpu: add mmhub ras_late_init callback function (v2)

The function will be called in late init phase to do mmhub ras init v2: check ras_late_init function pointer before invoking the function Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26

[PATCH 3/7] drm/amdgpu: switch to amdgpu_ras_late_init for sdma v4 block (v2)

call helper function in late init phase to handle ras init for sdma ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 98 +- 1 file changed, 24 insertions(+), 74

[PATCH 2/7] drm/amdgpu: switch to amdgpu_ras_late_init for gfx v9 block (v2)

call helper function in late init phase to handle ras init for gfx ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 92 --- 1 file changed, 21 insertions(+), 71

[PATCH 4/7] drm/amdgpu: switch to amdgpu_ras_late_init for gmc v9 block (v2)

call helper function in late init phase to handle ras init for gmc ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 159 ++ 1 file changed, 47 insertions(+), 112

[PATCH 1/7] drm/amdgpu: add helper function to do common ras_late_init/fini (v3)

add interrupt handler or not v3: add ras_late_fini for cleanup all the ras fs node and remove interrupt handler Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 72 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 7 2 files changed, 79

[PATCH 5/8] drm/amdgpu: update nbio v7_4 ip header files

Add mmBIF_INTR_CNTL and its shift mask. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h | 4 ++-- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions

[PATCH 1/8] drm/amdgpu: add new amdgpu nbio header file

More nbio funcitonalities will be added and nbio could be treated as an ip block like gfx/sdma.etc Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 87 1 file changed, 87 insertions(+) create mode 100644

[PATCH 3/8] drm/amdgpu/nbio: add functions to query ras specific interrupt status

ras_controller_interrupt and err_event_interrupt are ras specific interrupts. add functions to check their status and ack them if they are generated. both funcitons should only be invoked in ISR when BIF ring is disabled or even not initialized. Signed-off-by: Hawking Zhang Reviewed-by: Alex

[PATCH 2/8] drm/amdgpu: switch to new amdgpu_nbio structure

no functional change, just switch to new structures Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 63 ++- drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 16 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

[PATCH 7/8] drm/amdgpu: enable/disable ras_controller_irq and err_event_athub_irq

Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 55da6f5..8b4a568 100644 --- a/drivers/gpu

[PATCH 4/8] drm/amdgpu: add nbif v7_4 irq source header for vega20

nbif v7_4 interrupt source definition Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- .../amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h| 42 ++ 1 file changed, 42 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h

[PATCH 6/8] drm/amdgpu: add ras_controller and err_event_athub interrupt support

Ras controller interrupt and Ras err event athub interrupt are two dedicated interrupts for RAS support. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 drivers/gpu/drm/amd/amdgpu

[PATCH 0/8] drm/amdgpu: enable dedicated ras controller interrupt

. BIF ring was designed and dedicated for both interrupts. However, it can't be enabled due to known HW bug. Driver has to poll BIF_DOORBELL_INT_CNTL register to check whether the interrupt is triggered or not. Hawking Zhang (8): drm/amdgpu: add new amdgpu nbio header file drm/amdgpu: switch

[PATCH 8/8] drm/amdgpu: poll ras_controller_irq and err_event_athub_irq status

For the hardware that can not enable BIF ring for IH cookies for both ras_controller_irq and err_event_athub_irq, the driver has to poll the status register in irq handling and ack the hardware properly when there is interrupt triggered Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher

[PATCH 4/4] drm/amdgpu: drop ras self test

this function is not needed any more. error injection is the only way to validate ras but it can't be executed in amdgpu_ras_init, where gpu is even not initialized Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 --- 1 file changed, 7 deletions(-) diff --git

[PATCH 1/4] drm/amdgpu: do not create ras debugfs/sysfs node for ASICs that don't have ras ability

driver shouldn't init any ras debugfs/sysfs node for ASICs that don't have ras hardware ability Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd

[PATCH 3/4] drm/amdgpu: only allow error injection to UMC IP block

error injection to other IP blocks (except UMC) will be enabled until RAS feature stablize on those IP blocks Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu

[PATCH 2/4] drm/amdgpu: disable GFX RAS by default

GFX RAS has not been stablized yet. disable GFX ras until it is fully funcitonal. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu

[PATCH] drm/amdgpu: set sdma irq src num according to sdma instances

Otherwise, it will cause driver access non-existing sdma registers in gpu reset code path Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b

[PATCH] drm/amdgpu: avoid upload corrupted ta ucode to psp

. In the terminate (unload) case, the driver will check the context readiness before perform unload activity. It's fine to keep it as is. Change-Id: I493116970ffb557f33c06de10f786684fdcef85b Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 22 +- 1 file changed

[PATCH] drm/amdgpu: avoid upload corrupted ta ucode to psp

. In the terminate (unload) case, the driver will check the context readiness before perform unload activity. It's fine to keep it as is. Change-Id: I493116970ffb557f33c06de10f786684fdcef85b Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 22 +- 1 file changed

[PATCH 2/2] drm/amdgpu: init umc functions for arcturus umc ras

reuse vg20 umc functions for arcturus umc ras Change-Id: Ia8af3c20a717c76ec18aa5fa332cfd81ca60ff69 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu

[PATCH 1/2] drm/amdgpu: enable ras capablity check on arcturus

check hw ras capablity via atomfirmware Change-Id: I495b73ac6c04910de2ad8d9c46e98873fb5bc44d Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm

[PATCH 2/3] drm/amdgpu: add helper func for psp ring cmd submission

Except for ring wptr update, the psp ring cmd submission function shouldn't be IP specific one. Create a common helper function to be shared for all the ASICs. Change-Id: Ic59f22f762fc7580fd9438d865d37d5996ce8b84 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 50

[PATCH 1/3] drm/amdgpu: add psp funcs for ring write pointer read/write

The ring write pointer regsiter update is the only part that is IP specific ones in psp_cmd_submit function. Add two callbacks for wptr read/write so that we unify the psp_cmd_submit function for all the ASICs. Change-Id: Idd0b70bd8682f8bd2f9b92098d6ce55fa4cee310 Signed-off-by: Hawking Zhang

[PATCH 3/3] drm/amdgpu: switch to common helper func for psp cmd submission

Drop all the IP specific cmd_submit callback function and use the common helper instead Change-Id: I865b26fd25a696f213e888beb927717dec884546 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 --- drivers/gpu/drm/amd

[PATCH] drm/amdgpu: pull ras controller int status only when ras enabled

ras_controller_irq and athub_err_event_irq are only registered when PCIE_BIF ras is marked as supported. as the result, the driver also just need pull the int status in such case. Change-Id: Ibd1f29be253e0e60f9be7ff2208f5cf2b78a56a4 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu

[PATCH] drm/amdgpu: fix resume failures casued by psp fw loading sequence change

-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 33 + 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index ceea8314d88d..2ef16d4c752d 100644 --- a/drivers/gpu/drm/amd/amdgpu

[PATCH] drm/amdgpu: fix resume failures due to psp fw loading sequence change (v2)

-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 + 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index ceea8314d88d..03c4a223c05f 100644 --- a/drivers/gpu/drm/amd/amdgpu

[PATCH] drm/amdgpu: fix resume failures due to psp fw loading sequence change (v3)

handling to failed tag Change-Id: I20d3651f325e793e1ea7e73df1c76219eaa0b5ab Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 33 + 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu

[PATCH] drm/amdgpu: apply gpr/gds workaround before enabling GFX EDC mode

gfx memory should be initialized before enabling DED and FUE field in mmGB_EDC_MODE Change-Id: I248a087364cbd9858cba32a70be456af3f07c90d Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu

[PATCH 2/3] drm/amdgpu: unload asd in psp hw de-init phase

issue unload_ta_cmd to tOS to unload asd driver Change-Id: I697cfc1774205ed6cbe22eb3c16143b603543564 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 + 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b

[PATCH 1/3] drm/amdgpu: drop asd shared memory

asd shared memory is not needed since drivers doesn't invoke any further cmd to asd directly after the asd loading. trust application is the one who needs to talk to asd after the initialization Change-Id: I728afa4c7e8b67bc06678b10e92ac064ba10173e Signed-off-by: Hawking Zhang --- drivers/gpu

[PATCH 3/3] drm/amdgpu: load np fw prior before loading the TAs

: I83db1a22577a84ae647e7e570c200057650096c5 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 66 - 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 0e8907179e07..ceea8314d88d

[PATCH 2/6] drm/amdgpu: add wafl2 ip headers

add wafl2 smn address and shift mask definition header files Signed-off-by: Hawking Zhang Reviewed-by: Guchun Chen --- .../asic_reg/wafl/wafl2_4_0_0_sh_mask.h | 69 +++ .../include/asic_reg/wafl/wafl2_4_0_0_smn.h | 29 2 files changed, 98 insertions(+) create

[PATCH 1/6] drm/amdgpu: add xgmi ip headers

add xgmi ip smn address and shift mask header files Signed-off-by: Hawking Zhang Reviewed-by: Guchun Chen --- .../asic_reg/xgmi/xgmi_4_0_0_sh_mask.h| 69 +++ .../include/asic_reg/xgmi/xgmi_4_0_0_smn.h| 29 2 files changed, 98 insertions(+) create mode

[PATCH 3/6] drm/amdgpu: add helper funcs to detect PCS error

Since from vega20, hardware supports run-time detect and report XGMI/WAFL PCS ras error. Add helper functions to walkthrough every type of ras error and report it if any. Signed-off-by: Hawking Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 173

[PATCH 4/6] drm/amdgpu: enable PCS error report on VG20

Now driver will report XGMI/WAFL PCS error through sysfs xgmi_wafl_err_count node on Vega20 Signed-off-by: Hawking Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b

[PATCH 5/6] drm/amdgpu: enable PCS error report on arcturus

add arcturus xgmi/wafl pcs err status group to support PCS error detection and report on arcturus Signed-off-by: Hawking Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 31 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd

[PATCH 3/4] drm/amdgpu: add reset_ras_error_count function for GFX

GFX ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

[PATCH 4/4] drm/amdgpu: add reset_ras_error_count function for HDP

HDP ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 - drivers/gpu/drm/amd/amdgpu/soc15.c| 14 ++ 3 files

[PATCH 0/4] reset ras error counters in initialization sequence

tool to force reset hw register counters. Hawking Zhang (4): drm/amdgpu: add reset_ras_error_count function for SDMA drm/amdgpu: add reset_ras_error_count function for MMHUB drm/amdgpu: add reset_ras_error_count function for GFX drm/amdgpu: add reset_ras_error_count function for HDP

[PATCH 2/4] drm/amdgpu: add reset_ras_error_count function for MMHUB

MMHUB ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 12

[PATCH 1/4] drm/amdgpu: add reset_ras_error_count function for SDMA

SDMA ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++-- 2 files changed, 15 insertions(+), 6

[PATCH] drm/amdgpu: correct ROM_INDEX/DATA offset for VEGA20

The ROMC_INDEX/DATA offset was changed to e4/e5 since from smuio_v11 (vega20/arcturus). Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/soc15.c | 25 +++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b

[PATCH 2/3] drm/amdgpu: move get_xgmi_relative_phy_addr to amdgpu_xgmi.c

centralize all the xgmi related function to amdgpu_xgmi.c Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 20 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 15 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++ 3 files changed, 21

[PATCH 3/3] drm/amdgpu: toggle DF-Cstate to protect DF reg access

driver needs to take DF out Cstate before any DF register access. otherwise, the DF register may not be accessible. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 25 +++- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu

[PATCH 1/3] drm/amdgpu: add dpm helper function for DF Cstate control

The helper function hides software smu and legacy powerplay implementation for DF Cstate control. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 17 + drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 3 +++ 2 files changed, 20 insertions(+) diff --git

[PATCH 1/2] drm/amdgpu: update arcturus ppsmc header to 54.15.0

two new smc messages added for arcturus with pmfw 54.15.0 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd

[PATCH 2/2] drm/amdgpu: add DFCstate control pptable func for arct

This is the callback function that is going to be invoked when amdgpu_dpm_set_df_cstate is called to toggle DFCstate Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 23 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd

[PATCH] drm/amdgpu: check sdma ras funcs pointer before accessing

sdma ras funcs are not supported by ASIC prior to vega20 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index

[PATCH] drm/amdgpu: check if driver should try recovery in ras recovery path

To allow the flexibilty for user to disable gpu recovery in RAS recovery path by module parameter amdgpu_gpu_recovery Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 ++- 2 files changed, 3 insertions(+), 1

[PATCH 1/2] drm/amdgpu: check if driver should try recovery in ras recovery path

To allow the flexibilty for user to disable gpu recovery in RAS recovery path by module parameter amdgpu_gpu_recovery Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu

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