-...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
Wentland, Harry
Cc: Li, Sun peng
Subject: [PATCH i-g-t] tests: Increase value of I915_MAX_PIPES to 6
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Increasing max pipe count to 6 to support AMD GPU's.
Since some tests' behavior depen
stuck in the moderation queue since Leo
(Sun peng) is fairly new on the FDO mailing lists.
Jani, Daniel, can you check if Leo's IGT emails are stuck in the
moderation queue?
Done. I've whitelisted his email address on intel-gfx, but I suggest
subscribing too.
BR,
Jani.
Thanks Jani.
I'll wait with p
seem to be quite wide, and I'd like some input on this
before I jump in. Any ideas and/or suggestions will be very much
appreciated!
Thanks,
Leo
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Hi Tom,
This is a known issue, and we're currently tracking it on ticket
SWDEV-135329. It's reported using Vega10, but we reproduced it on
Carrizo as well.
Thanks,
Leo
On 2017-10-13 09:30 AM, Tom St Denis wrote:
For what it's worth this commit also breaks resume on my Tonga only
system so
On 2017-10-13 11:56 AM, Andrey Grodzovsky wrote:
On 10/13/2017 11:41 AM, Leo wrote:
On 2017-10-13 11:03 AM, Andrey Grodzovsky wrote:
On 10/12/2017 05:15 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"<sunpeng...@amd.com>
Use the correct for_each_new/old_* i
On 2017-10-13 11:03 AM, Andrey Grodzovsky wrote:
On 10/12/2017 05:15 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"<sunpeng...@amd.com>
Use the correct for_each_new/old_* iterators instead of for_each_*
List of affected functions:
amdgpu_dm_find_first_crtc_matchin
On 2017-10-13 04:36 PM, Andrey Grodzovsky wrote:
On 10/13/2017 03:29 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Use the correct for_each_new/old_* iterators instead of for_each_*
The following functions
On 2017-10-13 08:39 AM, William Lewis wrote:
On 10/12/2017 04:15 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
To conform to DRM's new API, we should not be accessing a DRM object's
internal state directly. Rather, the DRM for_each_old
On 2017-10-11 10:30 AM, Maarten Lankhorst wrote:
Op 11-10-17 om 16:24 schreef sunpeng...@amd.com:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Use the correct for_each_new/old_* iterators instead of for_each_*
List of affected functions:
amdgpu_dm_find_first_crtc_matchin
On 2017-10-12 02:00 AM, Maarten Lankhorst wrote:
Op 11-10-17 om 22:40 schreef Harry Wentland:
On 2017-10-11 03:46 PM, Maarten Lankhorst wrote:
Op 11-10-17 om 20:55 schreef Leo:
On 2017-10-11 10:30 AM, Maarten Lankhorst wrote:
Op 11-10-17 om 16:24 schreef sunpeng...@amd.com:
From: &quo
On 2017-10-26 11:06 PM, Andrey Grodzovsky wrote:
On 2017-10-26 02:34 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Abandon new_crtcs array and use for_each_new iterator to acquire new
crtcs.
Signed-off-by: Leo (Sunpeng) Li <sunpeng...@amd.com&
On 2017-10-30 12:36 PM, Leo wrote:
On 2017-10-26 11:06 PM, Andrey Grodzovsky wrote:
On 2017-10-26 02:34 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Abandon new_crtcs array and use for_each_new iterator to acquire new
crtcs.
Signed-off-by:
bled == enable) {
> + DRM_DEBUG_ATOMIC("[MST PORT:%p] DSC flag is already set to %d,
> returning %d VCPI slots\n",
> + port, enable, pos->vcpi);
> + vcpi = pos->vcpi;
Do we want to early return here?
- Leo
> +
Reviewed-by: Leo Li
On 2019-11-16 5:01 p.m., mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> [why]
> For DSC case we cannot always use topology manager's PBN divider
> variable. The default divider does not take FEC into account.
> Therefore we should allow driver to
Just realized Lyude wasn't CC'd originally, and I forgot to CC everyone as well
in the reply :)
Leo
On 2019-11-26 10:24 a.m., Leo wrote:
>
>
> On 2019-11-16 5:01 p.m., mikita.lip...@amd.com wrote:
>> From: Mikita Lipski
>>
>> Adding a helper function to be called b
continue;
> +
> + if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
> + pbn_used += vcpi->pbn;
> + }
It's not clear to me how this will behave when recursively called.
The above iteration over b
gt; + return dc_link_bandwidth_kbps(link,
> + dc_link_get_link_cap(link)) / (8 * 1000 * 54);
Had to take a look at the DP spec to understand this conversion here, section
2.6.4.1.
LGTM,
Reviewed-by: Leo Li
> +}
> diff --git a/drivers/gpu/drm/amd/display/amdgpu
Sorry for the delay, change LGTM.
Reviewed-by: Leo Li
, and applied.
Thanks!
Leo
On 2020-01-24 5:18 a.m., Dor Askayo wrote:
> On Fri, Jan 17, 2020 at 12:59 PM Dor Askayo wrote:
>>
>> On Sat, Jan 4, 2020 at 2:23 PM Dor Askayo wrote:
>>>
>>> This allocation
display: Get VCO frequency from registers")
> Signed-off-by: Nathan Chancellor
Just hit this myself, thanks for the fix!
Reviewed-by: Leo Li
> ---
> drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&g
>
>> Signed-off-by: Chandan Vurdigere Nataraj
>
> Acked-by: Alex Deucher
Reviewed-by: Leo Li
>
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> index 4027f439a5a4..c8355acd3672 100644
?
>
> --
I don't quite recall the details, but in FPU context, we should not malloc
since it can fault/sleep. More info here:
https://yarchive.net/comp/linux/kernel_fp.html
-
On 2022-06-07 13:58, Aurabindo Pillai wrote:
>
>
> On 2022-06-07 11:34, Leo wrote:
>>
>>
>> On 2022-06-07 05:40, Chandan Vurdigere Nataraj wrote:
>>> [Why]
>>> Getting below errors:
>>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dc
hange is really doing is identifying the panel instance to run PSR
commands on, instead of assuming that the eDP we want is always instance 0.
Will reword the message.
Thanks,
Leo
>
>> Signed-off-by: Mikita Lipski
>
> This says the author is David but it has only Mikita's sign-of
1_5->number_of_path; ++i)
>> ^~~~
>>
>> [How]
>> Fix compilation issues
>>
>> Signed-off-by: Chandan Vurdigere Nataraj
>
> Acked-by: Alex Deucher
Reviewed-by: Leo Li
Thanks for the fix!
>
>>
>> diff --gi
RequestChroma;
> + RequestType RequestLuma;
> + RequestType RequestChroma;
This might need a wider cleanup, enum RequestType is defined in
display_mode_enums.h and is already included in all the display_mode_vba*.c
files I've come across. Unless I'm missing something,
From: Christian König <christian.koe...@amd.com>
Context buffers should be denied by default, not allowed.
Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
1 file changed,
From: Christian König <christian.koe...@amd.com>
Supported starting on certain FW versions.
Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu
Adapt to recent firmware update, it's also compatible with previous
firwmare version
Signed-off-by: Leo Liu <leo@amd.com>
---
tests/amdgpu/vce_ib.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h
index bd0bf94..80ab179
On 10/12/2016 07:05 AM, Christian König wrote:
Andy & Leo could you give that a brief testing?
run `kill -9' over 30 times, no issue.
Patch is:
Reviewed-and-Tested by: Leo Liu <leo@amd.com>
I currently don't have a setup for encoding/transcoding clips.
Regards,
Chri
Signed-off-by: Leo Liu <leo@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
---
include/drm/amdgpu_drm.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d702a95..96cccd1 100644
--- a
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index ff8ae50..b464f62 100644
--- a/drivers/gpu/drm/amd/
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d5c63d6c8fb3..0186bf49d5c2 100644
--- a/drive
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 09190fa..d58ca82 100644
--- a/drivers/gp
The power control for vcn has been moved to firmware, kernel'll spins
"amdgpu: [powerplay] pp_dpm_powergate_uvd was not implemented", each
time when application runs, so let's remove it.
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/a
when harvest part has only instance 1 available
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 61 +++
1 file changed, 55 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
b/drivers/gpu/d
We need program ring buffer on instance 1 register space domain,
when only if instance 1 available, with two instances or instance 0,
and we need only program instance 0 regsiter space domain for ring.
Signed-off-by: Leo Liu <leo@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc..
On 05/30/2017 12:15 PM, Christian König wrote:
Am 30.05.2017 um 17:56 schrieb Leo Liu:
We need program ring buffer on instance 1 register space domain,
when only if instance 1 available, with two instances or instance 0,
and we need only program instance 0 regsiter space domain for ring
On 05/30/2017 11:13 AM, Christian König wrote:
Am 30.05.2017 um 16:57 schrieb Deucher, Alexander:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Leo Liu
Sent: Monday, May 29, 2017 2:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo
To simplify vce bo create
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
We are using PSP to resume firmware after suspend, and it is
resumed at where it got suspended, so we'd better save the
the context.
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
On 05/31/2017 03:54 PM, Deucher, Alexander wrote:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Leo Liu
> Sent: Wednesday, May 31, 2017 3:28 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH
We are using PSP to resume firmware after suspend, and it is
resumed at where it got suspended, so we'd better save the
the context.
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 0a7f18c..c93f74a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu
When you git email-send first time, there is a message-id, when you
would send follow up patches, using --in-reply-to="message-id" in your
comment line, then that will be in the same thread.
Cheers,
Leo
On 06/01/2017 09:40 AM, Xie, AlexBin wrote:
Ok. I will add the v2 next t
On 06/01/2017 06:55 AM, Christian König wrote:
Am 31.05.2017 um 21:28 schrieb Leo Liu:
To simplify vce bo create
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27
+++
1 file changed, 3 insertions(+), 24 deletions(-)
The series is to add vcn unit tests for decode, and have the common
from previous uvd unit test to be shared with vcn decode.
Leo Liu (5):
tests/amdgpu: rename uvd messages to decode messages
tests/amdgpu: separate decode messages
tests/amdgpu: move decode sum to common
tests/amdgpu: add
AVC decode messages will be common with VCN decode
Signed-off-by: Leo Liu <leo@amd.com>
Acked-by: Christian König <christian.koe...@amd.com>
---
tests/amdgpu/cs_tests.c| 3 ++-
tests/amdgpu/decode_messages.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff -
Signed-off-by: Leo Liu <leo@amd.com>
Acked-by: Christian König <christian.koe...@amd.com>
---
tests/amdgpu/cs_tests.c| 2 +-
tests/amdgpu/decode_messages.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_t
Signed-off-by: Leo Liu <leo@amd.com>
Acked-by: Christian König <christian.koe...@amd.com>
---
tests/amdgpu/decode_messages.h | 30 +
tests/amdgpu/vcn_tests.c | 139 -
2 files changed, 166 insertions(+), 3 deletions(-)
diff -
Signed-off-by: Leo Liu <leo@amd.com>
Acked-by: Christian König <christian.koe...@amd.com>
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 6 +
tests/amdgpu/amdgpu_test.h | 15 +++
tests/amdgpu/vcn_tests.c | 277 ++
h that fixed, the series is
Reviewed-by: Leo Liu <leo@amd.com>
len += sizeof(uve_encode_param) / 4;
memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode));
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On 09/07/2017 08:08 AM, Christian König wrote:
Am 06.09.2017 um 18:33 schrieb Leo Liu:
On 09/06/2017 11:51 AM, Christian König wrote:
From: Christian König <christian.koe...@amd.com>
Use the VM instead of the BO list to find the BO for a virtual address.
This fixes UVD/VCE in ph
On 09/06/2017 11:51 AM, Christian König wrote:
From: Christian König <christian.koe...@amd.com>
Use the VM instead of the BO list to find the BO for a virtual address.
This fixes UVD/VCE in physical mode with VM local BOs.
The series is
Tested-by: Leo Liu <leo@amd.com>
On 10/02/2017 11:56 AM, Christian König wrote:
Some minor nit picks on patch #4 and #9, but apart from that it looks
good to me.
With those fixed the series is Reviewed-by: Christian König
<christian.koe...@amd.com>, but Leo should probably take a look as well.
Yes.
Reviewed-by: Leo Liu <leo@amd.com>
On 10/23/2017 01:34 PM, Alex Deucher wrote:
On Mon, Oct 23, 2017 at 1:03 PM, Tom St Denis <tom.stde...@amd.com> wrote:
On APUs the uvd6 driver was skipping proper suspend/resume routines resulting
in a broken state upon resume.
Signed-of
Hi Johannes,
The s3 resume issue looks to be a problem with amdgpu/display. Could you
give the attached patch a try?
Thanks,
Leo
On 2017-11-23 07:27 AM, Johannes Hirte wrote:
On 2017 Nov 23, Chunming Zhou wrote:
See the attached email, they fixed same issue, each of them is ok to fix
your
On 2017-11-23 02:52 PM, Harry Wentland wrote:
Signed-off-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Leo (Sunpeng) Li <sunpeng...@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
2 files changed,
On 2017-11-17 11:46 PM, Andrey Grodzovsky wrote:
On 2017-11-16 10:32 AM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Within atomic check, dm_update_crtcs_state is called twice. First to
remove from the dc_state, and subsequently to add to it
Signed-off-by: Leo Liu <leo@amd.com>
---
src/gallium/state_trackers/va/context.c | 99 -
1 file changed, 49 insertions(+), 50 deletions(-)
diff --git a/src/gallium/state_trackers/va/context.c
b/src/gallium/state_trackers/va/context.c
index 0ad4
From: Mark Thompson <s...@jkqxz.net>
It will be present from libva 2.1 (VAAPI 1.1.0 or higher).
v2: rebase to previous patches(Leo)
Signed-off-by: Mark Thompson <s...@jkqxz.net>
Signed-off-by: Leo Liu <leo@amd.com>
---
src/gallium/state_trackers/va/context.c |
Following VA spec
Signed-off-by: Leo Liu <leo@amd.com>
---
src/gallium/state_trackers/va/context.c| 2 +-
src/gallium/state_trackers/va/subpicture.c | 2 +-
src/gallium/state_trackers/va/va_private.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/g
Sent to the incorrect lists. Please ignores. Thanks.
On 12/04/2017 03:50 PM, Leo Liu wrote:
Following VA spec
Signed-off-by: Leo Liu <leo@amd.com>
---
src/gallium/state_trackers/va/context.c| 2 +-
src/gallium/state_trackers/va/subpicture.c | 2 +-
src/gallium/state_track
On 2017-11-10 01:40 PM, Andrey Grodzovsky wrote:
On 11/10/2017 01:38 PM, Andrey Grodzovsky wrote:
On 11/09/2017 03:05 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This is a followup to the following revert:
Rex Zhu Revert "drm/amd/
With the enablement of VCN Dec and Enc from user space, User space queries
kernel for the IP information, if HW has UVD/VCE, the info comes from these
IP blocks, but this could end up mis-interpret for VCN when they are in the
union, ther other way same when HW with VCN block.
Signed-off-by: Leo
rqs_on_caller+0x11f/0x190
[ 9066.794466] ? trace_hardirqs_on+0xd/0x10
[ 9066.794492] amdgpu_drm_ioctl+0x47/0x80 [amdgpu]
[ 9066.794495] do_vfs_ioctl+0x8e/0x640
[ 9066.794497] ? trace_hardirqs_on+0xd/0x10
[ 9066.794500] ? security_file_ioctl+0x3e/0x60
On 11/21/2017 09:28 AM, Leo Liu wrote:
With t
On 11/21/2017 12:17 PM, Michel Dänzer wrote:
On 2017-11-21 03:28 PM, Leo Liu wrote:
With the enablement of VCN Dec and Enc from user space, User space queries
kernel for the IP information, if HW has UVD/VCE, the info comes from these
IP blocks, but this could end up mis-interpret for VCN
On 2017-11-10 02:00 PM, Andrey Grodzovsky wrote:
On 11/09/2017 03:05 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
When disabling pipe splitting, we need to make sure we disable both
planes used.
This should be done for Linux as
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 7e4de3e6950f..0c01825a8b9e 100644
--- a/drivers/gpu/drm/amd/
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 90332f55cfba..cf81065e3c5a 100644
--- a/d
On 10/24/2017 09:07 AM, Tom St Denis wrote:
Thanks Leo,
I don't have any uvd7 gear but that code has the same "workaround."
Should that be removed as well?
Good question. Since we don't have UVD7 APUs to verify, it's up to you
to either re-visit later or remove it now.
Leo
C
On 10/24/2017 12:08 PM, Tom St Denis wrote:
The workaround is not required anymor and would result in
hangs during suspend/resume cycles if the uvd block were busy.
Signed-off-by: Tom St Denis <tom.stde...@amd.com>
Acked-by: Leo Liu <leo@amd.com>
---
drivers/gpu/dr
Ping :)
Leo
On 2018-05-03 02:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This patchset ended up looking quite different from the first. To address some
fundamental issues, the design had to be reworked.
Things gathered from previous review:
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 05
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index f9
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
On 05/17/2018 02:18 PM, Alex Deucher wrote:
On Thu, May 17, 2018 at 2:12 PM, Leo Liu <leo@amd.com> wrote:
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
We discussed this when we first started working on amdgpu. Does it
have to be 0?
Yes.
message.
I will come up a patch to remove those entities for dec and enc.
Regards,
Leo
Christian.
unsigned num_enc_rings;
};
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It should be stateless, and no need for scheduler to take care
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 51 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 --
2 files changed, 10 insertions(+), 43 deletions(-)
On 2018-05-18 04:01 AM, Michel Dänzer wrote:
On 2018-05-17 11:44 PM, Leo Li wrote:
On 2018-05-16 01:10 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This will persist color management properties
On 2018-05-18 06:33 AM, Michel Dänzer wrote:
From: Michel Dänzer <michel.daen...@amd.com>
Leo pointed out that drmmode_do_crtc_dpms wasn't getting called when
turning off an output with
xrandr --output --off
This meant that the vblank sequence number and timestamp wouldn't be
On 2018-05-18 04:10 AM, Michel Dänzer wrote:
On 2018-05-17 11:43 PM, Leo Li wrote:
On 2018-05-16 01:06 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
3. The three color management properties (Degamma LUT, Color
Transform Matrix
(CTM), and Gamma LUT
On 2018-05-16 01:10 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This will persist color management properties on a CRTC across DPMS
state changes.
Signed-off-by: Leo (Sunpeng) Li <sunpeng...
se int32_t instead?).
For historical reasons, Xlib uses long for 32-bit values, so you have to
pad each 32-bit value to a long. XCB shouldn't be affected by this.
Noted.
Leo
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On 2018-05-16 01:08 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Push staged values on the driver-private CRTC, to kernel DRM when it's
initialized. This is to flush out any previous sta
On 2018-05-16 01:09 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The properties on an RandR output needs to stay consistent throughout
it's lifecycle. However, we cannot list color propert
On 2018-05-16 01:09 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The dpms_mode flag on the driver-private CRTC was not being set when
it's DPMS state is set to off. This causes some problems when
On 2018-05-16 01:07 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Non-legacy color management consists of 3 properties on the CRTC:
Degamma LUT, Color Transformation Matrix (CTM), and Gamma LUT.
Add
On 06/12/2018 11:46 AM, James Zhu wrote:
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for decode interface minor
[7, 0] for hardware family id
Signed-off-by: James Zhu
Reviewed-by: Leo
major.minor.revision)
Now the major and minor become 1.1. if you keep looking the code after
the changed part, the 1.1 will cause problem for number of handles,
since that decides how big of bo size for FW runtime.
Regards,
Leo
Apart from that looks good to me, but Leo should have the las
.
Regards,
Leo
[15, 8] for firmware revision
[7, 0] for hardware family id
Inside kernel log UVD firmware Version: 1.1.2 (denote major.minor.revision)
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 21 -
1 file changed, 16 insertions(+), 5
_1_66_16))
- DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too
old.\n",
- version_major, version_minor);
+ adev->uvd.fw_version = ((enc_major << 24) | (enc_minor << 16) |
+ (dec
On 2018-06-14 12:57 PM, Michel Dänzer wrote:
Hi Leo,
sorry for the delay.
Appreciate the review, it's not a small change by any means :)
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a ne
On 2018-06-06 01:03 PM, Michel Dänzer wrote:
On 2018-06-06 06:01 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new patchset. Per
Michel's suggestions, there have be
On 2018-05-28 11:20 AM, Michel Dänzer wrote:
On 2018-05-28 05:06 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
For cases where the CRTC is inactive (DPMS off), where a modeset is not
required, yet the CRTC is still in the atomic state, we sh
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 142 +
1 file changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/amd
On 05/31/2018 01:04 PM, Michel Dänzer wrote:
On 2018-05-31 06:49 PM, Leo Liu wrote:
On 05/31/2018 12:47 PM, Michel Dänzer wrote:
On 2018-05-31 06:39 PM, Leo Liu wrote:
On 05/31/2018 12:30 PM, Michel Dänzer wrote:
On 2018-05-30 08:42 PM, Leo Liu wrote:
diff --git a/drivers/gpu/drm/amd
On 05/31/2018 11:43 AM, Alex Deucher wrote:
On Wed, May 30, 2018 at 2:42 PM, Leo Liu wrote:
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
A few comments below about readability
On 05/31/2018 12:30 PM, Michel Dänzer wrote:
On 2018-05-30 08:42 PM, Leo Liu wrote:
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
This isn't enough to actually make this part
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