Add support for DRM_FORMAT_{A,X}BGR in atombios_crtc
R6xx crossbar registers are defined and used based on ASIC_IS_DCE2 condition,
for DCE1/R5xx AVIVO_D1GRPH_SWAP_RB bit is used to swap red and blue channels.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/radeon/atombios_crtc.c | 25
Sending a respin for support of {A,X}RGB pixel formats in DCE1 and later,
with separate patches for amd dc, amdgpu and radeon
Please review taking in to account following doubts I have:
For amd dc crossbars register controls to swap red and blue channels
are already implemented in
, 11.0
modules.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6
Add support for DRM_FORMAT_{A,X}BGR in amdgpu, for si and amd dc disabled
Here is it necessary to define and set crossbar registers
to swap red and blue channels
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 ++
drivers/gpu/drm/amd/amdgpu/si_enums.h | 20
bitwise OR for DCE1 path
Use bitwise OR where required for big endian settings in fb_swap
Use existing code style CHIP_R600 condition, fix typo in R600 blue crossbar
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/radeon/atombios_crtc.c | 25 +
drivers/gpu/drm/radeon
where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 ++
drivers/gpu/drm/amd/amdgpu
-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 770c6b24be0b..4f689f47d7c3 100644
--- a/drivers/gpu/drm
Sending PATCH v3 series for support of {A,X}RGB pixel formats
in DCE1/R5xx and later, with separated patches for amd dc,
amdgpu and radeon, based on Alexander Deucher comments
Tested and working on R5xx (X1300), R6xx (HD2400), R7xx (HD4830),
Juniper (HD5770), Turks (HD7600M), Tahiti (HD7950),
Hi Alex,
Il giorno mar 17 lug 2018 alle ore 15:43 Alex Deucher
ha scritto:
> On Sun, Jul 15, 2018 at 10:03 PM, Mauro Rossi
> wrote:
> > From: Mauro Rossi
> >
> > (v1) {A,X}BGR code paths are added in amdgpu_dm, by using an
> fb_format
> > a
From: Mauro Rossi
(v1) {A,X}BGR code paths are added in amdgpu_dm, by using an fb_format
already listed in dc/dc_hw_types.h (SURFACE_PIXEL_FORMAT_GRPH_ABGR),
and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later.
GRPH_FORMAT_ARGB is used due to lack of specific
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
drivers/gpu/drm/amd/amdgpu/si.c| 14 ++
2 files changed, 21 insertions(+)
diff --git
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
1 file changed, 26 insertions(+)
diff --git
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8 +
.../display/dc/bios/command_table_helper.h| 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c
IMPORTANT: Coding of
+1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without r
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
IMPORTANT: Coding of dce60_resource.c requires review to understand
if
DCE6 targets are added as branching of existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
DCE6 targets are added replicating existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/i2caux/Makefile| 12 +
.../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
.../dc/i2caux/dce60/i2c_hw_engine_dce60.h | 54 ++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.c
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index ed654a76c76a..c79afe89e6e2 100644
(Vulkan API) OK
Sacha Willems examples OK
Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
Kind regards
Mauro Rossi
android-x86 team
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo
s to adapt code for DCE8 to
work for DCE6,
but it was like an "optimistic monkey with a keyboard" approach, with all
due respect for monkeys with keyboards,
:-) I may have missed dozen of changes.
Mauro
>
> On Mon, 8 Oct 2018 at 03:24 Mauro Rossi wrote:
>
>> [PATCH 01
Hi Sylvain,
On Mon, Oct 8, 2018 at 2:04 PM wrote:
>
> I am currently testing your patch set, on amd-staging-drm-next
> (380d480842d584278dba9aa74341017d8c7d8c23) with an AMD tahiti xt part and a
> displayport monitor.
> patch02 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c did not apply
Hi,
reporting about some progress made during the weekend,
thanks to Sylvain feedback & suggestions.
I have rebased and updated the series on top of
https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
Here is the amd_dc_si branch:
https://github.com/maurossi/linux/tree/amd_dc_si
Hi Sylvain,
Il lun 15 ott 2018, 03:25 ha scritto:
> On Sun, Oct 14, 2018 at 11:47:18PM +0200, Mauro Rossi wrote:
> > DOUBT: I think that it would make sense to set "power level 0" i.e.
> > the "lower state" as safe default,
> > considering that powerp
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled
(v2) Hainan is not supported, description updated accordingly
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
(v1) pre-requisite to have Kaveri and Hawaii is revert of d9fda24804
("drm/amdgpu: Don't default to DC support for Kaveri and older")
(v2) fix for bc011f9350 ("drm/amdgpu:
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
(v2) remove CHIP_HAINAN support since it does not have physical DCE6 module
add SI families except CHIP_HAINAN in load_dmcu_fw() new function
---
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c
IMPORTANT: Coding of
DCE6 targets are added replicating existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/i2caux/Makefile| 12 +
.../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
.../dc/i2caux/dce60/i2c_hw_engine_dce60.h | 54 ++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.c
Sending PATCH v2 series rebase on amd-staging-drm-next
dce/dce60/dce60_resources.c and irq/dce60/irq_service_dce60.c
are still using dce_8_0_{d,sh_mask}.h headers
dpm is used for power management, a non fatal message is generated:
[drm:dm_pp_get_static_clocks: [amdgpu]]
*ERROR* DM_PPLIB:
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8 +
.../display/dc/bios/command_table_helper.h| 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
IMPORTANT: Coding of dce60_resource.c requires review to understand
if
DCE6 targets are added as branching of existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without r
Hi Harry,
thanks a lot for response,
On Mon, Oct 15, 2018 at 11:19 PM Harry Wentland wrote:
>
> On 2018-10-15 5:06 p.m., Harry Wentland wrote:
> > On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> >> Hi,
> >>
> >> reporting about some progress made during the w
Hi Harry,
in this thread some of the coding changes with open points,
as a checklist/track for review of upcoming (v2) patches.
M.
On Mon, Oct 15, 2018 at 11:06 PM Harry Wentland wrote:
>
> On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> > Hi,
> >
> > reporting about s
Work In Progress for using DCE6 headers
vblank registers and masks where identified,
but using them gives a glipse with monitor screen active,
followed by monitor screen in standby
Please review to identify the problem
as the DCE6 vblank irq do not map exactlyto DC irq code,
it's not clear how
iated.
Kind regards
Mauro
On Wed, Jan 9, 2019 at 8:07 PM Mauro Rossi wrote:
>
> Ah-ha! (Meaning self-checking and trying to self-correct myself)
>
> I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
> entries for VBLANK isr.")
> required to be comp
ther VBLANK Interrupt Register better than the one I found
I'd like to know to implement directly the best solution.
Mauro
On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi wrote:
>
> Work In Progress for using DCE6 headers
> vblank registers and masks where identified,
> but using them
Hi Harry,
On Wed, Oct 17, 2018 at 9:47 PM Wentland, Harry wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> >
> > NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_m
, CONFIG_AMD_DC=y, CONFIG_AMD_DC_DCN1_0=y,
or some undocumented module dependencies, which are mandatory for the
Raven APUs correct detection?
Thanks for any info
Mauro Rossi
android-x86 team volunteer
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amd-gfx mailing list
amd-gfx@lists.freedesktop.org
Hi Felix,
On Mon, Jan 27, 2020 at 10:34 AM Felix Kuehling wrote:
>
> I've seen hangs on a Raven AM4 system after the Ubuntu upgrade to kernel
> 5.3. I am able to work around it by disabling stutter mode with the
> module parameter amdgpu.ppfeaturemask=0xfffdbfff. If that doesn't help,
> you
Hi, good news,
'modprobe amdgpu' is finally working with Athlon 200GE, on a motherboard
MSI B450M-A Pro Max,
with latest raven linux-firmware bundle for 19.50
Mauro
On Tue, Feb 11, 2020 at 7:20 PM Mauro Rossi wrote:
> Hi Felix,
>
> On Mon, Jan 27, 2020 at 10:34 AM Felix Kuehling
ecb3b794e2 "drm/amd/display: dc/clk_mgr: add support for SI parts (v2)"
Reported-by: kernel test robot
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/disp
Hello,
re-sending and copying full DL
On Wed, Jul 22, 2020 at 4:51 AM Alex Deucher wrote:
> On Mon, Jul 20, 2020 at 6:00 AM Mauro Rossi wrote:
> >
> > Hi Christian,
> >
> > On Mon, Jul 20, 2020 at 11:00 AM Christian König
> > wrote:
> > >
On Mon, Jul 27, 2020 at 8:31 PM Alex Deucher wrote:
> On Sun, Jul 26, 2020 at 11:31 AM Mauro Rossi
> wrote:
> >
> > Hello,
> >
> > On Fri, Jul 24, 2020 at 8:31 PM Alex Deucher
> wrote:
> >>
> >> On Wed, Jul 22, 2020 at 3:57 AM Mauro Ros
ons and continuous feedback.
I would suggest that Alex comments on the proposed next steps to follow.
Mauro
>
> Am 16.07.20 um 23:22 schrieb Mauro Rossi:
> > The series adds SI support to AMD DC
> >
> > Changelog:
> >
> > [RFC]
> > Preliminar Proof Of Concept, wi
)
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 34ae4f3a32f4..77569097a480 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers
[Why]
kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by
dce110
[How]
DCE6 set .cursor_lock = dce60_pipe_control_lock
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c | 1 +
1 file changed, 1 insertion(+)
diff --git
() in ipp_funcs dce60_ipp_funcs
Add DCE6 specific dce60_ipp_construct
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 46 ++
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h | 49
2 files changed, 95 insertions(+)
diff --git a/drivers
[Why]
hw_factory.c requires changes for DCE6 support
[How]
DCE6 targets added replicating and adapting existing DCE8 implementation.
(v2) changes due to following commit:
91db931 ("drm/amd/display: refactor gpio to allocate hw_container in
constructor")
Signed-off-by: M
[Why]
Asic info for SI parts need to be preliminarly added
[How]
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display
program visibility implementation
Fix a typo in the initial header includes comment 's/DCE8/DCE6/g'
Use dce60_apply_ctx_for_surface() in dce60_hw_sequencer_construct
Use dce60_pipe_control_lock() in dce60_hw_sequencer_construct
Signed-off-by: Mauro Rossi
---
.../amd/display/dc/dce60
dce60_program_size() fuction w/o Rotation processing
Add dce60_mi_program_surface_config() fuction
Use dce60_mi_program_display_marks() in dce60_mi_funcs
Use dce60_mi_program_surface_config() in dce60_mi_funcs
Add DCE6 specific dce60_mem_input_construct
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce
() function
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce60/dce60_resource.c | 89 +--
1 file changed, 42 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
index
and use it in vblank_int_entry(reg_num) macro definition
(v3) updated due to following kernel 5.3 commit:
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v4) updated due to following kernel 5.6 commit:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs"
of construct and destruct funcs")
f42ea55 ("drm/amd/display: add separate of private hwss functions")
(v9b) updated dce60 due to following kernel 5.8 commits:
bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
904fb6e ("drm/amd/display: mo
-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_link_encoder.c | 369 ++
.../drm/amd/display/dc/dce/dce_link_encoder.h | 38 ++
2 files changed, 407 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dce
() stub with no op
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 9 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 18 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
b/drivers/gpu/drm/amd
() in dce60_funcs
Add DCE specific dce60_audio_create
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/dc/dce/dce_audio.c| 131 ++
.../gpu/drm/amd/display/dc/dce/dce_audio.h| 23 +++
2 files changed, 154 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce
From: Alex Deucher
To help with the DC port.
v2: add missing masks, add additional registers
v3: more updates
v4: fix accidently dropped changes
v5: add missing nb pstate mask
v6: add vblank, vline masks
Signed-off-by: Alex Deucher
---
.../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 62
v7: add SCL_HORZ_FILTER_INIT regs
---
.../gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 16
.../amd/include/asic_reg/dce/dce_6_0_sh_mask.h | 12
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
e behavior of dce110_register_irq_handlers()
as per commit b57de80 ("drm/amd/display: Register on VLBLANK ISR.")
(v4) updated due to following kernel 5.2 commit:
b2fddb13 ("drm/amd/display: Drop underlay plane support")
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/displ
dce60_program_bit_depth_reduction()
Use dce60_transform_set_scaler() in dce60_transform_funcs
Use dce60_transform_set_pixel_storage_depth() in dce60_transform_funcs
Add DCE6 specific dce60_transform_construct
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_transform.c| 268
and dce60_is_tg_enabled() kept as static
Use dce60_configure_crc() function in dce60_tg_funcs
Signed-off-by: Mauro Rossi
---
.../display/dc/dce60/dce60_timing_generator.c | 57 +--
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 11
2 files changed, 50 insertions(+), 18 deletions(-)
diff
() with dce60_set_truncation
Use dce60_opp_program_fmt() in dce60_opp_funcs
Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs
Add DCE6 specific dce60_opp_construct
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 205 +++
drivers/gpu/drm/amd/display/dc/dce
[Why]
DCE6 chipsets do not support HW rotation
[How]
rotation property is created for Bonaire and later
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
ation")
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7b5f90ebb133..ca26714c8
file rules for dce60_clk_mgr.o target conditional to
CONFIG_DRM_AMD_DC_SI
Signed-off-by: Mauro Rossi
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 11 ++
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 6 +
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 174 ++
.../display/
[Why]
command_table_helper.c requires changes for DCE6 support
[How]
DCE6 targets added replicating and adapting the existing DCE8 implementation.
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8
Kaveri and older amdgpu.dc=1 kernel cmdline is required
(v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
remove CHIP_HAINAN support since it does not have physical DCE6 module
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dev
[Why]
DCE6 has no SMU_INTERRUPT_CONTROL register, but it's used for DCN10 and later
[How]
Add DCE6 specific macros definitions for DMCU registers and masks
DCE6 DMCU macros will avoid buiding errors when using DCE6 headers
There is no other change needed in dce_dcmu
Signed-off-by: Mauro Rossi
sclh_ratios_inits in dce_transform.h
Add dce60_calculate_inits() function
Add dce60_program_scl_ratios_inits() function
Fix dce60_transform_set_scaler() function
Signed-off-by: Mauro Rossi
---
.../drm/amd/display/dc/dce/dce_transform.c| 73 +--
.../drm/amd/display/dc/dce
[Why]
Issue in the Mouse cursor size in Linux Desktop Environments
[How]
In DCE6 dc->caps.max_cursor_size need to be set as 64 instead of 128
Signed-off-by: Mauro Rossi
---
drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
d
[PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2)
[PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2)
Signed-off-by: Mauro Rossi
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Mauro Rossi wrote:
> Hi all,
>
> with Android 14 QPR2 there were substantial changes in graphic stack's
> Android HAL (Hardware Abstraction Layer),
> essentially it became mandatory that hwcomposer HAL module supports AIDL
> Android Interface Definition Language,
>
> at t
Hi all,
with Android 14 QPR2 there were substantial changes in graphic stack's
Android HAL (Hardware Abstraction Layer),
essentially it became mandatory that hwcomposer HAL module supports AIDL
Android Interface Definition Language,
at the moment drm_hwcomposer does not support AIDL [1]
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