[PATCH] drm/amd/display: [FIX] Compilation error
[Why] ifdef mismatch. [How] Update to the correct flag. Signed-off-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 389ca0d54d1b..24f7fe374e13 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -189,7 +189,7 @@ #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define ABM_MASK_SH_LIST_DCN301(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) #endif -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: [FIX] Compilation error
[Why] ifdef mismatch. [How] Update to the correct flag. Signed-off-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 389ca0d54d1b..829cd9a93ba9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -189,7 +189,7 @@ #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) || defined(CONFIG_DRM_AMD_DC_DCN3_01) #define ABM_MASK_SH_LIST_DCN301(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) #endif -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: [FIX] update clock under two conditions
[Why]
Update clock only when non-seamless boot stream exists
creates regression on multiple scenerios.
[How]
Update clock in two conditions
1. Non-seamless boot stream exist.
2. Stream_count = 0
Fixes:06f9b1475d98("drm/amd/display: update clock
when non-seamless boot stream exist")
Signed-off-by: Lewis Huang
Acked-by: Qingqing Zhuo
Cc:
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1efc823c2a14..7e74ddc1c708 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1286,7 +1286,8 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
dc->optimize_seamless_boot_streams++;
}
- if (context->stream_count > dc->optimize_seamless_boot_streams)
+ if (context->stream_count > dc->optimize_seamless_boot_streams ||
+ context->stream_count == 0)
dc->hwss.prepare_bandwidth(dc, context);
disable_dangling_plane(dc, context);
@@ -1368,7 +1369,8 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
- if (context->stream_count > dc->optimize_seamless_boot_streams) {
+ if (context->stream_count > dc->optimize_seamless_boot_streams ||
+ context->stream_count == 0) {
/* Must wait for no flips to be pending before doing optimize
bw */
wait_for_no_pipes_pending(dc, context);
/* pplib is notified if disp_num changed */
--
2.17.1
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[PATCH 12/16] drm/amd/display: combine public interfaces into single header
From: Anthony Koo
[Why]
We want to better encapsulate all driver-fw dependencies into a single
file.
[How]
Combine all the headers under inc folder into a single header
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4 -
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 383 +-
.../drm/amd/display/dmub/inc/dmub_cmd_dal.h | 91 -
.../drm/amd/display/dmub/inc/dmub_cmd_vbios.h | 41 --
.../drm/amd/display/dmub/inc/dmub_fw_meta.h | 65 ---
.../drm/amd/display/dmub/inc/dmub_gpint_cmd.h | 75
.../gpu/drm/amd/display/dmub/inc/dmub_rb.h| 154 ---
.../gpu/drm/amd/display/dmub/inc/dmub_types.h | 78
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 +-
.../gpu/drm/amd/display/dmub/src/dmub_reg.h | 2 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
.../amd/display/modules/power/power_helpers.c | 2 +-
12 files changed, 374 insertions(+), 525 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 73b5d500ccf6..0ea702eeddad 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -64,11 +64,7 @@
* other component within DAL.
*/
-#include "inc/dmub_types.h"
#include "inc/dmub_cmd.h"
-#include "inc/dmub_gpint_cmd.h"
-#include "inc/dmub_cmd_dal.h"
-#include "inc/dmub_rb.h"
#if defined(__cplusplus)
extern "C" {
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 7782b7fc1ce0..48baf92a1cb5 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -26,20 +26,188 @@
#ifndef _DMUB_CMD_H_
#define _DMUB_CMD_H_
-#include "dmub_types.h"
-#include "dmub_cmd_dal.h"
-#include "dmub_cmd_vbios.h"
+#include
+#include
+#include
+#include
+#include
+
#include "atomfirmware.h"
-#define DMUB_RB_CMD_SIZE 64
-#define DMUB_RB_MAX_ENTRY 128
-#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
-#define REG_SET_MASK 0x
+
+//==
+/* Basic type definitions. */
#define SET_ABM_PIPE_GRADUALLY_DISABLE 0
#define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
#define SET_ABM_PIPE_NORMAL 1
+/* Maximum number of streams on any ASIC. */
+#define DMUB_MAX_STREAMS 6
+
+/* Maximum number of planes on any ASIC. */
+#define DMUB_MAX_PLANES 6
+
+#ifndef PHYSICAL_ADDRESS_LOC
+#define PHYSICAL_ADDRESS_LOC union large_integer
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef dmub_memcpy
+#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
+#endif
+
+#ifndef dmub_memset
+#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
+#endif
+
+#ifndef dmub_udelay
+#define dmub_udelay(microseconds) udelay(microseconds)
+#endif
+
+union dmub_addr {
+ struct {
+ uint32_t low_part;
+ uint32_t high_part;
+ } u;
+ uint64_t quad_part;
+};
+
+union dmub_psr_debug_flags {
+ struct {
+ uint8_t visual_confirm : 1;
+ } bitfields;
+
+ unsigned int u32All;
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+
+//==
+//=
+//==
+//<
DMUB_META>==
+//==
+#pragma pack(push, 1)
+
+/* Magic value for identifying dmub_fw_meta_info */
+#define DMUB_FW_META_MAGIC 0x444D5542
+
+/* Offset from the end of the file to the dmub_fw_meta_info */
+#define DMUB_FW_META_OFFSET 0x24
+
+/**
+ * struct dmub_fw_meta_info - metadata associated with fw binary
+ *
+ * NOTE: This should be considered a stable API. Fields should
+ * not be repurposed or reordered. New fields should be
+ * added instead to extend the structure.
+ *
+ * @magic_value: magic value identifying DMUB firmware meta info
+ * @fw_region_size: size of the firmware state region
+ * @trace_buffer_size: size of the tracebuffer region
+ * @fw_version: the firmware version information
+ */
+struct d
[PATCH 07/16] drm/amd/display: Increase Default Sizes of FW State and Trace Buffer
From: David Galiffi [WHY] To facilitate DM removing the dependency between dc and the firmware binary. [HOW] Setting the default values to match VBIOS: 64 KB. These values are only used if meta is absent. Signed-off-by: David Galiffi Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index d128b0639572..f50fc8a3344f 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -47,10 +47,10 @@ #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) /* Default state size if meta is absent. */ -#define DMUB_FW_STATE_SIZE (1024) +#define DMUB_FW_STATE_SIZE (64 * 1024) /* Default tracebuffer size if meta is absent. */ -#define DMUB_TRACE_BUFFER_SIZE (1024) +#define DMUB_TRACE_BUFFER_SIZE (64 * 1024) /* Default scratch mem size. */ #define DMUB_SCRATCH_MEM_SIZE (256) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/16] drm/amd/display: simplify dml log2 function
From: Dmytro Laktyushkin
Current implementation is slightly inaccurate and will often
result in truncation/floor operation decrementing an exact
integer output by 1.
Only rounded down output is ever expected, just extract the fp
exponent for this to increase performance and avoid any
truncation issues.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dml/dml_inline_defs.h | 20 ---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
index ab0870e2a103..479d7d83220c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
@@ -86,9 +86,20 @@ static inline double dml_round(double a)
return floor;
}
-static inline double dml_log2(double x)
+/* float
+static inline int dml_log2(float x)
{
- return (double) dcn_bw_log(x, 2);
+ unsigned int ix = *((unsigned int *));
+
+ return (int)((ix >> 23) & 0xff) - 127;
+}*/
+
+/* double */
+static inline int dml_log2(double x)
+{
+ unsigned long long ix = *((unsigned long long *));
+
+ return (int)((ix >> 52) & 0x7ff) - 1023;
}
static inline double dml_pow(double a, int exp)
@@ -116,11 +127,6 @@ static inline double dml_floor_ex(double x, double
granularity)
return (double) dcn_bw_floor2(x, granularity);
}
-static inline double dml_log(double x, double base)
-{
- return (double) dcn_bw_log(x, base);
-}
-
static inline unsigned int dml_round_to_multiple(unsigned int num,
unsigned int multiple,
unsigned char up)
--
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[PATCH 06/16] drm/amd/display: Handle link loss interrupt better
From: Aric Cyr
[Why]
Link loss currently only retrains and re-enables the stream. This can
cause issues for some sinks.
[How]
When link loss occurs, the link and stream(s) should be completely
disabled and then reenabled.
Signed-off-by: Aric Cyr
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 26 +++
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index b578687f2b38..08c3b32e188c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2849,7 +2849,6 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link,
union hpd_irq_data *out_hpd
enum dc_status result;
bool status = false;
struct pipe_ctx *pipe_ctx;
- struct dc_link_settings previous_link_settings;
int i;
if (out_link_loss)
@@ -2925,12 +2924,6 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link,
union hpd_irq_data *out_hpd
sizeof(hpd_irq_dpcd_data),
"Status: ");
- for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx =
>dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == link)
- link->dc->hwss.blank_stream(pipe_ctx);
- }
-
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
>dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == link)
@@ -2940,20 +2933,19 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link,
union hpd_irq_data *out_hpd
if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
return false;
- previous_link_settings = link->cur_link_settings;
- perform_link_training_with_retries(_link_settings,
- true, LINK_TRAINING_ATTEMPTS,
- pipe_ctx,
- pipe_ctx->stream->signal);
-
- if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- dc_link_reallocate_mst_payload(link);
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_ctx =
>dc->current_state->res_ctx.pipe_ctx[i];
+ if (pipe_ctx && pipe_ctx->stream &&
!pipe_ctx->stream->dpms_off &&
+ pipe_ctx->stream->link == link)
+ core_link_disable_stream(pipe_ctx);
+ }
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
>dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == link)
- link->dc->hwss.unblank_stream(pipe_ctx,
_link_settings);
+ if (pipe_ctx && pipe_ctx->stream &&
!pipe_ctx->stream->dpms_off &&
+ pipe_ctx->stream->link == link)
+
core_link_enable_stream(link->dc->current_state, pipe_ctx);
}
status = false;
--
2.17.1
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[PATCH 09/16] drm/amd/display: Guard against invalid array access
From: Aric Cyr
[Why]
There are scenarios where no OPP is assigned to an OTG so its value is
0xF which is outside the size of the OPP array causing a potential
driver crash.
[How]
Change the assert to an early return to guard against access. If
there's no OPP assigned already, then OTG will be blank anyways so no
functionality should be lost.
Signed-off-by: Aric Cyr
Reviewed-by: Zhan Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 26cac587c56b..223e314d26b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -291,12 +291,20 @@ void dcn20_init_blank(
/* get the OPTC source */
tg->funcs->get_optc_source(tg, _opps, _id_src0, _id_src1);
- ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
+
+ if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
+ ASSERT(false);
+ return;
+ }
opp = dc->res_pool->opps[opp_id_src0];
if (num_opps == 2) {
otg_active_width = otg_active_width / 2;
- ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
+
+ if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
+ ASSERT(false);
+ return;
+ }
bottom_opp = dc->res_pool->opps[opp_id_src1];
}
--
2.17.1
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[PATCH 13/16] drm/amd/display: enable plane if container of plane_status changed
From: Hugo Hu
[why]
We hit an issue which driver reallocate a pipe from desktop bottom
pipe to video bottom pipe. In this case, driver need to re-enable
plane.
[how]
Enable plane if container of plane status changed.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 223e314d26b4..13183bd7ea0f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1160,13 +1160,20 @@ void dcn20_pipe_control_lock(
static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct
pipe_ctx *new_pipe)
{
+ bool plane_state_update = false;
new_pipe->update_flags.raw = 0;
/* Exit on unchanged, unused pipe */
if (!old_pipe->plane_state && !new_pipe->plane_state)
return;
+
+ /* Detect plane state update */
+ if (old_pipe->plane_state && new_pipe->plane_state
+ && (old_pipe->plane_state != new_pipe->plane_state)) {
+ plane_state_update = true;
+ }
/* Detect pipe enable/disable */
- if (!old_pipe->plane_state && new_pipe->plane_state) {
+ if ((!old_pipe->plane_state && new_pipe->plane_state) ||
plane_state_update) {
new_pipe->update_flags.bits.enable = 1;
new_pipe->update_flags.bits.mpcc = 1;
new_pipe->update_flags.bits.dppclk = 1;
--
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[PATCH 15/16] drm/amd/display: Don't compare same stream for synchronized vblank
From: Alvin Lee
[Why]
When determining synchronzied vblank we don't need to compare the stream
with itself
[How]
If comparing same stream, continue to next iteration
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 4ffdbcbcdfd4..8bf7c5bc946c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2015,6 +2015,10 @@ int dcn20_populate_dml_pipes_from_context(
pipe_cnt = i;
continue;
}
+
+ if (res_ctx->pipe_ctx[pipe_cnt].stream ==
res_ctx->pipe_ctx[i].stream)
+ continue;
+
if (dc->debug.disable_timing_sync ||
!resource_are_streams_timing_synchronizable(
res_ctx->pipe_ctx[pipe_cnt].stream,
res_ctx->pipe_ctx[i].stream)) {
--
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[PATCH 16/16] drm/amd/display: 3.2.87
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 687faf83a54c..ecbdca6d4a79 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.86" +#define DC_VER "3.2.87" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/16] DC Patches May 25th, 2020
This DC patchset brings improvements in multiple areas. In summary, we have: * Fixes on HDCP, eDP, etc. * Enhancements on interrupt handling, code security and others. --- Alvin Lee (2): drm/amd/display: Disable PG on NV12 drm/amd/display: Don't compare same stream for synchronized vblank Anthony Koo (2): drm/amd/display: combine public interfaces into single header drm/amd/display: [FW Promotion] Release 1.0.12 Aric Cyr (5): drm/amd/display: 3.2.86 drm/amd/display: Fix potential integer wraparound resulting in a hang drm/amd/display: Handle link loss interrupt better drm/amd/display: Guard against invalid array access drm/amd/display: 3.2.87 Bhawanpreet Lakha (1): drm/amd/display: Fix incorrect HDCP caps for dongle David Galiffi (1): drm/amd/display: Increase Default Sizes of FW State and Trace Buffer Dmytro Laktyushkin (1): drm/amd/display: simplify dml log2 function Eric Bernstein (1): drm/amd/display: Allow Diagnostics test with eDP not connected Hugo Hu (1): drm/amd/display: enable plane if container of plane_status changed Paul Hsieh (2): drm/amd/display: link_status not align when power off encoder drm/amd/display: unit show garbage when do OPTC blank .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 26 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 4 +- .../display/dc/dce110/dce110_hw_sequencer.c | 2 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 21 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 10 +- .../drm/amd/display/dc/dml/dml_inline_defs.h | 20 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 391 +- .../drm/amd/display/dmub/inc/dmub_cmd_dal.h | 91 .../drm/amd/display/dmub/inc/dmub_cmd_vbios.h | 41 -- .../drm/amd/display/dmub/inc/dmub_fw_meta.h | 65 --- .../drm/amd/display/dmub/inc/dmub_gpint_cmd.h | 75 .../gpu/drm/amd/display/dmub/inc/dmub_rb.h| 154 --- .../gpu/drm/amd/display/dmub/inc/dmub_types.h | 78 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 +- .../gpu/drm/amd/display/dmub/src/dmub_reg.h | 2 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 6 +- .../amd/display/modules/power/power_helpers.c | 2 +- 23 files changed, 453 insertions(+), 568 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/16] drm/amd/display: unit show garbage when do OPTC blank
From: Paul Hsieh
[Why]
Unit enter to S4, garbage show on screen when do OPTC blank.
[How]
Wait for vblank then do OPTC blank
Signed-off-by: Paul Hsieh
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0313ca83cdb9..deaafb4782d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2581,8 +2581,10 @@ void dcn10_blank_pixel_data(
}
} else if (blank) {
dc->hwss.set_abm_immediate_disable(pipe_ctx);
- if (stream_res->tg->funcs->set_blank)
+ if (stream_res->tg->funcs->set_blank) {
+ stream_res->tg->funcs->wait_for_state(stream_res->tg,
CRTC_STATE_VBLANK);
stream_res->tg->funcs->set_blank(stream_res->tg, blank);
+ }
}
}
--
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[PATCH 03/16] drm/amd/display: Fix incorrect HDCP caps for dongle
From: Bhawanpreet Lakha
[Why]
Previously we used link signal type to get the caps. We should use the
sink signal type
[How]
Use sink signal type instead of link signal type
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 ++--
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8
drivers/gpu/drm/amd/display/dc/dc_link.h | 4 ++--
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 076af267b488..7b8968baaeb9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -859,8 +859,8 @@ static int hdcp_sink_capability_show(struct seq_file *m,
void *data)
seq_printf(m, "%s:%d HDCP version: ", connector->name,
connector->base.id);
- hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link);
- hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link);
+ hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link,
aconnector->dc_sink->sink_signal);
+ hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link,
aconnector->dc_sink->sink_signal);
if (hdcp_cap)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d80b2de3ee82..c00f656e22ff 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -521,11 +521,11 @@ static void link_disconnect_remap(struct dc_sink
*prev_sink, struct dc_link *lin
}
#if defined(CONFIG_DRM_AMD_DC_HDCP)
-bool dc_link_is_hdcp14(struct dc_link *link)
+bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
{
bool ret = false;
- switch (link->connector_signal) {
+ switch (signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
@@ -545,11 +545,11 @@ bool dc_link_is_hdcp14(struct dc_link *link)
return ret;
}
-bool dc_link_is_hdcp22(struct dc_link *link)
+bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
{
bool ret = false;
- switch (link->connector_signal) {
+ switch (signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 5c60c2f9779a..aec514e52e4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -312,8 +312,8 @@ bool dc_link_detect_sink(struct dc_link *link, enum
dc_connection_type *type);
*/
#ifdef CONFIG_DRM_AMD_DC_HDCP
-bool dc_link_is_hdcp14(struct dc_link *link);
-bool dc_link_is_hdcp22(struct dc_link *link);
+bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
+bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
#endif
void dc_link_set_drive_settings(struct dc *dc,
struct link_training_settings *lt_settings,
--
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[PATCH 01/16] drm/amd/display: 3.2.86
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 11ac4b7ab174..687faf83a54c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.85" +#define DC_VER "3.2.86" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/16] drm/amd/display: [FW Promotion] Release 1.0.12
From: Anthony Koo [Header Changes] - Combine all interface dependencies between driver and fw into a single header file - Add FW Versioning to the dmub_cmd.h file Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 48baf92a1cb5..15ff4e471c3d 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -34,6 +34,14 @@ #include "atomfirmware.h" +/* Firmware versioning. */ +#ifdef DMUB_EXPOSE_VERSION +#define DMUB_FW_VERSION_GIT_HASH 0x718f63a96 +#define DMUB_FW_VERSION_MAJOR 1 +#define DMUB_FW_VERSION_MINOR 0 +#define DMUB_FW_VERSION_REVISION 12 +#define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) | (DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION) +#endif //== /* Basic type definitions. */ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/16] drm/amd/display: link_status not align when power off encoder
From: Paul Hsieh [Why] The link_status is incorrect cause driver power off eDP when backlight on. Some eDP panels may show garbage on screen. [How] Correct link_status when power off encoder Signed-off-by: Paul Hsieh Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index a475e529ae1c..2ec5e9e1bdc6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1443,6 +1443,8 @@ static void power_down_encoders(struct dc *dc) dc->links[i]->link_enc->funcs->disable_output( dc->links[i]->link_enc, signal); + + dc->links[i]->link_status.link_active = false; } } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/16] drm/amd/display: Allow Diagnostics test with eDP not connected
From: Eric Bernstein
[Why]
Diagnostics DIO test with eDP not connected is required to run
[How]
Allow Diagnostics test with eDP not connected to skip link detection but
still execute DIO test
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 45cfb7c45566..04c3d9f7e323 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -186,9 +186,10 @@ static bool create_links(
bool should_destory_link = false;
if (link->connector_signal == SIGNAL_TYPE_EDP) {
- if (dc->config.edp_not_connected)
- should_destory_link = true;
- else if (dc->debug.remove_disconnect_edp) {
+ if (dc->config.edp_not_connected) {
+ if
(!IS_DIAG_DC(dc->ctx->dce_environment))
+ should_destory_link = true;
+ } else {
enum dc_connection_type type;
dc_link_detect_sink(link, );
if (type == dc_connection_none)
--
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[PATCH 05/16] drm/amd/display: Fix potential integer wraparound resulting in a hang
From: Aric Cyr [Why] If VUPDATE_END is before VUPDATE_START the delay calculated can become very large, causing a soft hang. [How] Take the absolute value of the difference between START and END. Signed-off-by: Aric Cyr Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 4db6ec96eea1..0313ca83cdb9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1742,6 +1742,8 @@ static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx) return; /* Stall out until the cursor update completes. */ + if (vupdate_end < vupdate_start) + vupdate_end += stream->timing.v_total; us_vupdate = (vupdate_end - vupdate_start + 1) * us_per_line; udelay(us_to_vupdate + us_vupdate); } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/16] drm/amd/display: Disable PG on NV12
From: Alvin Lee
[Why]
HW team request to disable PG on NV12 (fixing missed cases)
[How]
Disable dpp and hubp PG
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 99925079a55d..4ffdbcbcdfd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -4053,8 +4053,12 @@ static bool dcn20_resource_construct(
// to be consumed. We could have created dcn20_init_hw to get
// the same effect by checking ASIC rev, but there was a
// request at some point to not check ASIC rev on hw sequencer.
- if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
+ if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
dc->hwseq->funcs.enable_power_gating_plane = NULL;
+ dc->debug.disable_dpp_power_gate = true;
+ dc->debug.disable_hubp_power_gate = true;
+ }
+
dc->caps.max_planes = pool->base.pipe_count;
--
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[PATCH 11/15] drm/amd/display: Implement PSR wait for enable/disable
From: Wyatt Wood
[Why]
For DMUB implementation of PSR, the 'wait' parameter,
used to determine if driver should wait for PSR enable/disable,
is not implemented correctly.
[How]
Implement wait for PSR enable/disable.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 27 ++-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 +-
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1871ff6119ae..f13396254b5d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2566,7 +2566,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link,
bool allow_active, bool
link->psr_settings.psr_allow_active = allow_active;
if (psr != NULL && link->psr_settings.psr_feature_enabled)
- psr->funcs->psr_enable(psr, allow_active);
+ psr->funcs->psr_enable(psr, allow_active, wait);
else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
link->psr_settings.psr_feature_enabled)
dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
else
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 5167d6b8a48d..bf24f1029547 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -119,10 +119,11 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub,
struct dc_stream_state *
/**
* Enable/Disable PSR.
*/
-static void dmub_psr_enable(struct dmub_psr *dmub, bool enable)
+static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
{
union dmub_rb_cmd cmd;
struct dc_context *dc = dmub->ctx;
+ uint32_t retry_count, psr_state = 0;
cmd.psr_enable.header.type = DMUB_CMD__PSR;
@@ -136,6 +137,30 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool
enable)
dc_dmub_srv_cmd_queue(dc->dmub_srv, );
dc_dmub_srv_cmd_execute(dc->dmub_srv);
dc_dmub_srv_wait_idle(dc->dmub_srv);
+
+ /* Below loops 1000 x 500us = 500 ms.
+* Exit PSR may need to wait 1-2 frames to power up. Timeout after at
+* least a few frames. Should never hit the max retry assert below.
+*/
+ if (wait) {
+ for (retry_count = 0; retry_count <= 1000; retry_count++) {
+ dmub_psr_get_state(dmub, _state);
+
+ if (enable) {
+ if (psr_state != 0)
+ break;
+ } else {
+ if (psr_state == 0)
+ break;
+ }
+
+ udelay(500);
+ }
+
+ /* assert if max retry hit */
+ if (retry_count >= 1000)
+ ASSERT(0);
+ }
}
/**
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index f404fecd6410..dc121ed92d2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -36,7 +36,7 @@ struct dmub_psr {
struct dmub_psr_funcs {
bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
struct psr_context *psr_context);
- void (*psr_enable)(struct dmub_psr *dmub, bool enable);
+ void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait);
void (*psr_get_state)(struct dmub_psr *dmub, uint32_t *psr_state);
void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
};
--
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[PATCH 10/15] drm/amd/display: allow DP RX to use more cr aux rd interval delay
From: Wenjing Liu
[why]
Regression is caused by previous change with attempt to correct the
extended cr aux rd interval delay due to mis interpretation of the DP specs.
I4b4f508e30e5218ffeb7e40cc19e6dc54357361e
The change turns out not working well with certain RXs.
So we decided to keep the cr aux rd interval logic as before.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 47fb09f41bfb..232d77721ad9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -49,6 +49,23 @@ static struct dc_link_settings
get_common_supported_link_settings(
struct dc_link_settings link_setting_a,
struct dc_link_settings link_setting_b);
+static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
+ const struct dc_link_settings *link_settings)
+{
+ union training_aux_rd_interval training_rd_interval;
+ uint32_t wait_in_micro_secs = 100;
+
+ memset(_rd_interval, 0, sizeof(training_rd_interval));
+ core_link_read_dpcd(
+ link,
+ DP_TRAINING_AUX_RD_INTERVAL,
+ (uint8_t *)_rd_interval,
+ sizeof(training_rd_interval));
+ if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
+ wait_in_micro_secs =
training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
+ return wait_in_micro_secs;
+}
+
static uint32_t get_eq_training_aux_rd_interval(
struct dc_link *link,
const struct dc_link_settings *link_settings)
@@ -1251,7 +1268,7 @@ static void initialize_training_settings(
if (overrides->cr_pattern_time != NULL)
lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
else
- lt_settings->cr_pattern_time = 100;
+ lt_settings->cr_pattern_time =
get_cr_training_aux_rd_interval(link, link_setting);
if (overrides->eq_pattern_time != NULL)
lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
--
2.17.1
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[PATCH 05/15] drm/amd/display: Bug in dce_is_panel_backlight_on()
From: Peikang Zhang
[Why]
dce_is_panel_backlight_on() will return wrong value if
LVTMA_BLON_OVRD is 0
[How]
When LVTMA_BLON_OVRD is 0, read
LVTMA_PWRSEQ_TARGET_STATE instead
Signed-off-by: Peikang Zhang
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c | 10 +++---
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 4
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index df7f826eebd8..74f7619d4154 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -159,11 +159,15 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl
*panel_cntl)
static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
{
struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
- uint32_t value;
+ uint32_t blon, blon_ovrd, pwrseq_target_state;
- REG_GET(PWRSEQ_CNTL, LVTMA_BLON, );
+ REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, , LVTMA_BLON_OVRD, _ovrd);
+ REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, _target_state);
- return value;
+ if (blon_ovrd)
+ return blon;
+ else
+ return pwrseq_target_state;
}
static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
index 967d04d75b98..6bd1196083a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
@@ -61,8 +61,10 @@
#define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+ DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON_OVRD, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
+ DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE,
mask_sh), \
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R,
mask_sh), \
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
@@ -76,8 +78,10 @@
#define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
type LVTMA_BLON;\
+ type LVTMA_BLON_OVRD;\
type LVTMA_DIGON;\
type LVTMA_DIGON_OVRD;\
+ type LVTMA_PWRSEQ_TARGET_STATE; \
type LVTMA_PWRSEQ_TARGET_STATE_R; \
type BL_PWM_REF_DIV; \
type BL_PWM_EN; \
--
2.17.1
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[PATCH 07/15] drm/amd/display: Fix ODM policy implementation
From: Wesley Chalmers
[WHY]
Only the leftmost ODM pipe should be offset when scaling. A previous
code change was intended to implement this policy, but a section of code
was overlooked.
Signed-off-by: Wesley Chalmers
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Cc:
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4cea9344d8aa..e430148e47cf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -785,14 +785,15 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
/*
* Only the leftmost ODM pipe should be offset by a nonzero distance
*/
- if (!pipe_ctx->prev_odm_pipe)
+ if (!pipe_ctx->prev_odm_pipe) {
data->recout.x = stream->dst.x;
- else
- data->recout.x = 0;
- if (stream->src.x < surf_clip.x)
- data->recout.x += (surf_clip.x - stream->src.x) *
stream->dst.width
+ if (stream->src.x < surf_clip.x)
+ data->recout.x += (surf_clip.x - stream->src.x) *
stream->dst.width
/ stream->src.width;
+ } else
+ data->recout.x = 0;
+
data->recout.width = surf_clip.width * stream->dst.width /
stream->src.width;
if (data->recout.width + data->recout.x > stream->dst.x +
stream->dst.width)
data->recout.width = stream->dst.x + stream->dst.width -
data->recout.x;
--
2.17.1
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[PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN
From: David Galiffi [Why] Typo in backlight refactor introduced wrong register offset. [How] SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2). Signed-off-by: David Galiffi Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h index 99c68ca9c7e0..967d04d75b98 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h @@ -54,7 +54,7 @@ SR(BL_PWM_CNTL2), \ SR(BL_PWM_PERIOD_CNTL), \ SR(BL_PWM_GRP1_REG_LOCK), \ - SR(BIOS_SCRATCH_2) + NBIO_SR(BIOS_SCRATCH_2) #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/15] drm/amd/display: Check for flip pending before locking pipes.
From: Taimur Hassan
[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.
[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.
Signed-off-by: Taimur Hassan
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 12 ++--
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h| 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h| 2 +-
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 83ce55edb3aa..1efc823c2a14 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2324,7 +2324,6 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
- bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2355,14 +2354,8 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
- if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock &&
- dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
- dc->hwss.interdependent_update_lock(dc, context, true);
- mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
- dc->hwss.interdependent_update_lock(dc, context, false);
- if (mpcc_disconnected)
- dc->hwss.wait_for_pending_cleared(dc, context);
- }
+ if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
+ dc->hwss.disconnect_pipes(dc, context);
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f3bf953d02..79fe9571cf5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
-bool dcn10_disconnect_pipes(
+void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context)
{
@@ -2772,6 +2772,10 @@ bool dcn10_disconnect_pipes(
bool mpcc_disconnected = false;
struct pipe_ctx *old_pipe;
struct pipe_ctx *new_pipe;
+
+ dc->hwss.wait_for_pending_cleared(dc, context);
+ dc->hwss.interdependent_update_lock(dc, context, true);
+
DC_LOGGER_INIT(dc->ctx->logger);
/* Set pipe update flags and lock pipes */
@@ -2874,7 +2878,11 @@ bool dcn10_disconnect_pipes(
}
}
}
- return mpcc_disconnected;
+
+ dc->hwss.interdependent_update_lock(dc, context, false);
+
+ if (mpcc_disconnected)
+ dc->hwss.wait_for_pending_cleared(dc, context);
}
void dcn10_wait_for_pending_cleared(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index e5691e499023..9a0f7a8a85cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
-bool dcn10_disconnect_pipes(
+void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..f48ee24d42f9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
- bool (*disconnect_pipes)(struct dc *dc,
+ voi
[PATCH 09/15] drm/amd/display: Enable DP YCbCr420 mode support for DCN10
From: Gary Li
[WHY]
In DCN10 when a panel with YCbCr420 capability is connected via
USB-C to HDMI active dongle, no YCbCr420 option is listed in
Radeon settings.
[HOW]
Enable DP YCbCr420 mode support for DCN10
Signed-off-by: Gary Li
Reviewed-by: Eric Yang
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 1abd81e17f09..a78712caf124 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -798,7 +798,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 60,
.hdmi_ycbcr420_supported = true,
- .dp_ycbcr420_supported = false,
+ .dp_ycbcr420_supported = true,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
--
2.17.1
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[PATCH 15/15] drm/amd/display: 3.2.104
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d65483483d05..061ca15660ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.103" +#define DC_VER "3.2.104" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/15] DC Patches September 21, 2020
This DC patchset brings improvements in multiple areas. In summary, we have: * DC version 3.2.104. * DMUB Firmware release 0.0.34. * Improve on HDMI fallback mechanism. * Enable DP YCbCr420 mode support for DCN10 ASICs. * Bug fixes for backlight, ODM, eDP and others. -- Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.33 drm/amd/display: [FW Promotion] Release 0.0.34 Aric Cyr (2): drm/amd/display: 3.2.103 drm/amd/display: 3.2.104 Chris Park (1): drm/amd/display: TMDS Fallback transition David Galiffi (1): drm/amd/display: Fix incorrect backlight register offset for DCN Gary Li (1): drm/amd/display: Enable DP YCbCr420 mode support for DCN10 Peikang Zhang (2): drm/amd/display: Bug in dce_is_panel_backlight_on() drm/amd/display: eDP intermittent black screen during PnP Taimur Hassan (1): drm/amd/display: Check for flip pending before locking pipes. Wenjing Liu (1): drm/amd/display: allow DP RX to use more cr aux rd interval delay Wesley Chalmers (2): drm/amd/display: Fix ODM policy implementation drm/amd/display: Increase timeout for DP Disable Wyatt Wood (1): drm/amd/display: Implement PSR wait for enable/disable jinlong zhang (1): drm/amd/display: Replace msleep with udelay while read edid return defer. .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 + drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 - .../drm/amd/display/dc/core/dc_link_hwss.c| 2 ++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 11 drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +- .../drm/amd/display/dc/dce/dce_panel_cntl.c | 10 --- .../drm/amd/display/dc/dce/dce_panel_cntl.h | 6 - drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 27 ++- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 +- .../display/dc/dce110/dce110_hw_sequencer.c | 1 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 +++-- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../display/dc/dcn10/dcn10_stream_encoder.c | 4 +-- .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +--- 24 files changed, 113 insertions(+), 34 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/15] drm/amd/display: eDP intermittent black screen during PnP
From: Peikang Zhang
[Why]
We dont's turn off backlight before power off eDP (VDD),
which is a violation of eDP specs.
[How]
Power off eDP backlight before power off eDP
Signed-off-by: Peikang Zhang
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 ++
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 +
6 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 81c026319ccd..dba338c88256 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -229,6 +229,8 @@ void dp_disable_link_phy(struct dc_link *link, enum
signal_type signal)
dp_receiver_power_ctrl(link, false);
if (signal == SIGNAL_TYPE_EDP) {
+ if (link->dc->hwss.edp_backlight_control)
+ link->dc->hwss.edp_backlight_control(link, false);
link->link_enc->funcs->disable_output(link->link_enc, signal);
link->dc->hwss.edp_power_control(link, false);
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1002ce9979dc..27a1262a20f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2890,6 +2890,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.setup_stereo = NULL,
.set_avmute = dce110_set_avmute,
.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dce110_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index a1d1559bb5d7..b24c8ae8b1ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -66,6 +66,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 966e1790b9bf..072193c5ffe6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -68,6 +68,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 2ba880c3943c..2b7396c9fcb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -69,6 +69,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 19daa456e3bf..7c90c506 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -69,6 +69,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
[PATCH 03/15] drm/amd/display: 3.2.103
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d9b22d6a985a..d65483483d05 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.102" +#define DC_VER "3.2.103" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
From: jinlong zhang
[why]
while read edid return defer, then it enter to msleep,
but it actually took more time during msleep,
this will cause remaining edid read fail.
[how]
Replacing msleep with udelay, it will not take any extra time, edid return pass
finally.
Signed-off-by: jinlong zhang
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 743042d5905a..cdcad82765e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
if ((*payload->reply ==
AUX_TRANSACTION_REPLY_AUX_DEFER) ||
(*payload->reply ==
AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
if (payload->defer_delay > 0)
-
msleep(payload->defer_delay);
+
udelay(payload->defer_delay * 1000);
}
}
break;
--
2.17.1
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[PATCH 02/15] drm/amd/display: [FW Promotion] Release 0.0.33
From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a0bd502dc7d7..f20d6df6def1 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -36,10 +36,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x82f998da6 +#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 32 +#define DMUB_FW_VERSION_REVISION 33 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/15] drm/amd/display: [FW Promotion] Release 0.0.34
From: Anthony Koo
[Header Changes]
- Add new SCRATCH0 status bits for detecting restore state
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f20d6df6def1..137613a60419 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b
+#define DMUB_FW_VERSION_GIT_HASH 0xf547f0b9d
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 33
+#define DMUB_FW_VERSION_REVISION 34
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -170,7 +170,7 @@ union dmub_fw_boot_status {
uint32_t dal_fw : 1;
uint32_t mailbox_rdy : 1;
uint32_t optimized_init_done : 1;
- uint32_t reserved : 29;
+ uint32_t restore_required : 1;
} bits;
uint32_t all;
};
@@ -179,6 +179,7 @@ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1),
DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2),
+ DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3),
};
/* Register bit definition for SCRATCH15 */
@@ -301,6 +302,10 @@ enum dmub_cmd_type {
DMUB_CMD__VBIOS = 128,
};
+enum dmub_out_cmd_type {
+ DMUB_OUT_CMD__NULL = 0,
+};
+
#pragma pack(push, 1)
struct dmub_cmd_header {
--
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[PATCH 13/15] drm/amd/display: TMDS Fallback transition
From: Chris Park
[Why]
HDMI requires fallback to TMDS by redetection
in order to switch PHY settings.
This avoids black out when link training fail
during mode setting, link quality update,
disable driver sequence.
[How]
Allow driver to redetect HDMI displays
based on retraining or fallback mechanism.
Signed-off-by: Chris Park
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 +
drivers/gpu/drm/amd/display/dc/dc_link.h| 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 0b9a4fc642ae..98b4d5e2e336 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -158,7 +158,20 @@ static bool validate_dsc_caps_on_connector(struct
amdgpu_dm_connector *aconnecto
u8 dsc_caps[16] = { 0 };
aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
+#if defined(CONFIG_HP_HOOK_WORKAROUND)
+ /*
+* drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
+* because it only check the dsc/fec caps of the "port variable" and
not the dock
+*
+* This case will return NULL: DSC capabe MST dock connected to a non
fec/dsc capable display
+*
+* Workaround: explicitly check the use case above and use the mst
dock's aux as dsc_aux
+*
+*/
+ if (!aconnector->dsc_aux && !port->parent->port_parent)
+ aconnector->dsc_aux = >mst_port->dm_dp_aux.aux;
+#endif
if (!aconnector->dsc_aux)
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index e002ef706e1d..266b93a705d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -237,6 +237,8 @@ enum dc_detect_reason {
DETECT_REASON_BOOT,
DETECT_REASON_HPD,
DETECT_REASON_HPDRX,
+ DETECT_REASON_FALLBACK,
+ DETECT_REASON_RETRAIN
};
bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
--
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[PATCH 08/15] drm/amd/display: Increase timeout for DP Disable
From: Wesley Chalmers [WHY] When disabling DP video, the current REG_WAIT timeout of 50ms is too low for certain cases with very high VSYNC intervals. [HOW] Increase the timeout to 102ms, so that refresh rates as low as 10Hz can be handled properly. Signed-off-by: Wesley Chalmers Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 9cf139be3f40..f70fcadf1ee5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -896,10 +896,10 @@ void enc1_stream_encoder_dp_blank( */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); /* Larger delay to wait until VBLANK - use max retry of -* 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode + +* 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + * a little more because we may not trust delay accuracy. */ - max_retries = DP_BLANK_MAX_RETRY * 250; + max_retries = DP_BLANK_MAX_RETRY * 501; /* disable DP stream */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/25] drm/amd/display: Update connector on DSC property change
From: Eryk Brol
[Why]
We want to trigger atomic check on connector when
DSC debugfs properties are changed. The previous
method was reverted because it accessed connector
properties unsafely and would also heavily
impact performance.
[How]
Add a flag for forcing DSC update in CRTC state
and add connector to the state if the flag is set.
Signed-off-by: Eryk Brol
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 124 ++
3 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdb1fa72061a..345eb2130869 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8773,6 +8773,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
enum dc_status status;
int ret, i;
bool lock_and_validation_needed = false;
+ struct dm_crtc_state *dm_old_crtc_state;
trace_amdgpu_dm_atomic_check_begin(state);
@@ -8815,9 +8816,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
}
#endif
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
+ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
!new_crtc_state->color_mgmt_changed &&
- old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
+ old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled
&&
+ dm_old_crtc_state->dsc_force_changed == false)
continue;
if (!new_crtc_state->enable)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 6057eb6bc362..9bf141aa660c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -440,6 +440,7 @@ struct dm_crtc_state {
bool freesync_timing_changed;
bool freesync_vrr_info_changed;
+ bool dsc_force_changed;
bool vrr_supported;
struct mod_freesync_config freesync_config;
struct dc_info_packet vrr_infopacket;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8cd646eef096..5c72ebd5998f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1253,6 +1253,10 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+ struct drm_connector *connector = >base;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc = NULL;
+ struct dm_crtc_state *dm_crtc_state = NULL;
struct pipe_ctx *pipe_ctx;
int i;
char *wr_buf = NULL;
@@ -1295,6 +1299,25 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
if (!pipe_ctx || !pipe_ctx->stream)
goto done;
+ // Get CRTC state
+ mutex_lock(>mode_config.mutex);
+ drm_modeset_lock(>mode_config.connection_mutex, NULL);
+
+ if (connector->state == NULL)
+ goto unlock;
+
+ crtc = connector->state->crtc;
+ if (crtc == NULL)
+ goto unlock;
+
+ drm_modeset_lock(>mutex, NULL);
+ if (crtc->state == NULL)
+ goto unlock;
+
+ dm_crtc_state = to_dm_crtc_state(crtc->state);
+ if (dm_crtc_state->stream == NULL)
+ goto unlock;
+
if (param[0] == 1)
aconnector->dsc_settings.dsc_force_enable =
DSC_CLK_FORCE_ENABLE;
else if (param[0] == 2)
@@ -1302,6 +1325,14 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
else
aconnector->dsc_settings.dsc_force_enable =
DSC_CLK_FORCE_DEFAULT;
+ dm_crtc_state->dsc_force_changed = true;
+
+unlock:
+ if (crtc)
+ drm_modeset_unlock(>mutex);
+ drm_modeset_unlock(>mode_config.connection_mutex);
+ mutex_unlock(>mode_config.mutex);
+
done:
kfree(wr_buf);
return size;
@@ -1408,6 +1439,10 @@ static ssize_t dp_dsc_slice_width_write(struct file *f,
const char __user *buf,
{
struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
struct pipe_ctx *pipe_ctx;
+ struct drm_connector *connector = >base;
+ struct drm_dev
[PATCH 18/25] drm/amd/display: Calculate CRC on specific frame region
From: Wayne Lin
[why]
Currently, we only support calculating CRC on whole frame.
We want to extend the capability to calculate CRC on
specific frame area.
[how]
Calculate CRC on specific area once it's specified from the
input parameter.
Signed-off-by: Wayne Lin
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index d0699e98db92..c29dc11619f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -115,7 +115,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc
*crtc,
/* Enable CRTC CRC generation if necessary. */
if (dm_is_crc_source_crtc(source)) {
if (!dc_stream_configure_crc(stream_state->ctx->dc,
-stream_state, enable, enable)) {
+stream_state, NULL, enable,
enable)) {
ret = -EINVAL;
goto unlock;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 18154eea09f8..34e76fdc1334 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -346,7 +346,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
* calculate the crc.
*/
bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
-bool enable, bool continuous)
+struct crc_params *crc_window, bool enable, bool
continuous)
{
int i;
struct pipe_ctx *pipe;
@@ -362,7 +362,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct
dc_stream_state *stream,
if (i == MAX_PIPES)
return false;
- /* Always capture the full frame */
+ /* By default, capture the full frame */
param.windowa_x_start = 0;
param.windowa_y_start = 0;
param.windowa_x_end = pipe->stream->timing.h_addressable;
@@ -372,6 +372,17 @@ bool dc_stream_configure_crc(struct dc *dc, struct
dc_stream_state *stream,
param.windowb_x_end = pipe->stream->timing.h_addressable;
param.windowb_y_end = pipe->stream->timing.v_addressable;
+ if (crc_window) {
+ param.windowa_x_start = crc_window->windowa_x_start;
+ param.windowa_y_start = crc_window->windowa_y_start;
+ param.windowa_x_end = crc_window->windowa_x_end;
+ param.windowa_y_end = crc_window->windowa_y_end;
+ param.windowb_x_start = crc_window->windowb_x_start;
+ param.windowb_y_start = crc_window->windowb_y_start;
+ param.windowb_x_end = crc_window->windowb_x_end;
+ param.windowb_y_end = crc_window->windowb_y_end;
+ }
+
param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
param.odm_mode = pipe->next_odm_pipe ? 1:0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 82a35d008094..e37720344819 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -457,6 +457,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
bool dc_stream_configure_crc(struct dc *dc,
struct dc_stream_state *stream,
+struct crc_params *crc_window,
bool enable,
bool continuous);
--
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[PATCH 09/25] drm/amd/display: 3.2.109
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c74be6dafafc..273963e8e61a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.108" +#define DC_VER "3.2.109" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/25] drm/amd/display: Keep GSL for full updates with planes that flip VSYNC
From: Alvin Lee
[Why]
When enabling PIP in Heaven, the PIP planes are VSYNC
flip and is also the top-most pipe. In this case GSL
will be disabled because we only check immediate flip
for the top pipe. However, the desktop planes are still
flip immediate so we should at least keep GSL on until
the full update.
[How]
Check each pipe in the tree to see if any planes
are flip immediate. Maintain the GSL lock if yes,
and take it down after when unlocking if any planes
are flipping VSYNC. Keeping GSL on with VSYNC +
flip immediate planes causes corruption.
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 71499c131947..3b26396cbc5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1158,6 +1158,7 @@ void dcn20_pipe_control_lock(
struct pipe_ctx *pipe,
bool lock)
{
+ struct pipe_ctx *temp_pipe;
bool flip_immediate = false;
/* use TG master update lock to lock everything on the TG
@@ -1169,6 +1170,13 @@ void dcn20_pipe_control_lock(
if (pipe->plane_state != NULL)
flip_immediate = pipe->plane_state->flip_immediate;
+ temp_pipe = pipe->bottom_pipe;
+ while (!flip_immediate && temp_pipe) {
+ if (temp_pipe->plane_state != NULL)
+ flip_immediate = temp_pipe->plane_state->flip_immediate;
+ temp_pipe = temp_pipe->bottom_pipe;
+ }
+
if (flip_immediate && lock) {
const int TIMEOUT_FOR_FLIP_PENDING = 10;
int i;
@@ -1196,6 +1204,17 @@ void dcn20_pipe_control_lock(
(!flip_immediate && pipe->stream_res.gsl_group > 0))
dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
+ temp_pipe = pipe->bottom_pipe;
+ while (flip_immediate && temp_pipe) {
+ if (temp_pipe->plane_state != NULL)
+ flip_immediate = temp_pipe->plane_state->flip_immediate;
+ temp_pipe = temp_pipe->bottom_pipe;
+ }
+
+ if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
+ !flip_immediate)
+ dcn20_setup_gsl_group_as_lock(dc, pipe, false);
+
if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
--
2.17.1
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[PATCH 13/25] drm/amd/display: correct eDP T9 delay
From: Hugo Hu
[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.
[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.
Signed-off-by: Hugo Hu
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 -
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 16
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 1 +
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 11a619befb42..124ce215fca5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -156,6 +156,13 @@ void dp_enable_link_phy(
dp_receiver_power_ctrl(link, true);
}
+void edp_add_delay_for_T9(struct dc_link *link)
+{
+ if (link->local_sink &&
+
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
+
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off *
1000);
+}
+
bool edp_receiver_ready_T9(struct dc_link *link)
{
unsigned int tries = 0;
@@ -165,7 +172,7 @@ bool edp_receiver_ready_T9(struct dc_link *link)
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, ,
sizeof(edpRev));
- /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
if (result == DC_OK && edpRev >= DP_EDP_12) {
do {
sinkstatus = 1;
@@ -178,10 +185,6 @@ bool edp_receiver_ready_T9(struct dc_link *link)
} while (++tries < 50);
}
- if (link->local_sink &&
-
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
-
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off *
1000);
-
return result;
}
bool edp_receiver_ready_T7(struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3ac6c7b65a45..9f56887029ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -992,8 +992,6 @@ void dce110_edp_backlight_control(
link_transmitter_control(ctx->dc_bios, );
-
-
if (enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_POST_T7_DELAY);
@@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control(
/*edp 1.2*/
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
- edp_receiver_ready_T9(link);
+ edp_add_delay_for_T9(link);
if (!enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_PRE_T11_DELAY);
@@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
- /*
-* After output is idle pattern some sinks need time to
recognize the stream
-* has changed or they enter protection state and hang.
-*/
- if (!dc_is_embedded_signal(pipe_ctx->stream->signal))
+ if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
+ /*
+* After output is idle pattern some sinks need time to
recognize the stream
+* has changed or they enter protection state and hang.
+*/
msleep(60);
+ } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+ edp_receiver_ready_T9(link);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 9af7ee5bc8ee..33590a728fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -51,6 +51,7 @@ void dp_enable_link_phy(
const struct dc_link_settings *link_settings);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);
--
2.17.1
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[PATCH 25/25] drm/amd/display: fix recout calculation for left side clip
From: Dmytro Laktyushkin Recout calculation does not corrrectly handle plane clip rect that extends beyond the left most border of stream source rect. This change adds handling by truncating the invisible clip rect. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Hersen Wu Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index d49a8b3e5137..998d87b852a7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -825,6 +825,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) } else data->recout.x = 0; + if (stream->src.x > surf_clip.x) + surf_clip.width -= stream->src.x - surf_clip.x; data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; @@ -833,6 +835,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) if (stream->src.y < surf_clip.y) data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height / stream->src.height; + else if (stream->src.y > surf_clip.y) + surf_clip.height -= stream->src.y - surf_clip.y; data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 23/25] drm/amd/display: [FW Promotion] Release 0.0.40
From: Anthony Koo
[Header Changes]
- Add command for retrieving PSR residency
- Add command for forcing PSR static
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 221bb2d65c1c..81433c22fb51 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x26ad601d9
+#define DMUB_FW_VERSION_GIT_HASH 0x9f0af34af
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 39
+#define DMUB_FW_VERSION_REVISION 40
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -274,6 +274,7 @@ enum dmub_gpint_command {
* ARGS: Stream mask, 1 bit per active stream index.
*/
DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
+ DMUB_GPINT__PSR_RESIDENCY = 9,
};
//==
@@ -583,6 +584,7 @@ enum dmub_cmd_psr_type {
DMUB_CMD__PSR_ENABLE= 2,
DMUB_CMD__PSR_DISABLE = 3,
DMUB_CMD__PSR_SET_LEVEL = 4,
+ DMUB_CMD__PSR_FORCE_STATIC = 5,
};
enum psr_version {
@@ -643,6 +645,10 @@ struct dmub_rb_cmd_psr_set_version {
struct dmub_cmd_psr_set_version_data psr_set_version_data;
};
+struct dmub_rb_cmd_psr_force_static {
+ struct dmub_cmd_header header;
+};
+
union dmub_hw_lock_flags {
struct {
uint8_t lock_pipe : 1;
@@ -800,6 +806,7 @@ union dmub_rb_cmd {
struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
struct dmub_rb_cmd_psr_enable psr_enable;
struct dmub_rb_cmd_psr_set_level psr_set_level;
+ struct dmub_rb_cmd_psr_force_static psr_force_static;
struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
struct dmub_rb_cmd_mall mall;
struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
--
2.17.1
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[PATCH 24/25] drm/amd/display: 3.2.110
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 87bc10279349..e6b92683dc5b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.109" +#define DC_VER "3.2.110" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/25] drm/amd/display: Update panel register
From: Chris Park
[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.
[How]
Implement same register space to future
resource files.
Signed-off-by: Chris Park
Reviewed-by: Joshua Aberback
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index c4ffed95d35e..2345f12ceab3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -967,7 +967,7 @@ static const struct encoder_feature_support
link_enc_feature = {
[id] = {\
LE_DCN3_REG_LIST(id), \
UNIPHY_DCN2_REG_LIST(phyid), \
- DPCS_DCN2_REG_LIST(id), \
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
}
static const struct dcn10_link_enc_registers link_enc_regs[] = {
--
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[PATCH 03/25] drm/amd/display: only check available pipe to disable vbios mode.
From: Yongqiang Sun
[Why & How]
1. only need to check first ODM pipe.
2. Only need to check eDP which is on.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1fa4a50e0a44..18154eea09f8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -861,12 +861,16 @@ static void disable_vbios_mode_if_required(
if (stream == NULL)
continue;
+ // only looking for first odm pipe
+ if (pipe->prev_odm_pipe)
+ continue;
+
if (stream->link->local_sink &&
stream->link->local_sink->sink_signal ==
SIGNAL_TYPE_EDP) {
link = stream->link;
}
- if (link != NULL) {
+ if (link != NULL &&
link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
unsigned int enc_inst, tg_inst = 0;
unsigned int pix_clk_100hz;
--
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[PATCH 02/25] drm/amd/display: Add MPC memory shutdown support for DCN3
From: Jacky Liao
[Why]
The MPC memory blocks in DCN3 should be powered down completely when
they are not in use. This will reduce power consumption.
[How]
This commits changes behaviour for dcn3 and does the following:
1. Write to MPC_RMU_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to
automatically shut down memory when not in use
2. mpc3_power_on_shaper_3dlut and mpc3_power_on_ogam_lut are called
to disable force power on when configuration finishes
3. Added a debug option to allow this behaviour to be turned off
Signed-off-by: Jacky Liao
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 56 ++-
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 9 +++
3 files changed, 63 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index b7f53908ebea..c74be6dafafc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -506,6 +506,7 @@ struct dc_debug_options {
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
bool force_ignore_link_settings;
+ bool enable_mpc_mem_powerdown: 1;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 8fadd61a55ec..1671688557f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -143,8 +143,16 @@ static void mpc3_power_on_ogam_lut(
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
- MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+ if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ // Force power on
+ REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS,
power_on == true ? 1:0);
+ // Wait for confirmation when powering on
+ if (power_on)
+ REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id],
MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10);
+ } else {
+ REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
+ MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0 :
1);
+ }
}
static void mpc3_configure_ogam_lut(
@@ -360,6 +368,9 @@ void mpc3_set_output_gamma(
/*we need to program 2 fields here as apposed to 1*/
REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],
MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1);
+
+ if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)
+ mpc3_power_on_ogam_lut(mpc, mpcc_id, false);
}
void mpc3_set_denorm(
@@ -801,16 +812,28 @@ static void mpc3_power_on_shaper_3dlut(
uint32_t power_status_shaper = 2;
uint32_t power_status_3dlut = 2;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+ int max_retries = 10;
if (rmu_idx == 0) {
REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,
MPC_RMU0_MEM_PWR_DIS, power_on == true ? 1:0);
+ /* wait for memory to fully power up */
+ if (power_on && mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+ }
+
/*read status is not mandatory, it is just for debugging*/
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE,
_status_shaper);
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE,
_status_3dlut);
} else if (rmu_idx == 1) {
REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,
MPC_RMU1_MEM_PWR_DIS, power_on == true ? 1:0);
+ if (power_on && mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+ }
+
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE,
_status_shaper);
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE,
_status_3dlut);
}
@@ -838,6 +861,10 @@ bool mpc3_program_shaper(
REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, 0);
return false;
}
+
+ if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)
+ mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);
+
current_mode = mpc3_get_shaper_current(mpc, rmu_idx);
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
@@ -1196,6 +1223,9 @@ bool mpc3_program_3dlut(
[PATCH 15/25] drm/amd/display: Reset flip_immediate to topmost plane
From: Alvin Lee
[Why]
When checking if we want to disable GSL or not,
we should reset flip_immediate to be the flip type
of the topmost plane before looping through the
other planes.
[How]
Set flip_immediate to be the flip type of the topmost
plane before looping through the other planes.
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 3b26396cbc5c..a195dfb718dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1204,6 +1204,9 @@ void dcn20_pipe_control_lock(
(!flip_immediate && pipe->stream_res.gsl_group > 0))
dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
+ if (pipe->plane_state != NULL)
+ flip_immediate = pipe->plane_state->flip_immediate;
+
temp_pipe = pipe->bottom_pipe;
while (flip_immediate && temp_pipe) {
if (temp_pipe->plane_state != NULL)
--
2.17.1
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[PATCH 12/25] drm/amd/display: Add OPTC memory low power support
From: Jacky Liao
[Why]
The OPTC memory blocks should be powered down when they are not in use.
This will reduce power consumption.
[How]
1. Set ODM_MEM_UNASSIGNED_PWR_MODE to shutdown memory when unassigned
2. Set ODM_MEM_VBLANK_PWR_MODE to light sleep mode when in vblank
3. Added a debug option to allow this behaviour to be turned off
4. Restructured debug options to use a bitfield in a way that's more clear
Signed-off-by: Jacky Liao
Reviewed-by: Eric Yang
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h| 10 +-
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12 ++--
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 14 +++---
4 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 273963e8e61a..87bc10279349 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -414,6 +414,14 @@ struct dc_bw_validation_profile {
} \
}
+union mem_low_power_enable_options {
+ struct {
+ bool mpc: 1;
+ bool optc: 1;
+ } bits;
+ uint32_t u32All;
+};
+
struct dc_debug_options {
enum visual_confirm visual_confirm;
bool sanity_checks;
@@ -506,7 +514,7 @@ struct dc_debug_options {
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
bool force_ignore_link_settings;
- bool enable_mpc_mem_powerdown: 1;
+ union mem_low_power_enable_options enable_mem_low_power;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index b77e22bf6aec..a8103c762c08 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -607,6 +607,10 @@ struct dce_hwseq_registers {
uint32_t MC_VM_XGMI_LFB_CNTL;
uint32_t AZALIA_AUDIO_DTO;
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+ #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ uint32_t HPO_TOP_CLOCK_CONTROL;
+ uint32_t ODM_MEM_PWR_CTRL3;
+ #endif
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -845,7 +849,9 @@ struct dce_hwseq_registers {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
- HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
@@ -1059,7 +1065,9 @@ struct dce_hwseq_registers {
type D2VGA_MODE_ENABLE; \
type D3VGA_MODE_ENABLE; \
type D4VGA_MODE_ENABLE; \
- type AZALIA_AUDIO_DTO_MODULE;
+ type AZALIA_AUDIO_DTO_MODULE; \
+ type ODM_MEM_UNASSIGNED_PWR_MODE; \
+ type ODM_MEM_VBLANK_PWR_MODE;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_DCN3_REG_FIELD_LIST(type) \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 3699c9a2789c..53b892f16da4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -462,6 +462,12 @@ void dcn30_init_hw(struct dc *dc)
hws->funcs.disable_vga(dc->hwseq);
}
+ // Set default OPTC memory power states
+ if (dc->debug.enable_mem_low_power.bits.optc) {
+ // Shutdown when unassigned and light sleep in VBLANK
+ REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3,
ODM_MEM_VBLANK_PWR_MODE, 1);
+ }
+
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 1671688557f4..d7d053fc6e91 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -143,7 +143,7 @@ static void mpc3_power_on_ogam_lut(
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
// Force power on
REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS,
power_on == true ? 1:0);
// Wait for confirmation when powering on
@@ -369,7 +369,7 @@ void mpc3_set_output_gamma(
REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],
[PATCH 21/25] drm/amd/display: set hdcp1 wa re-auth delay to 200ms
From: Jake Wang
[Why]
Fail and restart timing for HDCP1 retry occurs too quickly.
This would cause some MST monitors to show black screen.
[How]
Adjusted timing of fail and restart to 200ms.
Signed-off-by: Jake Wang
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
index f3711914364e..24ab95b093f7 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
@@ -231,7 +231,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct
mod_hdcp *hdcp,
fail_and_restart_in_ms(0, , output);
break;
} else if (conn->hdcp1_retry_count <
conn->link.adjust.hdcp1.min_auth_retries_wa) {
- fail_and_restart_in_ms(0, , output);
+ fail_and_restart_in_ms(200, , output);
break;
}
if (conn->is_repeater) {
--
2.17.1
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[PATCH 17/25] drm/amd/display: Do not warn NULL dc_sink if forcing connector
From: Victor Lu
[why]
There is a DRM_ERROR when the dc_sink is NULL and
there should not be this warning when the connector
is forced.
[how]
Do not warn if dc_sink is NULL if the connector
is forced.
Signed-off-by: Victor Lu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 345eb2130869..6b3ae523e62e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5485,7 +5485,8 @@ enum drm_mode_status
amdgpu_dm_connector_mode_valid(struct drm_connector *connec
dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
- if (dc_sink == NULL) {
+ if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
+ aconnector->base.force != DRM_FORCE_ON) {
DRM_ERROR("dc_sink is NULL!\n");
goto fail;
}
--
2.17.1
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[PATCH 08/25] drm/amd/display: Blank HUBP during pixel data blank for DCN30
From: Joshua Aberback
[Why]
There are some timings for which we support p-state
switching in active, but not in blank. There was a
previous issue where a timing that had active-only
support would hang a p-state request when we were in
an extended blanking period. The workaround for that
issue was to block active-only p-state switching,
but that resulted in a lack of p-state support for
some common timings such as 1440p60. We want to fix
that issue properly by un-blocking p-state requests
while the display is blanked, so that we can re-enable
active-only p-state switching.
[How]
- new version of blank_pixel_data for DCN30
- call hubp->set_blank from dcn30_blank_pixel_data
- blank every hubp in the mpcc tree, and odm tree
- on blank enable, wait until the next frame before blanking HUBP
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 83 +++
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h| 2 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +-
.../dc/dml/dcn30/display_mode_vba_30.c| 2 +-
4 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index f3ae208850b0..3699c9a2789c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -794,3 +794,86 @@ void dcn30_hardware_release(struct dc *dc)
dc->res_pool->hubbub->funcs->force_pstate_change_control(
dc->res_pool->hubbub, true, true);
}
+
+void dcn30_blank_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool
blank)
+{
+ struct tg_color black_color = {0};
+ struct stream_resource *stream_res = _ctx->stream_res;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ enum dc_color_space color_space = stream->output_color_space;
+ enum controller_dp_test_pattern test_pattern =
CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
+ enum controller_dp_color_space test_pattern_color_space =
CONTROLLER_DP_COLOR_SPACE_UDEFINED;
+ struct pipe_ctx *odm_pipe;
+ struct pipe_ctx *mpcc_pipe;
+ int odm_cnt = 1;
+
+ int width = stream->timing.h_addressable + stream->timing.h_border_left
+ stream->timing.h_border_right;
+ int height = stream->timing.v_addressable +
stream->timing.v_border_bottom + stream->timing.v_border_top;
+
+ if (stream->link->test_pattern_enabled)
+ return;
+
+ /* get opp dpg blank color */
+ color_space_to_black_color(dc, color_space, _color);
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe =
odm_pipe->next_odm_pipe)
+ odm_cnt++;
+
+ width = width / odm_cnt;
+
+ if (blank) {
+ dc->hwss.set_abm_immediate_disable(pipe_ctx);
+
+ if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
+ test_pattern_color_space =
CONTROLLER_DP_COLOR_SPACE_RGB;
+ }
+ } else {
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
+ }
+
+ stream_res->opp->funcs->opp_set_disp_pattern_generator(
+ stream_res->opp,
+ test_pattern,
+ test_pattern_color_space,
+ stream->timing.display_color_depth,
+ _color,
+ width,
+ height,
+ 0);
+
+ /* wait for the next frame when enabling DPG */
+ if (blank && stream_res->tg->funcs->is_tg_enabled(stream_res->tg))
+
dc->hwseq->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
+
+ /* Blank HUBP to allow p-state during blank on all timings */
+ pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp,
blank);
+ for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
+
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, blank);
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe =
odm_pipe->next_odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
+ odm_pipe->stream_res.opp,
+ dc->debug.visual_confirm !=
VISUAL_CONFIRM_DISABLE && blank ?
+
CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
+ test_pattern_color_space,
+ stream->timing.display_color_depth,
+ _col
[PATCH 20/25] drm/amd/display: Revert HUBP blank behaviour for now
From: Joshua Aberback
[Why]
Commit "Blank HUBP during pixel data blank for DCN30 v2"
modifies HW behaviour during blank, which might have OS
dependencies. We need to assess the impact on amdgpu_dm
and only re-enable HUBP blanking when all necessary
changes are understood.
[How]
- revert functional changes
- leave architectural changes intact
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 27 ++-
.../dc/dml/dcn30/display_mode_vba_30.c| 2 +-
2 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 6b6e92e261ef..a57e83428a77 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -809,29 +809,6 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
const struct tg_color *solid_color,
int width, int height, int offset)
{
- struct stream_resource *stream_res = _ctx->stream_res;
- struct pipe_ctx *mpcc_pipe;
-
- if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
- /* turning on DPG */
-
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp,
test_pattern, color_space,
- color_depth, solid_color, width, height, 0);
-
- /* wait for the next frame when enabling DPG */
- if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg))
-
dc->hwseq->funcs.wait_for_blank_complete(stream_res->opp);
-
- /* Blank HUBP to allow p-state during blank on all timings */
-
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
- for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
-
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
- } else {
- /* turning off DPG */
-
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
- for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
-
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
-
-
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp,
test_pattern, color_space,
- color_depth, solid_color, width, height, 0);
- }
+
pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp,
test_pattern,
+ color_space, color_depth, solid_color, width, height,
0);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 50b7d011705d..9e0ae18e71fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5558,7 +5558,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
}
}
- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0 && PrefetchMode ==
0) {
*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
} else if (((mode_lib->vba.SynchronizedVBlank == true ||
mode_lib->vba.TotalNumberOfActiveOTG == 1 ||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode ==
0)) {
*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
--
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[PATCH 04/25] drm/amd/display: Force prefetch mode to 0
From: Isabel Zhang
[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.
[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.
Signed-off-by: Isabel Zhang
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 70a18271bd2d..5ae3419682c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -301,7 +301,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.xfc_bus_transport_time_us = 4,
.xfc_xbuf_latency_tolerance_us = 4,
.use_urgent_burst_bw = 1,
- .num_states = 8
+ .num_states = 8,
+ .allow_dram_self_refresh_or_dram_clock_change_in_vblank
+ = dm_allow_self_refresh_and_mclk_switch
};
#ifndef MAX
--
2.17.1
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[PATCH 06/25] drm/amd/display: [FW Promotion] Release 0.0.39
From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a4c3f078887d..221bb2d65c1c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -36,10 +36,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x8aafc9acc +#define DMUB_FW_VERSION_GIT_HASH 0x26ad601d9 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 38 +#define DMUB_FW_VERSION_REVISION 39 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/25] drm/amd/display: stop top_mgr when type change to non-MST during s3
From: Lewis Huang
[Why]
Driver keeps the invalid information cause report the
incorrect monitor which save in remote sink to OS
[How]
When connector type change from MST to non-MST,
stop the topology manager.
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 5652a072d9be..4dfa70c0301b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -854,6 +854,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
struct dpcd_caps prev_dpcd_caps;
bool same_dpcd = true;
enum dc_connection_type new_connection_type = dc_connection_none;
+ enum dc_connection_type pre_connection_type = dc_connection_none;
bool perform_dp_seamless_boot = false;
const uint32_t post_oui_delay = 30; // 30ms
@@ -889,6 +890,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
link_disconnect_sink(link);
if (new_connection_type != dc_connection_none) {
+ pre_connection_type = link->type;
link->type = new_connection_type;
link->link_state_valid = false;
@@ -962,6 +964,12 @@ static bool dc_link_detect_helper(struct dc_link *link,
return true;
}
+ // link switch from MST to non-MST stop topology manager
+ if (pre_connection_type == dc_connection_mst_branch &&
+ link->type != dc_connection_mst_branch) {
+ dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
+ }
+
if (link->type == dc_connection_mst_branch) {
LINK_INFO("link=%d, mst branch is now
Connected\n",
link->link_index);
--
2.17.1
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[PATCH 01/25] drm/amd/display: Fix compilation error
From: "Tao.Huang"
[Why]
The C standard does not specify whether an enum is signed or unsigned.
In the function prototype, one of the argument is defined as an enum
but its declaration was unit32_t. Fix this by changing the function
argument to enum in the declaration.
Signed-off-by: Tao.Huang
Signed-off-by: Florin Iucha
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 6 +++---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 7f6bedbc1ff1..81bf2ecc2831 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -585,7 +585,7 @@ void dpp3_cm_set_gamut_remap(
const struct dpp_grph_csc_adjustment *adjust);
void dpp3_set_pre_degam(struct dpp *dpp_base,
- uint32_t degamma_lut_selection);
+ enum dc_transfer_func_predefined tr);
void dpp3_set_cursor_attributes(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 4da21966ddce..c6a1cd80aeae 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -51,7 +51,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum
bits_per_comp bpc,
const struct qp_entry *table = 0L;
// alias enum
- enum { min = MM_MIN, max = MM_MAX };
+ enum { min = DAL_MM_MIN, max = DAL_MM_MAX };
switch (sel) {
TABLE_CASE(444, 8, max);
TABLE_CASE(444, 8, min);
@@ -233,8 +233,8 @@ static void _do_calc_rc_params(struct rc_params *rc, enum
colour_mode cm,
rc->flatness_max_qp = ((bpc == BPC_8) ? (12) : ((bpc == BPC_10) ?
(16) : (20))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
rc->flatness_det_thresh = 2 << (bpc - 8);
- get_qp_set(rc->qp_min, cm, bpc, MM_MIN, bpp);
- get_qp_set(rc->qp_max, cm, bpc, MM_MAX, bpp);
+ get_qp_set(rc->qp_min, cm, bpc, DAL_MM_MIN, bpp);
+ get_qp_set(rc->qp_max, cm, bpc, DAL_MM_MAX, bpp);
if (cm == CM_444 && minor_version == 1) {
for (i = 0; i < QP_SET_SIZE; ++i) {
rc->qp_min[i] = rc->qp_min[i] > 0 ? rc->qp_min[i] - 1 :
0;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
index 21723fa6561e..8123827840c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
@@ -66,8 +66,8 @@ enum bits_per_comp {
};
enum max_min {
- MM_MIN = 0,
- MM_MAX = 1
+ DAL_MM_MIN = 0,
+ DAL_MM_MAX = 1
};
struct qp_entry {
--
2.17.1
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[PATCH 10/25] drm/amd/display: fail instead of div by zero/bugcheck
From: Ashley Thomas
[why]
If pbn_per_slot is 0, fail instead of dividing by zero and
bugchecking.
[how]
Check for zero divisor before division operation.
Signed-off-by: Ashley Thomas
Reviewed-by: Wyatt Wood
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 ++
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 4
drivers/gpu/drm/amd/display/dc/inc/core_status.h | 1 +
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 7977e2839065..21be2a684393 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -420,6 +420,8 @@ char *dc_status_to_str(enum dc_status status)
return "Fail clk below required CFG (hard_min in PPLIB)";
case DC_NOT_SUPPORTED:
return "The operation is not supported.";
+ case DC_UNSUPPORTED_VALUE:
+ return "The value specified is not supported.";
case DC_ERROR_UNEXPECTED:
return "Unexpected error";
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 4dfa70c0301b..eafefcf3696c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2951,6 +2951,10 @@ enum dc_status dc_link_allocate_mst_payload(struct
pipe_ctx *pipe_ctx)
/* slot X.Y for only current stream */
pbn_per_slot = get_pbn_per_slot(stream);
+ if (pbn_per_slot.value == 0) {
+ DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot
continue, returning DC_UNSUPPORTED_VALUE.\n");
+ return DC_UNSUPPORTED_VALUE;
+ }
pbn = get_pbn_from_timing(pipe_ctx);
avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 714593a15590..d34b0b0eea65 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -51,6 +51,7 @@ enum dc_status {
DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
DC_NOT_SUPPORTED = 24,
+ DC_UNSUPPORTED_VALUE = 25,
DC_ERROR_UNEXPECTED = -1
};
--
2.17.1
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[PATCH 16/25] drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2
From: Joshua Aberback
[Why]
Prior commit "Blank HUBP during pixel data blank for DCN30"
missed the call to set_disp_pattern_generator from
set_crtc_test_pattern, which re-exposed the issue for which
we initially blocked active-only p-state switching.
[How]
- remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version
- new hwss funciton set_disp_pattern_generator
- dcn20 version just calls opp_set_disp_pattern_generator
- dcn30 version implements the HUBP blank
Signed-off-by: Joshua Aberback
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 62 ++--
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 20 +++-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 9 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 +
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 96 +--
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h| 8 +-
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 3 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 ++
9 files changed, 100 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2114c280895a..9d1c5e1d06c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3848,7 +3848,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
controller_test_pattern, color_depth);
- else if (opp->funcs->opp_set_disp_pattern_generator) {
+ else if (link->dc->hwss.set_disp_pattern_generator) {
struct pipe_ctx *odm_pipe;
enum controller_dp_color_space controller_color_space;
int opp_cnt = 1;
@@ -3878,26 +3878,29 @@ static void set_crtc_test_pattern(struct dc_link *link,
dpg_width = width / opp_cnt;
offset = dpg_width;
- opp->funcs->opp_set_disp_pattern_generator(opp,
- controller_test_pattern,
- controller_color_space,
- color_depth,
- NULL,
- dpg_width,
- height,
- 0);
-
- for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe;
odm_pipe = odm_pipe->next_odm_pipe) {
- struct output_pixel_processor *odm_opp =
odm_pipe->stream_res.opp;
-
odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, );
-
odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ link->dc->hwss.set_disp_pattern_generator(link->dc,
+ pipe_ctx,
controller_test_pattern,
controller_color_space,
color_depth,
NULL,
dpg_width,
height,
- offset);
+ 0);
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe;
odm_pipe = odm_pipe->next_odm_pipe) {
+ struct output_pixel_processor *odm_opp =
odm_pipe->stream_res.opp;
+
+
odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, );
+
link->dc->hwss.set_disp_pattern_generator(link->dc,
+ odm_pipe,
+ controller_test_pattern,
+ controller_color_space,
+ color_depth,
+ NULL,
+ dpg_width,
+ height,
+ offset);
offset += offset;
}
}
@@ -3913,7 +3916,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
color_depth);
- else if (opp->funcs->opp_set_disp_pattern_g
[PATCH 00/25] DC Patches Nov 2nd, 2020
This DC patchset brings improvements in multiple areas. In summary, we have: * DC 3.2.110 * Firmware release 0.0.40 * Enable CRC calculation on specific frame region * Bug fixes on GSL, recout calculation, missing pflip irq and more. --- Alvin Lee (2): drm/amd/display: Keep GSL for full updates with planes that flip VSYNC drm/amd/display: Reset flip_immediate to topmost plane Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.39 drm/amd/display: [FW Promotion] Release 0.0.40 Aric Cyr (2): drm/amd/display: 3.2.109 drm/amd/display: 3.2.110 Ashley Thomas (1): drm/amd/display: fail instead of div by zero/bugcheck Bhawanpreet Lakha (1): drm/amd/display: Add missing pflip irq Chris Park (1): drm/amd/display: Update panel register Dale Zhao (1): drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP Dmytro Laktyushkin (1): drm/amd/display: fix recout calculation for left side clip Eryk Brol (1): drm/amd/display: Update connector on DSC property change Hugo Hu (1): drm/amd/display: correct eDP T9 delay Isabel Zhang (1): drm/amd/display: Force prefetch mode to 0 Jacky Liao (2): drm/amd/display: Add MPC memory shutdown support for DCN3 drm/amd/display: Add OPTC memory low power support Jake Wang (1): drm/amd/display: set hdcp1 wa re-auth delay to 200ms Joshua Aberback (3): drm/amd/display: Blank HUBP during pixel data blank for DCN30 drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2 drm/amd/display: Revert HUBP blank behaviour for now Lewis Huang (1): drm/amd/display: stop top_mgr when type change to non-MST during s3 Tao.Huang (1): drm/amd/display: Fix compilation error Victor Lu (1): drm/amd/display: Do not warn NULL dc_sink if forcing connector Wayne Lin (1): drm/amd/display: Calculate CRC on specific frame region Yongqiang Sun (1): drm/amd/display: only check available pipe to disable vbios mode. .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 124 ++ drivers/gpu/drm/amd/display/dc/core/dc.c | 21 ++- .../gpu/drm/amd/display/dc/core/dc_debug.c| 2 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12 ++ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 72 +- .../drm/amd/display/dc/core/dc_link_hwss.c| 13 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 4 + drivers/gpu/drm/amd/display/dc/dc.h | 11 +- drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 12 +- .../display/dc/dce110/dce110_hw_sequencer.c | 16 +-- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 42 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 9 ++ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 2 +- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 18 +++ .../drm/amd/display/dc/dcn30/dcn30_hwseq.h| 8 ++ .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 56 +++- .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 9 ++ .../amd/display/dc/dcn302/dcn302_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 6 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 4 +- .../gpu/drm/amd/display/dc/inc/core_status.h | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 ++ .../gpu/drm/amd/display/dc/inc/link_hwss.h| 1 + .../display/dc/irq/dcn30/irq_service_dcn30.c | 4 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +- .../display/modules/hdcp/hdcp1_transition.c | 2 +- 34 files changed, 418 insertions(+), 72 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 22/25] drm/amd/display: Add missing pflip irq
From: Bhawanpreet Lakha
If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
index 49689f71f4f1..0effbb2bd74a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
@@ -306,8 +306,8 @@ irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
pflip_int_entry(1),
pflip_int_entry(2),
pflip_int_entry(3),
- [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
- [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+ pflip_int_entry(4),
+ pflip_int_entry(5),
[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
gpio_pad_int_entry(0),
gpio_pad_int_entry(1),
--
2.17.1
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[PATCH 19/25] drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP
From: Dale Zhao
[Why]
Customer make a request to add this WA by driver.
Some MUX chips will power down with eDP 1.4 panel and
lose previous supported link rates(DPCD 0x010) in
customer's hybrid-GPU designs. As a result, during sleep
resuming and screen turns on from idle, link training
will be performed incorrectly and eDP will flicker or
black screen. These MUX chips need source to read DPCD
0x010 again during LKT so that it can restore supported
link rates of panel.
For driver side, supported link rate set is fetched when
link detection, no need to update but just read again
as WA.
[How]
Read DPCD 0x010 again during link training for eDP 1.4.
Signed-off-by: Dale Zhao
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9d1c5e1d06c0..54ac3de4e8e0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -183,6 +183,16 @@ static void dpcd_set_link_settings(
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
lt_settings->link_settings.use_link_rate_set == true) {
rate = 0;
+ /* WA for some MUX chips that will power down with eDP and lose
supported
+* link rate set for eDP 1.4. Source reads DPCD 0x010 again to
ensure
+* MUX chip gets link rate set back before link training.
+*/
+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
+ uint8_t supported_link_rates[16];
+
+ core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
+ supported_link_rates,
sizeof(supported_link_rates));
+ }
core_link_write_dpcd(link, DP_LINK_BW_SET, , 1);
core_link_write_dpcd(link, DP_LINK_RATE_SET,
_settings->link_settings.link_rate_set, 1);
--
2.17.1
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[PATCH 5/9] drm/amd/display: Fix LFC multiplier changing erratically
From: Anthony Koo
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.
2. We do not handle unsigned integer subtraction correctly and it underflows
to a really large value, which causes some logic errors.
[How]
1. Fix logic to calculate 'within range' using last_render_time_in_us
2. Split out delta_from_mid_point_delta_in_us calculation to ensure
we don't underflow and wrap around
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../amd/display/modules/freesync/freesync.c | 36 +++
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 81820f3d6b3b..d988533d4af5 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -324,22 +324,44 @@ static void apply_below_the_range(struct core_freesync
*core_freesync,
/* Choose number of frames to insert based on how close it
* can get to the mid point of the variable range.
+* - Delta for CEIL: delta_from_mid_point_in_us_1
+* - Delta for FLOOR: delta_from_mid_point_in_us_2
*/
- if ((frame_time_in_us / mid_point_frames_ceil) >
in_out_vrr->min_duration_in_us &&
- (delta_from_mid_point_in_us_1 <
delta_from_mid_point_in_us_2 ||
- mid_point_frames_floor < 2)) {
+ if ((last_render_time_in_us / mid_point_frames_ceil) <
in_out_vrr->min_duration_in_us) {
+ /* Check for out of range.
+* If using CEIL produces a value that is out of range,
+* then we are forced to use FLOOR.
+*/
+ frames_to_insert = mid_point_frames_floor;
+ } else if (mid_point_frames_floor < 2) {
+ /* Check if FLOOR would result in non-LFC. In this case
+* choose to use CEIL
+*/
+ frames_to_insert = mid_point_frames_ceil;
+ } else if (delta_from_mid_point_in_us_1 <
delta_from_mid_point_in_us_2) {
+ /* If choosing CEIL results in a frame duration that is
+* closer to the mid point of the range.
+* Choose CEIL
+*/
frames_to_insert = mid_point_frames_ceil;
- delta_from_mid_point_delta_in_us =
delta_from_mid_point_in_us_2 -
- delta_from_mid_point_in_us_1;
} else {
+ /* If choosing FLOOR results in a frame duration that is
+* closer to the mid point of the range.
+* Choose FLOOR
+*/
frames_to_insert = mid_point_frames_floor;
- delta_from_mid_point_delta_in_us =
delta_from_mid_point_in_us_1 -
- delta_from_mid_point_in_us_2;
}
/* Prefer current frame multiplier when BTR is enabled unless
it drifts
* too far from the midpoint
*/
+ if (delta_from_mid_point_in_us_1 <
delta_from_mid_point_in_us_2) {
+ delta_from_mid_point_delta_in_us =
delta_from_mid_point_in_us_2 -
+ delta_from_mid_point_in_us_1;
+ } else {
+ delta_from_mid_point_delta_in_us =
delta_from_mid_point_in_us_1 -
+ delta_from_mid_point_in_us_2;
+ }
if (in_out_vrr->btr.frames_to_insert != 0 &&
delta_from_mid_point_delta_in_us <
BTR_DRIFT_MARGIN) {
if (((last_render_time_in_us /
in_out_vrr->btr.frames_to_insert) <
--
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[PATCH 3/9] drm/amd/display: Revert regression
From: Alvin Lee
[Why]
Caused pipe split regression
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 --
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 114 --
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 7 --
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 2 -
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 2 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 -
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 -
7 files changed, 141 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ebbb8182228d..5aa3b89471c3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2300,7 +2300,6 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
- bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2331,15 +2330,6 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
- if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock &&
- dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
- dc->hwss.interdependent_update_lock(dc, context, true);
- mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
- dc->hwss.interdependent_update_lock(dc, context, false);
- if (mpcc_disconnected)
- dc->hwss.wait_for_pending_cleared(dc, context);
- }
-
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 73eb4e76a0b1..66180b4332f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1624,120 +1624,6 @@ static void dcn20_program_pipe(
}
}
-bool dcn20_disconnect_pipes(
- struct dc *dc,
- struct dc_state *context)
-{
- int i;
- struct dce_hwseq *hws = dc->hwseq;
- bool mpcc_disconnected = false;
- DC_LOGGER_INIT(dc->ctx->logger);
-
- /* Set pipe update flags and lock pipes */
- for (i = 0; i < dc->res_pool->pipe_count; i++)
-
dcn20_detect_pipe_changes(>current_state->res_ctx.pipe_ctx[i],
- >res_ctx.pipe_ctx[i]);
-
- if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
- /* OTG blank before disabling all front ends */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if
(context->res_ctx.pipe_ctx[i].update_flags.bits.disable
- &&
!context->res_ctx.pipe_ctx[i].top_pipe
- &&
!context->res_ctx.pipe_ctx[i].prev_odm_pipe
- && context->res_ctx.pipe_ctx[i].stream)
{
- hws->funcs.blank_pixel_data(dc,
>res_ctx.pipe_ctx[i], true);
- }
- }
-
- /* Disconnect mpcc */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if
(context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {
- hws->funcs.plane_atomic_disconnect(dc,
>current_state->res_ctx.pipe_ctx[i]);
- DC_LOG_DC("Reset mpcc for pipe %d\n",
dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
- mpcc_disconnected = true;
- }
- }
- }
-
- if (mpcc_disconnected) {
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe =
>current_state->res_ctx.pipe_ctx[i];
- struct dc_plane_state *plane_state =
pipe_ctx->plane_state;
- struct hubp *hubp = pipe_ctx->plane_res.hubp;
-
- if (!pipe_ctx || !plane_state ||
!pipe_ctx->stream)
- continue;
-
- // Only update scaler and viewport here if we lose a
pipe split.
-
[PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend
From: Stylon Wang [Why] Resuming from suspend, CEA blocks from EDID are not parsed and no video modes can support YUV420. When this happens, output bpc cannot go over 8-bit with 4K modes on HDMI. [How] In amdgpu_dm_update_connector_after_detect(), drm_add_edid_modes() is called after drm_connector_update_edid_property() to fully parse EDID and update display info. Cc: sta...@vger.kernel.org Signed-off-by: Stylon Wang Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 53bf8f60d30c..bfb06c168fba 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2202,6 +2202,7 @@ void amdgpu_dm_update_connector_after_detect( drm_connector_update_edid_property(connector, aconnector->edid); + drm_add_edid_modes(connector, aconnector->edid); if (aconnector->dc_link->aux_mode) drm_dp_cec_set_edid(>dm_dp_aux.aux, -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session
From: Jaehyun Chung [Why] Stream disable sequence incorretly destroys HDCP session while stream is not blanked and while audio is not muted. This sequence causes a flash of corruption during mode change and an audio click. [How] Change sequence to blank stream before destroying HDCP session. Audio will also be muted by blanking the stream. Cc: sta...@vger.kernel.org Signed-off-by: Jaehyun Chung Reviewed-by: Alvin Lee Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 4bd6e03a7ef3..117d8aaf2a9b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3286,12 +3286,11 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) core_link_set_avmute(pipe_ctx, true); } + dc->hwss.blank_stream(pipe_ctx); #if defined(CONFIG_DRM_AMD_DC_HDCP) update_psp_stream_config(pipe_ctx, true); #endif - dc->hwss.blank_stream(pipe_ctx); - if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/9] drm/amd/display: mpcc black color should not be impacted by pixel encoding format
From: Xiaodong Yan [Why] The format in MPCC should be 444 [How] do not modify the mpcc black color according to pixel encoding format Signed-off-by: Xiaodong Yan Reviewed-by: Eric Yang Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index a643927e272b..57cd52789606 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2368,14 +2368,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) _cfg.black_color); } - /* -* The way 420 is packed, 2 channels carry Y component, 1 channel -* alternate between Cb and Cr, so both channels need the pixel -* value for Y -*/ - if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) - blnd_cfg.black_color.color_r_cr = blnd_cfg.black_color.color_g_y; - if (per_pixel_alpha) blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; else -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 7/9] drm/amd/display: Disconnect pipe separetely when disable pipe split
From: Alvin Lee
[Why]
When changing pixel formats for HDR (e.g. ARGB -> FP16)
there are configurations that change from 2 pipes to 1 pipe.
In these cases, it seems that disconnecting MPCC and doing
a surface update at the same time(after unlocking) causes
some registers to be updated slightly faster than others
after unlocking (e.g. if the pixel format is updated to FP16
before the new surface address is programmed, we get
corruption on the screen because the pixel formats aren't
matching). We separate disconnecting MPCC from the rest
of the pipe programming sequence to prevent this.
[How]
Move MPCC disconnect into separate operation than the
rest of the pipe programming.
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 146 ++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 6 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 2 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 2 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 2 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +
8 files changed, 174 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5aa3b89471c3..ebbb8182228d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2300,6 +2300,7 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
+ bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2330,6 +2331,15 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
+ if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock &&
+ dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
+ dc->hwss.interdependent_update_lock(dc, context, true);
+ mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
+ dc->hwss.interdependent_update_lock(dc, context, false);
+ if (mpcc_disconnected)
+ dc->hwss.wait_for_pending_cleared(dc, context);
+ }
+
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 57cd52789606..95e9d05f884b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2752,6 +2752,152 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
+bool dcn10_disconnect_pipes(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ bool found_stream = false;
+ int i, j;
+ struct dce_hwseq *hws = dc->hwseq;
+ struct dc_state *old_ctx = dc->current_state;
+ bool mpcc_disconnected = false;
+ struct pipe_ctx *old_pipe;
+ struct pipe_ctx *new_pipe;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ /* Set pipe update flags and lock pipes */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ old_pipe = >current_state->res_ctx.pipe_ctx[i];
+ new_pipe = >res_ctx.pipe_ctx[i];
+ new_pipe->update_flags.raw = 0;
+
+ if (!old_pipe->plane_state && !new_pipe->plane_state)
+ continue;
+
+ if (old_pipe->plane_state && !new_pipe->plane_state)
+ new_pipe->update_flags.bits.disable = 1;
+
+ /* Check for scl update */
+ if (memcmp(_pipe->plane_res.scl_data,
_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
+ new_pipe->update_flags.bits.scaler = 1;
+
+ /* Check for vp update */
+ if (memcmp(_pipe->plane_res.scl_data.viewport,
_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
+ ||
memcmp(_pipe->plane_res.scl_data.viewport_c,
+
_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
+ new_pipe->update_flags.bits.viewport = 1;
+
+ }
+
+ if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ /* Disconnect m
[PATCH 1/9] drm/amd/display: Adjust static-ness of resource functions
From: Joshua Aberback
[Why]
Register definitions are asic-specific, so functions that use registers of
a particular asic should be static, to be exposed in asic-specific function
pointer structures.
[How]
- make register-definition-using functions static
- make some functions non-static, for future use
- remove duplicate function definition
Signed-off-by: Joshua Aberback
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 -
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 27 ++-
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 3 +++
3 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 2c1959845c29..cdd39ee9761d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -95,7 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create(
struct dc_context *ctx, uint32_t inst);
void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
-void dcn20_patch_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_st *bb);
void dcn20_cap_soc_clocks(
struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 653a571e366d..de53d26f61d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -871,7 +871,7 @@ void dcn30_dpp_destroy(struct dpp **dpp)
*dpp = NULL;
}
-struct dpp *dcn30_dpp_create(
+static struct dpp *dcn30_dpp_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -889,7 +889,8 @@ struct dpp *dcn30_dpp_create(
kfree(dpp);
return NULL;
}
-struct output_pixel_processor *dcn30_opp_create(
+
+static struct output_pixel_processor *dcn30_opp_create(
struct dc_context *ctx, uint32_t inst)
{
struct dcn20_opp *opp =
@@ -905,7 +906,7 @@ struct output_pixel_processor *dcn30_opp_create(
return >base;
}
-struct dce_aux *dcn30_aux_engine_create(
+static struct dce_aux *dcn30_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -924,6 +925,7 @@ struct dce_aux *dcn30_aux_engine_create(
return _engine->base;
}
+
#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
static const struct dce_i2c_registers i2c_hw_regs[] = {
@@ -943,7 +945,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
};
-struct dce_i2c_hw *dcn30_i2c_hw_create(
+static struct dce_i2c_hw *dcn30_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -958,6 +960,7 @@ struct dce_i2c_hw *dcn30_i2c_hw_create(
return dce_i2c_hw;
}
+
static struct mpc *dcn30_mpc_create(
struct dc_context *ctx,
int num_mpcc,
@@ -1008,7 +1011,7 @@ struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
return >base;
}
-struct timing_generator *dcn30_timing_generator_create(
+static struct timing_generator *dcn30_timing_generator_create(
struct dc_context *ctx,
uint32_t instance)
{
@@ -1042,7 +1045,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.flags.bits.IS_TPS4_CAPABLE = true
};
-struct link_encoder *dcn30_link_encoder_create(
+static struct link_encoder *dcn30_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dcn20_link_encoder *enc20 =
@@ -1063,7 +1066,7 @@ struct link_encoder *dcn30_link_encoder_create(
return >enc10.base;
}
-struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data
*init_data)
+static struct panel_cntl *dcn30_panel_cntl_create(const struct
panel_cntl_init_data *init_data)
{
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
@@ -1311,7 +1314,7 @@ static void dcn30_resource_destruct(struct
dcn30_resource_pool *pool)
dcn_dccg_destroy(>base.dccg);
}
-struct hubp *dcn30_hubp_create(
+static struct hubp *dcn30_hubp_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -1330,7 +1333,7 @@ struct hubp *dcn30_hubp_create(
return NULL;
}
-bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool
*pool)
{
int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
@@ -1355,7 +1358,7 @@ bool dcn30_dwbc_create(struct dc_context *ctx, struct
resource_pool *pool)
return true;
}
-bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+static bool
[PATCH 6/9] drm/amd/display: Switch to immediate mode for updating infopackets
From: Anthony Koo
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be erroneously sent out on
initial frame after stream is re-enabled.
[How]
Switch to using IMMEDIATE_UPDATE mode
Signed-off-by: Anthony Koo
Reviewed-by: Ashley Thomas
Acked-by: Qingqing Zhuo
---
.../amd/display/dc/dcn10/dcn10_stream_encoder.c | 16
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 14 ++
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 07b2f9399671..842abb4c475b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -121,35 +121,35 @@ void enc1_update_generic_info_packet(
switch (packet_index) {
case 0:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC0_FRAME_UPDATE, 1);
+ AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
break;
case 1:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC1_FRAME_UPDATE, 1);
+ AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
break;
case 2:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC2_FRAME_UPDATE, 1);
+ AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
break;
case 3:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC3_FRAME_UPDATE, 1);
+ AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
break;
case 4:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC4_FRAME_UPDATE, 1);
+ AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
break;
case 5:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC5_FRAME_UPDATE, 1);
+ AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
break;
case 6:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC6_FRAME_UPDATE, 1);
+ AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
break;
case 7:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC7_FRAME_UPDATE, 1);
+ AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index ed385b1477be..30eae7459d50 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -281,7 +281,14 @@ struct dcn10_stream_enc_registers {
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE,
mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE,
mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE,
mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE,
mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE,
mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE,
mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE,
mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE,
mask_sh),\
@@ -345,7 +352,14 @@ struct dcn10_stream_enc_registers {
type AFMT_GENERIC2_FRAME_UPDATE;\
type AFMT_GENERIC3_FRAME_UPDATE;\
type AFMT_GENERIC4_FRAME_UPDATE;\
+ type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC7_IMMEDIATE_UPDATE
[PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN
From: Aric Cyr [Why] Typo in backlight refactor inctroduced wrong register offset. [How] Change DCE to DCN register map for PWRSEQ_REF_DIV Cc: sta...@vger.kernel.org Signed-off-by: Aric Cyr Reviewed-by: Ashley Thomas Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h index 70ec691e14d2..99c68ca9c7e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h @@ -49,7 +49,7 @@ #define DCN_PANEL_CNTL_REG_LIST()\ DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \ DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \ - DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \ + DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \ SR(BL_PWM_CNTL), \ SR(BL_PWM_CNTL2), \ SR(BL_PWM_PERIOD_CNTL), \ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/9] DC Patches August 10th, 2020
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Fixes on LFC, pipe split, register mapping and others. * Code clean-up. Alvin Lee (2): drm/amd/display: Revert regression drm/amd/display: Disconnect pipe separetely when disable pipe split Anthony Koo (2): drm/amd/display: Fix LFC multiplier changing erratically drm/amd/display: Switch to immediate mode for updating infopackets Aric Cyr (1): drm/amd/display: Fix incorrect backlight register offset for DCN Jaehyun Chung (1): drm/amd/display: Blank stream before destroying HDCP session Joshua Aberback (1): drm/amd/display: Adjust static-ness of resource functions Stylon Wang (1): drm/amd/display: Fix EDID parsing after resume from suspend Xiaodong Yan (1): drm/amd/display: mpcc black color should not be impacted by pixel encoding format .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +- .../drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 154 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 6 + .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 2 + .../display/dc/dcn10/dcn10_stream_encoder.c | 16 +- .../display/dc/dcn10/dcn10_stream_encoder.h | 14 ++ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 114 - .../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 7 - .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 4 +- .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 - .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 4 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 4 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 27 +-- .../drm/amd/display/dc/dcn30/dcn30_resource.h | 3 + .../amd/display/modules/freesync/freesync.c | 36 +++- 17 files changed, 232 insertions(+), 166 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/1] drm/amd/display: fix compilation error on allmodconfig
when compiled with allmodconfig option, there are error messages as below: ERROR: modpost: "mod_color_is_table_init" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_get_table" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_set_table_init_state" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! To fix the issue, this commits removes CONFIG_DRM_AMD_DC_DCN guard in color/makefile. Signed-off-by: Qingqing Zhuo CC: Lewis Huang CC: Aric Cyr CC: Alexander Deucher CC: Harry Wentland CC: Nicholas Kazlauskas CC: Bhawanpreet Lakha CC: Stephen Rothwell --- drivers/gpu/drm/amd/display/modules/color/Makefile | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/color/Makefile b/drivers/gpu/drm/amd/display/modules/color/Makefile index 3ee7f27ff93b..e66c19a840c2 100644 --- a/drivers/gpu/drm/amd/display/modules/color/Makefile +++ b/drivers/gpu/drm/amd/display/modules/color/Makefile @@ -23,11 +23,7 @@ # Makefile for the color sub-module of DAL. # -MOD_COLOR = color_gamma.o - -ifdef CONFIG_DRM_AMD_DC_DCN -MOD_COLOR += color_table.o -endif +MOD_COLOR = color_gamma.o color_table.o AMD_DAL_MOD_COLOR = $(addprefix $(AMDDALPATH)/modules/color/,$(MOD_COLOR)) #$(info DAL COLOR MODULE MAKEFILE ) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/1] DC PATCH fix
An issue is reported regarding compilation errors on upstream branch. The corresponding fix has been attached below for review. Qingqing Zhuo (1): drm/amd/display: fix compilation error on allmodconfig drivers/gpu/drm/amd/display/modules/color/Makefile | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 28/28] drm/amd/display: 3.2.89
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7da41d465a34..a45b5ea98918 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.88" +#define DC_VER "3.2.89" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 22/28] drm/amd/display: Improve DisplayPort monitor interop
From: Aric Cyr
[Why]
DC is very fast at link training and stream enablement
which causes issues such as blackscreens for non-compliant
monitors.
[How]
After debugging with scaler vendors we implement the
minimum delays at the necessary locations to ensure
the monitor does not hang. Delays are generic due to
lack of IEEE OUI information on the failing displays.
Also reverts commit b9976bd920a19d509de09b6dc727fcaae60fbb32.
Signed-off-by: Aric Cyr
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
Acked-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 23 +++
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
.../display/dc/dce110/dce110_hw_sequencer.c | 11 -
4 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cbb4c24d748d..114ee29132fa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3309,9 +3309,11 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
write_i2c_redriver_setting(pipe_ctx, false);
}
}
- dc->hwss.disable_stream(pipe_ctx);
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+
+ dc->hwss.disable_stream(pipe_ctx);
+
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal))
dp_set_dsc_enable(pipe_ctx, false);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6c03dcd6acb5..484a6849f3de 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1102,6 +1102,10 @@ static inline enum link_training_result
perform_link_training_int(
dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
DPCD_TRAINING_PATTERN_VIDEOIDLE;
dpcd_set_training_pattern(link, dpcd_pattern);
+ /* delay 5ms after notifying sink of idle pattern before switching
output */
+ if (link->connector_signal != SIGNAL_TYPE_EDP)
+ msleep(5);
+
/* 4. mainlink output idle pattern*/
dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
@@ -1551,6 +1555,12 @@ bool perform_link_training_with_retries(
struct dc_link *link = stream->link;
enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
+ /* We need to do this before the link training to ensure the idle
pattern in SST
+* mode will be sent right after the link training
+*/
+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+
pipe_ctx->stream_res.stream_enc->id, true);
+
for (j = 0; j < attempts; ++j) {
dp_enable_link_phy(
@@ -1559,21 +1569,14 @@ bool perform_link_training_with_retries(
pipe_ctx->clock_source->id,
link_setting);
- if ((link && link->dc->debug.dppowerup_delay > 0) ||
stream->sink_patches.dppowerup_delay > 0) {
- int delay_dp_power_up_in_ms =
- (link->dc->debug.dppowerup_delay >=
stream->sink_patches.dppowerup_delay) ?
- link->dc->debug.dppowerup_delay :
stream->sink_patches.dppowerup_delay;
+ if (stream->sink_patches.dppowerup_delay > 0) {
+ int delay_dp_power_up_in_ms =
stream->sink_patches.dppowerup_delay;
+
msleep(delay_dp_power_up_in_ms);
}
dp_set_panel_mode(link, panel_mode);
- /* We need to do this before the link training to ensure the
idle pattern in SST
-* mode will be sent right after the link training
-*/
- link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-
pipe_ctx->stream_res.stream_enc->id, true);
-
if (link->aux_access_disabled) {
dc_link_dp_perform_link_training_skip_aux(link,
link_setting);
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f9bdd9115edc..7da41d465a34 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -498,7 +498,6 @@ struct dc_debug_options {
bool usbc_combo_phy_reset_wa;
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
- unsigned int dppowerup_delay;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_seq
[PATCH 09/28] drm/amd/display: Fix VBA chroma calculation for pipe splitting
From: Nicholas Kazlauskas
[Why]
DML failures occur for 420 modes with dynamic pipe
splitting enabled because the ChromaViewport exceeds
the ChromaSurfaceWidth.
This is caused by adding the viewport_width instead
of the viewport_width_c.
This similarly occurs for rotated modes due to the
use of viewport_height instead of viewport_height_c.
[How]
Correct the calculations.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 5a1ca8a5954c..7916a7ea9336 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -623,14 +623,14 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] +=
src_k->viewport_width;
mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] +=
-
src_k->viewport_width;
+
src_k->viewport_width_c;
mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] +=
dst_k->recout_width;
} else {
mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
src_k->viewport_height;
mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] +=
-
src_k->viewport_height;
+
src_k->viewport_height_c;
}
mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] +=
dout_k->dsc_slices;
--
2.17.1
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[PATCH 14/28] drm/amd/display: Passing initial SDP deadline to dmub
From: po-tchen [Why] The SDP deadline indicate the vertical time to send CRC infopacket in PSR. Signed-off-by: po-tchen Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index fd4e1021903a..916d305d3022 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -233,6 +233,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ? true : false; + copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; dc_dmub_srv_cmd_queue(dc->dmub_srv, ); dc_dmub_srv_cmd_execute(dc->dmub_srv); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/28] drm/amd/display: Force delay after DP receive power up
From: Martin Tsai
[Why]
Some sprcified monitor scalar cannot recognize timing
change on demand. Once the link phy disable and enable
during a short period then the Sink protection mechanism
could keep the screen in blank and cannot be recoverred.
[How]
To add 100ms delay between enable link phy and link training.
Signed-off-by: Martin Tsai
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 ---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 08c3b32e188c..674f53aaf2b4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1559,9 +1559,10 @@ bool perform_link_training_with_retries(
pipe_ctx->clock_source->id,
link_setting);
- if (stream->sink_patches.dppowerup_delay > 0) {
- int delay_dp_power_up_in_ms =
stream->sink_patches.dppowerup_delay;
-
+ if ((link && link->dc->debug.dppowerup_delay > 0) ||
stream->sink_patches.dppowerup_delay > 0) {
+ int delay_dp_power_up_in_ms =
+ (link->dc->debug.dppowerup_delay >=
stream->sink_patches.dppowerup_delay) ?
+ link->dc->debug.dppowerup_delay :
stream->sink_patches.dppowerup_delay;
msleep(delay_dp_power_up_in_ms);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cdbfa15874b..9138adf63f9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -498,6 +498,7 @@ struct dc_debug_options {
bool usbc_combo_phy_reset_wa;
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
+ unsigned int dppowerup_delay;
};
struct dc_debug_data {
--
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[PATCH 05/28] drm/amd/display: Move call to disable DPG
From: Wesley Chalmers
[WHY]
Disabling DPG should happen after setting watermarks and clocks
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5b7466a243b2..49dd310ed588 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1248,7 +1248,6 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
- disable_dangling_plane(dc, context);
for (i = 0; i < context->stream_count; i++)
dc_streams[i] = context->streams[i];
@@ -1264,6 +1263,7 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
if (dc->optimize_seamless_boot_streams == 0)
dc->hwss.prepare_bandwidth(dc, context);
+ disable_dangling_plane(dc, context);
/* re-program planes for existing stream, in case we need to
* free up plane resource for later use
*/
--
2.17.1
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[PATCH 02/28] drm/amd/display: Rework dsc to isolate FPU operations
From: Rodrigo Siqueira
When we want to use float point operation on Linux
we need to use within special kernel protection
(`kernel_fpu_{begin,end}()`.), otherwise the kernel
can clobber userspace FPU register state. For detecting
these issues we use a tool named objtool (with -Ffa
flags) to highlight the FPU problems, all warnings can
be summed up as follows:
./tools/objtool/objtool check -Ffa
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.o
[..] dc/dsc/rc_calc.o: warning: objtool: get_qp_set()+0x2f8:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: dsc_roundf()+0x5:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: dsc_ceil()+0x5:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: get_ofs_set()+0x3eb:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: calc_rc_params()+0x3c:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/dc_dsc.o: warning: objtool:
get_dsc_bandwidth_range.isra.0()+0x8d:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/dc_dsc.o: warning: objtool: setup_dsc_config()+0x2ef:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc_dpi.o: warning: objtool:copy_pps_fields()+0xbb:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc_dpi.o: warning: objtool:
dscc_compute_dsc_parameters()+0x7b:
FPU instruction outside of kernel_fpu_{begin,end}()
This commit fixes the above issues by rework DSC as described:
1. Isolate all FPU operations in a single file;
2. Use FPU flags only in the file that handles FPU operations;
3. Isolate all functions that require float point operation in static
functions;
4. Add a mid-layer function that does not use any float point operation,
and that could be safely invoked in other parts of the code.
5. Keep float point operation under DC_FP_{START/END} macro.
CC: Christian König
CC: Alexander Deucher
CC: Peter Zijlstra
CC: Tony Cheng
CC: Harry Wentland
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Mikita Lipski
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dsc/Makefile | 2 -
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 18 +--
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 151 +-
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 5 +-
.../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 27 +---
5 files changed, 153 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 3f66868df171..ea29cf95d470 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -28,8 +28,6 @@ endif
endif
CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_ccflags)
DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 0ea6662a1563..0c7f247bb7de 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -22,10 +22,12 @@
* Author: AMD
*/
+#include
#include "dc_hw_types.h"
#include "dsc.h"
#include
#include "dc.h"
+#include "rc_calc.h"
/* This module's internal functions */
@@ -304,22 +306,6 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t
value)
return (value + 9) / 10;
}
-static inline uint32_t calc_dsc_bpp_x16(uint32_t stream_bandwidth_kbps,
uint32_t pix_clk_100hz, uint32_t bpp_increment_div)
-{
- uint32_t dsc_target_bpp_x16;
- float f_dsc_target_bpp;
- float f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
- uint32_t precision = bpp_increment_div; // bpp_increment_div is
actually precision
-
- f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
-
- // Round down to the nearest precision stop to bring it into DSC spec
range
- dsc_target_bpp_x16 = (uint32_t)(f_dsc_target_bpp * precision);
- dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
-
- return dsc_target_bpp_x16;
-}
-
/* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range,
and timing's pixel clock
* and uncompressed bandwidth.
*/
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 03ae15946c6d..667afbc260f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -23,6 +23,7 @@
* Authors: AMD
*
*/
+#include
#include "os_types.h"
#include "rc_calc.h"
@@ -40,7 +41,8 @@
break
-void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, enum
max_min max_min, float bpp)
+static void get_qp
[PATCH 23/28] drm/amd/display: change global buffer to local buffer
From: Lewis Huang
[Why]
Multi-adapter calculate regamma table at the same time.
Two thread used the same global variable cause race
condition.
[How]
Change global buffer to local buffer
Signed-off-by: Lewis Huang
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 10 +-
.../drm/amd/display/modules/color/Makefile| 4 +
.../amd/display/modules/color/color_gamma.c | 115 ++
.../amd/display/modules/color/color_gamma.h | 18 ++-
.../amd/display/modules/color/color_table.c | 48
.../amd/display/modules/color/color_table.h | 47 +++
6 files changed, 183 insertions(+), 59 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.c
create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.h
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 4dfb6b55bb2e..b321ff654df4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -195,10 +195,13 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
bool has_rom)
{
struct dc_gamma *gamma = NULL;
+ struct calculate_buffer cal_buffer = {0};
bool res;
ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES);
+ cal_buffer.buffer_index = -1;
+
gamma = dc_create_gamma();
if (!gamma)
return -ENOMEM;
@@ -208,7 +211,7 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
__drm_lut_to_dc_gamma(lut, gamma, true);
res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
-NULL);
+NULL, _buffer);
dc_gamma_release();
@@ -221,10 +224,13 @@ static int __set_output_tf(struct dc_transfer_func *func,
bool has_rom)
{
struct dc_gamma *gamma = NULL;
+ struct calculate_buffer cal_buffer = {0};
bool res;
ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES);
+ cal_buffer.buffer_index = -1;
+
gamma = dc_create_gamma();
if (!gamma)
return -ENOMEM;
@@ -248,7 +254,7 @@ static int __set_output_tf(struct dc_transfer_func *func,
*/
gamma->type = GAMMA_CS_TFM_1D;
res = mod_color_calculate_regamma_params(func, gamma, false,
-has_rom, NULL);
+has_rom, NULL,
_buffer);
}
dc_gamma_release();
diff --git a/drivers/gpu/drm/amd/display/modules/color/Makefile
b/drivers/gpu/drm/amd/display/modules/color/Makefile
index 65c33a76951a..3ee7f27ff93b 100644
--- a/drivers/gpu/drm/amd/display/modules/color/Makefile
+++ b/drivers/gpu/drm/amd/display/modules/color/Makefile
@@ -25,6 +25,10 @@
MOD_COLOR = color_gamma.o
+ifdef CONFIG_DRM_AMD_DC_DCN
+MOD_COLOR += color_table.o
+endif
+
AMD_DAL_MOD_COLOR = $(addprefix $(AMDDALPATH)/modules/color/,$(MOD_COLOR))
#$(info DAL COLOR MODULE MAKEFILE )
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 9431b48aecb4..05f1651b7171 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -30,20 +30,10 @@
#include "opp.h"
#include "color_gamma.h"
-#define NUM_PTS_IN_REGION 16
-#define NUM_REGIONS 32
-#define MAX_HW_POINTS (NUM_PTS_IN_REGION*NUM_REGIONS)
-
static struct hw_x_point coordinates_x[MAX_HW_POINTS + 2];
-static struct fixed31_32 pq_table[MAX_HW_POINTS + 2];
-static struct fixed31_32 de_pq_table[MAX_HW_POINTS + 2];
-
// these are helpers for calculations to reduce stack usage
// do not depend on these being preserved across calls
-static struct fixed31_32 scratch_1;
-static struct fixed31_32 scratch_2;
-static struct translate_from_linear_space_args scratch_gamma_args;
/* Helper to optimize gamma calculation, only use in translate_from_linear, in
* particular the dc_fixpt_pow function which is very expensive
@@ -56,9 +46,6 @@ static struct translate_from_linear_space_args
scratch_gamma_args;
* just multiply with 2^gamma which can be computed once, and save the result
so we
* recursively compute all the values.
*/
-static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION];
-static struct fixed31_32 gamma_of_2; // 2^gamma
-int pow_buffer_ptr = -1;
/*sRGB 709 2.2 2.4 P3*/
static const int32_t gamma_numerator01[] = { 31308,18, 0, 0,
0};
static const int32_t gamma_numerator02[] = { 12920,4500, 0, 0,
[PATCH 18/28] drm/amd/display: add support for per-state dummy-pstate latency
From: Jun Lei
[why]
Dummy pstate latency actually varies between different
UCLK frequencies, when calculating watermark C, if DAL
always assumes worst case, then it can lead to dummy
pstate not supported scenarios.
[how]
Rather than statically calculating dummy pstate using
worst case, we store the entire table of UCLK to dummy
pstate relationships. On a per mode basis, we calculate
the actual UCLK lower limit, and use the dynamic worst
case dummy pstate latency. This prevents the situation
where we don't support full p-state (which will force
high DPM), but still use low DPM dummy pstate latency.
Signed-off-by: Jun Lei
Reviewed-by: Joshua Aberback
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 49c50af9cd9e..505357597603 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -198,11 +198,17 @@ struct wm_table {
#endif
};
+struct dummy_pstate_entry {
+ unsigned int dram_speed_mts;
+ unsigned int dummy_pstate_latency_us;
+};
+
struct clk_bw_params {
unsigned int vram_type;
unsigned int num_channels;
struct clk_limit_table clk_table;
struct wm_table wm_table;
+ struct dummy_pstate_entry dummy_pstate_table[4];
};
/* Public interfaces */
--
2.17.1
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[PATCH 20/28] drm/amd/display: make calculate watermarks a function pointer
From: Dmytro Laktyushkin
To allow code reuse with minimal duplication watermark
calculation needs to be function pointer.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 4fbed8dd0c59..5f985fcbedf1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -101,7 +101,11 @@ struct resource_funcs {
struct dc *dc,
struct dc_state *context,
bool fast_validate);
-
+ void (*calculate_wm)(
+ struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt,
+ int vlevel);
int (*populate_dml_pipes)(
struct dc *dc,
struct dc_state *context,
--
2.17.1
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[PATCH 01/28] drm/amd/display: correct alpha_en programming for new pixel format
From: Charlene Liu [why] for following new format, no alpha SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT/_FIX: SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT/_FIX same as case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: Signed-off-by: Charlene Liu Reviewed-by: Chris Park Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c index 42bba7c9548b..4af96cc5d9d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c @@ -181,9 +181,11 @@ static void dpp2_cnv_setup ( break; case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FIX: pixel_format = 112; + alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FIX: pixel_format = 113; + alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: pixel_format = 114; @@ -199,9 +201,11 @@ static void dpp2_cnv_setup ( break; case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT: pixel_format = 118; + alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT: pixel_format = 119; + alpha_en = 0; break; default: break; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 24/28] drm/amd/display: Disable pipe split for modes with borders
From: Dale Zhao
[Why]
For some special timing with border, like DMT 640*480 72Hz,
pipe split can't handle well. Thus, it will be black screen
for these special timing.
[How]
Disable pipe split for these timing with borders as W/A.
Signed-off-by: Dale Zhao
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index afa99f967558..fb167393b8fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2666,6 +2666,23 @@ int dcn20_validate_apply_pipe_split_flags(
if (plane_count > dc->res_pool->pipe_count / 2)
avoid_split = true;
+ /* W/A: Mode timing with borders may not work well with pipe split,
avoid for this corner case */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+ struct dc_crtc_timing timing;
+
+ if (!pipe->stream)
+ continue;
+ else {
+ timing = pipe->stream->timing;
+ if (timing.h_border_left + timing.h_border_right
+ + timing.v_border_top +
timing.v_border_bottom > 0) {
+ avoid_split = true;
+ break;
+ }
+ }
+ }
+
/* Avoid split loop looks for lowest voltage level that allows most
unsplit pipes possible */
if (avoid_split) {
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
--
2.17.1
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[PATCH 17/28] drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs update"
From: Wenjing Liu
[why]
The change causes some regression in a common use case.
Will need more investigation before fixing the original issue.
[how]
This reverts commit ad418864c63a1718f9e283207b3fac96fbc148c2.
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +-
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 13 ++--
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 59 ++-
.../drm/amd/display/dc/core/dc_link_hwss.c| 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 -
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
.../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 2 +-
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +-
9 files changed, 42 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cb5491fb326c..cbb4c24d748d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -690,11 +690,9 @@ static bool detect_dp(struct dc_link *link,
if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-
+ dpcd_set_source_specific_data(link);
if (!detect_dp_sink_caps(link))
return false;
- dpcd_set_source_specific_data(link);
-
if (is_mst_supported(link)) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
link->type = dc_connection_mst_branch;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 242ed5976cdb..aefd29a440b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -648,17 +648,16 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service
*ddc,
}
-bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
+uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
uint32_t timeout)
{
- bool result = false;
+ uint32_t prev_timeout = 0;
struct ddc *ddc_pin = ddc->ddc_pin;
- if
(ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
{
-
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc,
timeout);
- result = true;
- }
- return result;
+ if
(ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
+ prev_timeout =
+
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc,
timeout);
+ return prev_timeout;
}
/*test only function*/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 674f53aaf2b4..6c03dcd6acb5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -245,7 +245,7 @@ static uint8_t dc_dp_initialize_scrambling_data_symbols(
static inline bool is_repeater(struct dc_link *link, uint32_t offset)
{
- return (link->lttpr_non_transparent_mode && offset != 0);
+ return (!link->is_lttpr_mode_transparent && offset != 0);
}
static void dpcd_set_lt_pattern_and_lane_settings(
@@ -1038,7 +1038,7 @@ static enum link_training_result
perform_clock_recovery_sequence(
/* 3. wait receiver to lock-on*/
wait_time_microsec = lt_settings->cr_pattern_time;
- if (link->lttpr_non_transparent_mode)
+ if (!link->is_lttpr_mode_transparent)
wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
wait_for_training_aux_rd_interval(
@@ -1268,7 +1268,7 @@ static void configure_lttpr_mode(struct dc_link *link)
link->dpcd_caps.lttpr_caps.mode = repeater_mode;
}
- if (link->lttpr_non_transparent_mode) {
+ if (!link->is_lttpr_mode_transparent) {
DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent
Mode\n", __func__);
@@ -1473,7 +1473,7 @@ enum link_training_result
dc_link_dp_perform_link_training(
_settings);
/* Configure lttpr mode */
- if (link->lttpr_non_transparent_mode)
+ if (!link->is_lttpr_mode_transparent)
configure_lttpr_mode(link);
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
@@ -1489,7 +1489,7 @@ enum link_training_result
dc_link_dp_perform_link_training(
dp_set_fec_ready(link, fec_
[PATCH 08/28] drm/amd/display: Revert "enable plane if plane_status changed"
From: Hugo Hu
revert commit 77dcea7a0b133b362b2ebbf494eb13ee3e946836.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0b318f799db3..65e83fdd7b44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1209,20 +1209,13 @@ void dcn20_pipe_control_lock(
static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct
pipe_ctx *new_pipe)
{
- bool plane_state_update = false;
new_pipe->update_flags.raw = 0;
/* Exit on unchanged, unused pipe */
if (!old_pipe->plane_state && !new_pipe->plane_state)
return;
-
- /* Detect plane state update */
- if (old_pipe->plane_state && new_pipe->plane_state
- && (old_pipe->plane_state != new_pipe->plane_state)) {
- plane_state_update = true;
- }
/* Detect pipe enable/disable */
- if ((!old_pipe->plane_state && new_pipe->plane_state) ||
plane_state_update) {
+ if (!old_pipe->plane_state && new_pipe->plane_state) {
new_pipe->update_flags.bits.enable = 1;
new_pipe->update_flags.bits.mpcc = 1;
new_pipe->update_flags.bits.dppclk = 1;
--
2.17.1
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[PATCH 03/28] drm/amd/display: Fix incorrect dcn1 bandwidth calculations
From: Michael Strauss
[WHY]
Typos cause bandwidth calculation errors, one
of which can cause infinite loop on dcn1 with eDP
Signed-off-by: Michael Strauss
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index 1ef0074302c5..41284e263325 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -805,7 +805,7 @@ void mode_support_and_system_configuration(struct
dcn_bw_internal_vars *v)
if (v->pte_enable == dcn_bw_yes &&
v->dcc_enable[k] == dcn_bw_yes) {
v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
-
v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k],
+
v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],
v->extra_latency,
v->htotal[k] /
v->pixel_clock[k] / 4.0);
} else {
@@ -814,7 +814,7 @@ void mode_support_and_system_configuration(struct
dcn_bw_internal_vars *v)
if (v->pte_enable == dcn_bw_yes ||
v->dcc_enable[k] == dcn_bw_yes) {
v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
-
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bandwidth[k],
+
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
v->htotal[k] /
v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
v->extra_latency);
} else {
@@ -827,7 +827,7 @@ void mode_support_and_system_configuration(struct
dcn_bw_internal_vars *v)
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 *
(v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] /
v->pixel_clock[k]) + 0.125), 1.0) / 4;
v->maximum_vstartup =
v->maximum_vstartup - 1;
- if
(v->lines_for_meta_pte_without_immediate_flip[k] < 8.0 &&
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
+ if
(v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 &&
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
break;
} while(1);
--
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[PATCH 15/28] drm/amd/display: runtime select dmub emulatior.
From: Yongqiang Sun
[Why & How]
Add emul specific hw function to dmub, in case of
emulator is created, we can runtime switch between
dmub emulator or dmub uC via is_virtual flag in dmub.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 16
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 93d6ff80b248..c6a8d6c54621 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -256,6 +256,10 @@ struct dmub_srv_hw_funcs {
void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
+ uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);
+
+ void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t
wptr_offset);
+
bool (*is_supported)(struct dmub_srv *dmub);
bool (*is_hw_init)(struct dmub_srv *dmub);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 937f6c3c9911..eb51b7920864 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -199,13 +199,13 @@ enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
/* Override (some) hardware funcs based on user params. */
if (params->hw_funcs) {
- if (params->hw_funcs->get_inbox1_rptr)
- dmub->hw_funcs.get_inbox1_rptr =
- params->hw_funcs->get_inbox1_rptr;
+ if (params->hw_funcs->emul_get_inbox1_rptr)
+ dmub->hw_funcs.emul_get_inbox1_rptr =
+ params->hw_funcs->emul_get_inbox1_rptr;
- if (params->hw_funcs->set_inbox1_wptr)
- dmub->hw_funcs.set_inbox1_wptr =
- params->hw_funcs->set_inbox1_wptr;
+ if (params->hw_funcs->emul_set_inbox1_wptr)
+ dmub->hw_funcs.emul_set_inbox1_wptr =
+ params->hw_funcs->emul_set_inbox1_wptr;
if (params->hw_funcs->is_supported)
dmub->hw_funcs.is_supported =
@@ -502,7 +502,7 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
*/
dmub_rb_flush_pending(>inbox1_rb);
- dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
+ dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
return DMUB_STATUS_OK;
}
@@ -557,7 +557,7 @@ enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv
*dmub,
return DMUB_STATUS_INVALID;
for (i = 0; i <= timeout_us; ++i) {
- dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
+ dmub->inbox1_rb.rptr =
dmub->hw_funcs.get_inbox1_rptr(dmub);
if (dmub_rb_empty(>inbox1_rb))
return DMUB_STATUS_OK;
--
2.17.1
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[PATCH 19/28] drm/amd/display: Add helper to convert DC status
From: Rodrigo Siqueira
During the debugging process related to a hot-plug
problem with 4k display, we realized that we had
some issues related to the global state validation.
This problem was not explicitly highlighted in the
dmesg log, for this reason, this commit adds a function
that converts `enum dc_status` to a human-readable
string and appends the proper warning message in case
of failure.
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Harry Wentland
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++--
.../gpu/drm/amd/display/dc/core/dc_debug.c| 59 +++
.../gpu/drm/amd/display/dc/inc/core_status.h | 2 +
3 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f348693217d8..9ab0d8521576 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5152,11 +5152,12 @@ create_validate_stream_for_sink(struct
amdgpu_dm_connector *aconnector,
dc_result = dc_validate_stream(adev->dm.dc, stream);
if (dc_result != DC_OK) {
- DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation
with error %d\n",
+ DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation
with error %d (%s)\n",
drm_mode->hdisplay,
drm_mode->vdisplay,
drm_mode->clock,
- dc_result);
+ dc_result,
+ dc_status_to_str(dc_result));
dc_stream_release(stream);
stream = NULL;
@@ -8593,7 +8594,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_plane_state *old_plane_state, *new_plane_state;
enum surface_update_type update_type = UPDATE_TYPE_FAST;
enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
-
+ enum dc_status status;
int ret, i;
/*
@@ -8805,8 +8806,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;
-
- if (dc_validate_global_state(dc, dm_state->context, false) !=
DC_OK) {
+ status = dc_validate_global_state(dc, dm_state->context, false);
+ if (status != DC_OK) {
+ DC_LOG_WARNING("DC global validation failure: %s (%d)",
+ dc_status_to_str(status), status);
ret = -EINVAL;
goto fail;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 502ed3c7959d..87d89449b9af 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -365,3 +365,62 @@ void context_clock_trace(
context->bw_ctx.bw.dcn.clk.socclk_khz);
#endif
}
+
+/**
+ * dc_status_to_str - convert dc_status to a human readable string
+ * @status: dc_status to be converted
+ *
+ * Return:
+ * A string describing the DC status.
+ */
+char *dc_status_to_str(enum dc_status status)
+{
+ switch (status) {
+ case DC_OK:
+ return "DC OK";
+ case DC_NO_CONTROLLER_RESOURCE:
+ return "No controller resource";
+ case DC_NO_STREAM_ENC_RESOURCE:
+ return "No stream encoder";
+ case DC_NO_CLOCK_SOURCE_RESOURCE:
+ return "No clock source";
+ case DC_FAIL_CONTROLLER_VALIDATE:
+ return "Controller validation failure";
+ case DC_FAIL_ENC_VALIDATE:
+ return "Encoder validation failure";
+ case DC_FAIL_ATTACH_SURFACES:
+ return "Surfaces attachment failure";
+ case DC_FAIL_DETACH_SURFACES:
+ return "Surfaces detachment failure";
+ case DC_FAIL_SURFACE_VALIDATE:
+ return "Surface validation failure";
+ case DC_NO_DP_LINK_BANDWIDTH:
+ return "No DP link bandwidth";
+ case DC_EXCEED_DONGLE_CAP:
+ return "Exceed dongle capability";
+ case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED:
+ return "Unsupported pixel format";
+ case DC_FAIL_BANDWIDTH_VALIDATE:
+ return "Bandwidth validation failure (BW and Watermark)";
+ case DC_FAIL_SCALING:
+ return "Scaling failure";
+ case DC_FAIL_DP_LINK_TRAINING:
+ return "DP link training failure
[PATCH 07/28] drm/amd/display: Remove unused macro from dcn21
From: Roman Li [Why] SOC_BOUNDING_BOX_VALID is unused and not required for dcn21. [How] Remove it. Signed-off-by: Roman Li Reviewed-by: Bhawanpreet Lakha Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 00436654c584..24aa3f1db031 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -88,7 +88,6 @@ #include "dce/dmub_psr.h" #include "dce/dmub_abm.h" -#define SOC_BOUNDING_BOX_VALID false #define DC_LOGGER_INIT(logger) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/28] drm/amd/display: [FW Promotion] Release 1.0.14
From: Anthony Koo
[Header Changes]
- Add SDP transmission deadline for PSR config cmd
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index d04d2fc9ea61..5066c639670e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x3353119e1
+#define DMUB_FW_VERSION_GIT_HASH 0x5470fd231
#define DMUB_FW_VERSION_MAJOR 1
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 13
+#define DMUB_FW_VERSION_REVISION 14
#define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) |
(DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
#endif
@@ -421,6 +421,8 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t frame_delay;
uint8_t frame_cap_ind;
uint8_t pad[3];
+ uint16_t init_sdp_deadline;
+ uint16_t pad2;
};
struct dmub_rb_cmd_psr_copy_settings {
--
2.17.1
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[PATCH 25/28] drm/amd/display: not reset dmub in driver.
From: Yongqiang Sun
[Why]
during S0i3, set power state is toggled a few times,
and dmub uC will restart with current reset/hw_init.
[How]
Remove reset in set power state, and before doing hw_init,
check if dmub is enabled, and doing FW autoload check only
if dmub is already enabled.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 1e03f6fdabd6..2c4a2fe9311d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -275,7 +275,11 @@ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub,
uint32_t wptr_offset)
bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
{
- return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
+ uint32_t is_hw_init;
+
+ REG_GET(DMCUB_CNTL, DMCUB_ENABLE, _hw_init);
+
+ return is_hw_init != 0;
}
bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
--
2.17.1
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[PATCH 21/28] drm/amd/display: Enable use of dmub iff dmcu is disabled
From: Aurabindo Pillai
[Why & How]
DMUB command table should be allowed to be used
only if dmcu is explicitly disabled.
Signed-off-by: Aurabindo Pillai
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7a37065c55d1..7a038eef8902 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1906,6 +1906,8 @@ static bool dcn21_resource_construct(
BREAK_TO_DEBUGGER();
goto create_fail;
}
+
+ dc->debug.dmub_command_table = false;
}
if (dc->config.disable_dmcu) {
--
2.17.1
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[PATCH 26/28] drm/amd/display: Not doing bios data pack.
From: Yongqiang Sun
[Why]
dmub FW running abnormal after resume from S0i3 due
to data aliagnment issue.
[How]
Before having a solution for this issue, temparory
not doing data pack.
Signed-off-by: Yongqiang Sun
Reviewed-by: Sung Lee
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 150cdbc02d44..9311fec1643c 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1880,10 +1880,12 @@ static enum bp_result bios_get_board_layout_info(
return BP_RESULT_OK;
}
+
static uint16_t bios_parser_pack_data_tables(
struct dc_bios *dcb,
void *dst)
{
+#ifdef PACK_BIOS_DATA
struct bios_parser *bp = BP_FROM_DCB(dcb);
struct atom_rom_header_v2_2 *rom_header = NULL;
struct atom_rom_header_v2_2 *packed_rom_header = NULL;
@@ -1975,6 +1977,9 @@ static uint16_t bios_parser_pack_data_tables(
}
}
return packed_data_tbl_offset;
+#endif
+ // TODO: There is data bytes alignment issue, disable it for now.
+ return 0;
}
static const struct dc_vbios_funcs vbios_funcs = {
--
2.17.1
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[PATCH 10/28] drm/amd/display: update audio wall clock programming
From: Charlene Liu
[why]
for audio on real TV issue.
[how]
-add wall clock programming for DPREF based when
Pixel clock is done by DP DTO.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 5a35495bc11d..408046579712 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -140,6 +140,8 @@ static void check_audio_bandwidth_hdmi(
bool limit_freq_to_88_2_khz = false;
bool limit_freq_to_96_khz = false;
bool limit_freq_to_174_4_khz = false;
+ if (!crtc_info)
+ return;
/* For two channels supported return whatever sink support,unmodified*/
if (channel_count > 2) {
@@ -784,7 +786,7 @@ void dce_aud_wall_dto_setup(
struct azalia_clock_info clock_info = { 0 };
- if (dc_is_hdmi_signal(signal)) {
+ if (dc_is_hdmi_tmds_signal(signal)) {
uint32_t src_sel;
/*DTO0 Programming goal:
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2ec5e9e1bdc6..0ce430cf4dd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1148,7 +1148,7 @@ static void build_audio_output(
pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
/*for HDMI, audio ACR is with deep color ratio factor*/
- if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
+ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
audio_output->crtc_info.requested_pixel_clock_100Hz ==
(stream->timing.pix_clk_100hz)) {
if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding ==
PIXEL_ENCODING_YCBCR420) {
@@ -1963,10 +1963,8 @@ static void dce110_setup_audio_dto(
if (pipe_ctx->top_pipe)
continue;
-
if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
continue;
-
if (pipe_ctx->stream_res.audio != NULL) {
struct audio_output audio_output;
--
2.17.1
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[PATCH 00/28] DC Patches June 8, 2020
This DC patchset brings changes in multiple areas. In summary, we highlight: * Bug fixes in bandwidth calculation, DSC calculation, etc. * Improvements in DP * Code refactoring and cleanup * FW promotion Anthony Koo (3): drm/amd/display: [FW Promotion] Release 1.0.13 drm/amd/display: [FW Promotion] Release 1.0.14 drm/amd/display: [FW Promotion] Release 1.0.15 Aric Cyr (3): drm/amd/display: 3.2.88 drm/amd/display: Improve DisplayPort monitor interop drm/amd/display: 3.2.89 Aurabindo Pillai (1): drm/amd/display: Enable use of dmub iff dmcu is disabled Charlene Liu (2): drm/amd/display: correct alpha_en programming for new pixel format drm/amd/display: update audio wall clock programming Dale Zhao (1): drm/amd/display: Disable pipe split for modes with borders Dmytro Laktyushkin (2): drm/amd/display: remove unnecessary mpcc updates drm/amd/display: make calculate watermarks a function pointer Hugo Hu (1): drm/amd/display: Revert "enable plane if plane_status changed" Jun Lei (1): drm/amd/display: add support for per-state dummy-pstate latency Lewis Huang (1): drm/amd/display: change global buffer to local buffer Martin Tsai (1): drm/amd/display: Force delay after DP receive power up Michael Strauss (1): drm/amd/display: Fix incorrect dcn1 bandwidth calculations Nicholas Kazlauskas (2): drm/amd/display: Use u16 for drm_bpp in DSC calculations drm/amd/display: Fix VBA chroma calculation for pipe splitting Rodrigo Siqueira (2): drm/amd/display: Rework dsc to isolate FPU operations drm/amd/display: Add helper to convert DC status Roman Li (1): drm/amd/display: Remove unused macro from dcn21 Wenjing Liu (1): drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs update" Wesley Chalmers (1): drm/amd/display: Move call to disable DPG Yongqiang Sun (3): drm/amd/display: runtime select dmub emulatior. drm/amd/display: not reset dmub in driver. drm/amd/display: Not doing bios data pack. po-tchen (1): drm/amd/display: Passing initial SDP deadline to dmub .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 10 +- .../drm/amd/display/dc/bios/bios_parser2.c| 5 + .../drm/amd/display/dc/calcs/dcn_calc_auto.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_debug.c| 59 +++ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 13 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 75 + .../drm/amd/display/dc/core/dc_link_hwss.c| 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 1 - .../gpu/drm/amd/display/dc/dce/dce_audio.c| 4 +- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 + .../display/dc/dce110/dce110_hw_sequencer.c | 15 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 4 + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 22 +-- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 17 ++ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 5 +- .../drm/amd/display/dc/dml/display_mode_vba.c | 4 +- drivers/gpu/drm/amd/display/dc/dsc/Makefile | 2 - drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 18 +-- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 151 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 5 +- .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 27 +--- .../gpu/drm/amd/display/dc/inc/core_status.h | 2 + .../gpu/drm/amd/display/dc/inc/core_types.h | 6 +- .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 2 +- .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +- .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 70 +++- .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 6 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 16 +- .../drm/amd/display/modules/color/Makefile| 4 + .../amd/display/modules/color/color_gamma.c | 115 ++--- .../amd/display/modules/color/color_gamma.h | 18 ++- .../amd/display/modules/color/color_table.c | 48 ++ .../amd/display/modules/color/color_table.h | 47 ++ 39 files changed, 612 insertions(+), 207 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.c create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/28] drm/amd/display: 3.2.88
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e09eb876a366..8cdbfa15874b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.87" +#define DC_VER "3.2.88" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 27/28] drm/amd/display: [FW Promotion] Release 1.0.15
From: Anthony Koo
[Header Changes]
- Add new initialization bits for driver to check
firmware status
- Add command for HW locking via DMUB
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 68 ++-
1 file changed, 65 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 5066c639670e..7c03c4798348 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x5470fd231
+#define DMUB_FW_VERSION_GIT_HASH 0xee850bb2f
#define DMUB_FW_VERSION_MAJOR 1
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 14
+#define DMUB_FW_VERSION_REVISION 15
#define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) |
(DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
#endif
@@ -137,8 +137,31 @@ union dmub_fw_meta {
};
#pragma pack(pop)
+
+//==
+//<
DMUB_STATUS>
+//==
+
+/**
+ * DMCUB scratch registers can be used to determine firmware status.
+ * Current scratch register usage is as follows:
+ *
+ * SCRATCH0: Legacy status register
+ * SCRATCH1: Firmware version
+ * SCRATCH2: Firmware status bits defined by dmub_fw_status_bit
+ * SCRATCH3: Reserved firmware status bits
+ */
+
+/**
+ * DMCUB firmware status bits for SCRATCH2.
+ */
+enum dmub_fw_status_bit {
+ DMUB_FW_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
+ DMUB_FW_STATUS_BIT_COMMAND_TABLE_READY = (1 << 1),
+};
+
//==
-//==
+//
//==
//<
DMUB_VBIOS>=
//==
@@ -230,6 +253,7 @@ enum dmub_cmd_type {
DMUB_CMD__PLAT_54186_WA = 5,
DMUB_CMD__PSR = 64,
DMUB_CMD__ABM = 66,
+ DMUB_CMD__HW_LOCK = 69,
DMUB_CMD__VBIOS = 128,
};
@@ -453,6 +477,44 @@ struct dmub_rb_cmd_psr_set_version {
struct dmub_cmd_psr_set_version_data psr_set_version_data;
};
+union dmub_hw_lock_flags {
+ struct {
+ uint8_t lock_pipe : 1;
+ uint8_t lock_cursor : 1;
+ uint8_t lock_dig: 1;
+ uint8_t triple_buffer_lock : 1;
+ } bits;
+
+ uint8_t u8All;
+};
+
+struct dmub_hw_lock_inst_flags {
+ uint8_t otg_inst;
+ uint8_t opp_inst;
+ uint8_t dig_inst;
+ uint8_t pad;
+};
+
+enum hw_lock_client {
+ HW_LOCK_CLIENT_DRIVER = 0,
+ HW_LOCK_CLIENT_FW,
+ HW_LOCK_CLIENT_INVALID = 0x,
+};
+
+struct dmub_cmd_lock_hw_data {
+ enum hw_lock_client client;
+ struct dmub_hw_lock_inst_flags inst_flags;
+ union dmub_hw_lock_flags hw_locks;
+ uint8_t lock;
+ uint8_t should_release;
+ uint8_t pad;
+};
+
+struct dmub_rb_cmd_lock_hw {
+ struct dmub_cmd_header header;
+ struct dmub_cmd_lock_hw_data lock_hw_data;
+};
+
enum dmub_cmd_abm_type {
DMUB_CMD__ABM_INIT_CONFIG = 0,
DMUB_CMD__ABM_SET_PIPE = 1,
--
2.17.1
___
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