On 05/11/2018 10:26 AM, zhoucm1 wrote:
On 2018年05月11日 10:19, Zhang, Jerry (Junwei) wrote:
On 05/11/2018 10:11 AM, zhoucm1 wrote:
On 2018年05月11日 09:21, Zhang, Jerry (Junwei) wrote:
On 05/10/2018 10:40 PM, Christian König wrote:
Am 10.05.2018 um 07:01 schrieb Junwei Zhang:
Expect to add
On 05/10/2018 10:40 PM, Christian König wrote:
Am 10.05.2018 um 07:01 schrieb Junwei Zhang:
Expect to add an evitable bo who has reservation object
to the correct lru[bo->priority] list
Nice catch, but since this affects only a very small use case can we just remove
and readd the BO to the
2, 3, 4, 5 are
Reviewed-by: Junwei Zhang
Patch 1:
could you show the reserving VM?
Patch 6:
I could read that code, but not sure the purpose.
Jerry
On 05/17/2018 05:49 PM, Christian König wrote:
Only the moved state needs a separate spin lock protection. All other
On 05/17/2018 04:51 AM, Alex Deucher wrote:
Signed-off-by: Alex Deucher
Series is
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h | 4
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4
On 05/17/2018 04:51 AM, Alex Deucher wrote:
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h | 4
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4
2
On 05/23/2018 01:45 PM, Huang Rui wrote:
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 27 ++-
1 file changed, 26
On 05/25/2018 05:35 PM, Christian König wrote:
Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 03:54 PM, Christian König wrote:
Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom
On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying problem.
Somebody is accessing the page array when it should never be accessed.
If prime import as GTT bo by default(now it's CPU bo), it would happens quickly
when GTT sg bo
On 05/25/2018 03:54 PM, Christian König wrote:
Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying problem.
Somebody is accessing the page array when it should never be accessed
On 06/12/2018 10:25 AM, zhoucm1 wrote:
On 2018年06月11日 21:23, Christian König wrote:
Per VM BOs share the reservation object with the PD and so need to
reserve a shared fence slot for the update.
Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
Reviewed-by: Junwei Zhang
---
On 06/15/2018 03:22 PM, zhoucm1 wrote:
On 2018年06月15日 15:16, Zhang, Jerry wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Friday, June 15, 2018 15:09
To: Zhou, David(ChunMing) ; amd-
g...@lists.freedesktop.org
On 06/04/2018 02:43 PM, Christian König wrote:
Actually that is not correct. According to the documentation the PRT flag should
work for huge pages as well.
Mmm, I checked the doc earlier, didn't find the PRT flag for PDE.
In CTS PRT test, the reserved PRT mapping introduces huge page
On 06/04/2018 03:48 PM, Christian König wrote:
Am 04.06.2018 um 09:02 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 02:43 PM, Christian König wrote:
Actually that is not correct. According to the documentation the PRT flag should
work for huge pages as well.
Mmm, I checked the doc earlier
se part(reserved PRT range) bo_va is different from the target
one(tiled bo). so has to do bo update for else bo_va.
(under debugging...)
Thanks,
Christian.
Am 04.06.2018 um 11:51 schrieb Christian König:
Am 04.06.2018 um 10:19 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 03:48 PM, Christ
On 06/05/2018 04:20 PM, zhoucm1 wrote:
On 2018年06月05日 16:14, Christian König wrote:
Am 05.06.2018 um 10:09 schrieb Junwei Zhang:
From: Christian König
(comments: I cannot receive amdgfx mail recently and reply the mail directly,
so send it out with my update v2, tested with Unigine Heaven,
On 06/05/2018 04:54 PM, Christian König wrote:
Am 05.06.2018 um 10:47 schrieb Zhang, Jerry (Junwei):
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list
On 06/04/2018 05:51 PM, Christian König wrote:
Am 04.06.2018 um 10:19 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 03:48 PM, Christian König wrote:
Am 04.06.2018 um 09:02 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 02:43 PM, Christian König wrote:
Actually that is not correct. According
On 06/05/2018 02:20 PM, Christian König wrote:
Hi Jerry,
Am 05.06.2018 um 03:50 schrieb Zhang, Jerry (Junwei):
[SNIP]
Can you check if the problem also vanishes when you disable the following
optimization in amdgpu_vm_update_ptes?
/* We don't need to update PTEs for huge
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list because it is possible
that we need to split up huge pages for them.
Signed-off-by: Christian König
On 05/25/2018 07:23 PM, Christian König wrote:
Am 25.05.2018 um 11:51 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 05:35 PM, Christian König wrote:
Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 03:54 PM, Christian König wrote:
Am 25.05.2018 um 09:20 schrieb Zhang, Jerry
On 06/28/2018 12:52 AM, Felix Kuehling wrote:
On 2018-06-26 09:42 PM, Zhang, Jerry (Junwei) wrote:
BTW, kfd2kgd_calls kfd2kgd looks duplicated in amdkfd_gfx_v7/8/9.c
we may initialize it in a common place(at least for common members).
If it has other purpose, please ignore that.
Some
On 06/26/2018 03:46 PM, Michel Dänzer wrote:
On 2018-06-26 08:00 AM, Junwei Zhang wrote:
It could be got by amdgpu_bo_gpu_offset() if need
Signed-off-by: Junwei Zhang
[...]
@@ -931,7 +928,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32
domain,
* amdgpu_bo_pin - pin an _bo
On 06/26/2018 03:42 PM, Michel Dänzer wrote:
On 2018-06-26 08:00 AM, Junwei Zhang wrote:
Instead of calling gart memory on every bo pin,
allocates it on demand
Signed-off-by: Junwei Zhang
[...]
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
On 06/26/2018 04:35 PM, Michel Dänzer wrote:
On 2018-06-26 10:28 AM, Zhang, Jerry (Junwei) wrote:
On 06/26/2018 03:46 PM, Michel Dänzer wrote:
On 2018-06-26 08:00 AM, Junwei Zhang wrote:
It could be got by amdgpu_bo_gpu_offset() if need
Signed-off-by: Junwei Zhang
[...]
@@ -931,7 +928,6
On 06/25/2018 05:07 PM, Michel Dänzer wrote:
From: Michel Dänzer
Without this, there could not be enough slots, which could trigger the
BUG_ON in reservation_object_add_shared_fence.
v2:
* Jump to the error label instead of returning directly (Jerry Zhang)
Cc: sta...@vger.kernel.org
On 06/23/2018 12:42 AM, Michel Dänzer wrote:
From: Michel Dänzer
Without this, there could not be enough slots, which could trigger the
BUG_ON in reservation_object_add_shared_fence.
Cc: sta...@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106418
Reported-by:
On 06/26/2018 11:53 PM, Felix Kuehling wrote:
Comments inline [FK]
On 2018-06-26 04:35 AM, Junwei Zhang wrote:
Instead of calling gart memory on every bo pin,
allocates it on demand
v2: fix error handling
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|
On 06/27/2018 02:10 PM, Flora Cui wrote:
Change-Id: Ic0dbd693bac093e54eb95b5e547c89b64a5743b8
Signed-off-by: Flora Cui
Good catch.
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 5 -
1 file changed, 5 deletions(-)
diff --git
On 06/27/2018 05:01 PM, Koenig, Christian wrote:
Am 27.06.2018 10:29 schrieb Junwei Zhang :
Instead of calling gart memory on every bo pin,
allocates it on demand
v2: fix error handling
v3: drop the change for kfd gtt bo mapping, not needed.
Signed-off-by: Junwei Zhang
On 07/02/2018 05:23 PM, Christian König wrote:
Am 25.06.2018 um 11:07 schrieb Michel Dänzer:
From: Michel Dänzer
Without this, there could not be enough slots, which could trigger the
BUG_ON in reservation_object_add_shared_fence.
v2:
* Jump to the error label instead of returning directly
On 07/03/2018 03:36 AM, Alex Deucher wrote:
Use separate firmware path for amdgpu to avoid conflicts
with radeon on CIK parts.
Does that means firmware will be separated from radeon driver regardless of
whether they are same?
In another word, amdgpu/CIK-fw is likely to be identical to
On 07/03/2018 02:58 PM, Christian König wrote:
Am 03.07.2018 um 03:59 schrieb Zhang, Jerry (Junwei):
On 07/02/2018 05:23 PM, Christian König wrote:
Am 25.06.2018 um 11:07 schrieb Michel Dänzer:
From: Michel Dänzer
Without this, there could not be enough slots, which could trigger the
BUG_ON
On 07/03/2018 04:28 PM, Michel Dänzer wrote:
On 2018-07-03 10:12 AM, Zhang, Jerry (Junwei) wrote:
BTW, reservation_object_reserve_shared() will extend the max num as 2
times if it's not enough.
(default value is 4)
That's an implementation detail and depends on the circumstances. The
only
On 07/03/2018 04:42 PM, Christian König wrote:
Am 03.07.2018 um 10:12 schrieb Zhang, Jerry (Junwei):
On 07/03/2018 02:58 PM, Christian König wrote:
Am 03.07.2018 um 03:59 schrieb Zhang, Jerry (Junwei):
On 07/02/2018 05:23 PM, Christian König wrote:
[SNIP
On 05/01/2018 09:34 PM, Tom St Denis wrote:
Hi all,
I've noticed that on the tip of drm-next vcn playback of video is broken (see
dmesg below). I've bisected it to this commit
It may be fixed here as a common issue.
* https://patchwork.freedesktop.org/patch/218909/
Jerry
[root@raven
Hi Tom,
Sound you get the code from freedesktop rather than the internal drm-next.
Unfortunately freedesktop looks delay to sync the code from internal drm-next.
That's the gap it happened as issue in the test.
Hi Alex,
Is that a issue for code syncing between freedesktop and internal
Hi Tom,
It was landed in the latest drm-next, like
* 964933a 2018-04-27 10:26:09 +0800 drm/amdgpu/uvd7: add
emit_reg_write_reg_wait ring callback
Did you test with that included?
Please try to get the latest drm-next, if not.
They look the same issue from the log.
Jerry
On 05/02/2018
Hi Tom,
Do you mean you cannot find the patch from gerrit/amd-staging-dkms-next either?
I do find it.
the tip of gerrit/amd-staging-drm-next is
* bb54e82 2018-04-30 12:17:07 -0400 drm/amdgpu: Switch to interruptable wait
to recover from ring hang.
while the tip of freedesktop is
*
Hi Tom,
Ha, got your meaning.
Please check it with the latest drm-next from gerrit tomorrow.
Jerry
On 05/02/2018 09:41 AM, StDenis, Tom wrote:
Hi Jerry,
Like I said it's (now well) past EOD (meaning my workstation is powered off) so
I'll have to check tomorrow. But I do pull from gerrit
but the problem is there is a table for both decode and
encode. That patch that is already on drm-next only adds the callback for
encode.
My patch adds the callback for decode as well. :-)
Cheers,
Tom
On 05/01/2018 09:44 PM, Zhang, Jerry (Junwei) wrote:
Hi Tom,
Ha, got your meaning
On 04/24/2018 03:35 PM, Chunming Zhou wrote:
Change-Id: Ia3e57dbacff05f32b6c02e29aeadabd36f08028e
Signed-off-by: Chunming Zhou
Reviewed-by: Junwei Zhang
some trivial comments.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 75
On 04/24/2018 03:35 PM, Chunming Zhou wrote:
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM.
In some case, the BO on GTT could be evicted but the parent did not. This may
cause the shadow BO not be put in the evict list and could not be invalidate
correctly.
On 04/26/2018 10:18 AM, Alex Deucher wrote:
From: Leo Liu
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
On 07/04/2018 04:06 AM, Sonny Jiang wrote:
Signed-off-by: Sonny Jiang
Acked-by: Junwei Zhang
---
Documentation/gpu/amdgpu.rst| 7 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 222 +++-
2 files changed, 222 insertions(+), 7 deletions(-)
diff
On 01/11/2018 10:50 AM, Chunming Zhou wrote:
Could I how to verify this is valid fix?
For now, check if there is no vm fault or any other side effect when loading
amdgpu with ngg=1.
Later development will be implemented with OGL team together.
Jerry
Regards,
David Zhou
On 2018年01月11日
Please ignore this one, a minor update is coming.
Sorry for annoyance.
Jerry
On 01/11/2018 09:44 AM, Junwei Zhang wrote:
v2: fix register access
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++
1 file changed, 6 insertions(+), 4
On 01/10/2018 04:57 PM, Christian König wrote:
Am 10.01.2018 um 09:18 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
Just a typo in commit log:
admgpu -> amdgpu
Jerry
On 02/03/2018 01:34 AM, Marek Olšák wrote:
From: Marek Olšák
---
amdgpu/amdgpu.h | 21 +
amdgpu/amdgpu_device.c | 14 ++
amdgpu/amdgpu_internal.h | 1 +
3 files changed, 36
On 06/19/2018 03:04 PM, Christian König wrote:
We need a commit message, something like "Avoid confusing the GART with the GTT
domain.".
Yeah, will add such kind of info.
Am 19.06.2018 um 06:41 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
---
On 06/19/2018 08:57 PM, Christian König wrote:
Always validating the VM PTs takes to much time. Only always validate
the per VM BOs for now.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
1 file changed, 1 insertion(+), 1
On 08/02/2018 06:09 PM, Christian König wrote:
Am 02.08.2018 um 07:50 schrieb Zhang, Jerry (Junwei):
On 08/01/2018 07:31 PM, Christian König wrote:
Start to use the scheduler load balancing for userspace SDMA
command submissions.
In this case, each SDMA could load all SDMA(instances) rqs
On 08/02/2018 10:04 PM, Christian König wrote:
The kernel handles are dense and the kernel always tries to use the
lowest free id. Use this to implement a more efficient handle table
by using a resizeable array instead of a hash.
Signed-off-by: Christian König
---
amdgpu/Makefile.sources |
On 08/02/2018 10:55 PM, Michel Dänzer wrote:
On 2018-08-02 04:04 PM, Christian König wrote:
This way we can always find a BO structure by its handle.
Signed-off-by: Christian König
Typo in the shortlog: should be "lookup" instead of "lockup".
Also, this patch should really be after patch
On 07/31/2018 09:49 AM, Zhou, David(ChunMing) wrote:
Typo, excepted -> expected
-Original Message-
From: amd-gfx On Behalf Of Zhou,
David(ChunMing)
Sent: Tuesday, July 31, 2018 9:41 AM
To: Koenig, Christian ; Zhang, Jerry
; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 1/2]
On 07/26/2018 07:07 PM, Christian König wrote:
Am 26.07.2018 um 12:02 schrieb Junwei Zhang:
pass the evict flag instead of hard code
Signed-off-by: Junwei Zhang
I can't come up with a reason why we shouldn't do this, but please test
suspend/resume with this change just to be extra sure.
On 07/26/2018 04:29 AM, Bas Nieuwenhuizen wrote:
Every set_pages_array_wb call resulted in cross-core
interrupts and TLB flushes. Merge more of them for
less overhead.
This reduces the time needed to free a 1.6 GiB GTT WC
buffer as part of Vulkan CTS from ~2 sec to < 0.25 sec.
(Allocation
On 07/30/2018 06:47 PM, Christian König wrote:
Am 30.07.2018 um 12:02 schrieb Junwei Zhang:
From: Chunming Zhou
v2: get original gem handle from gobj
v3: update find bo data structure as union(in, out)
simply some code logic
Do we now have an open source user for this, so that we can
On 07/31/2018 03:03 PM, Christian König wrote:
Am 31.07.2018 um 08:58 schrieb Zhang, Jerry (Junwei):
On 07/30/2018 06:47 PM, Christian König wrote:
Am 30.07.2018 um 12:02 schrieb Junwei Zhang:
From: Chunming Zhou
v2: get original gem handle from gobj
v3: update find bo data structure
On 07/31/2018 04:13 PM, Christian König wrote:
Am 31.07.2018 um 10:05 schrieb Zhang, Jerry (Junwei):
On 07/31/2018 03:03 PM, Christian König wrote:
Am 31.07.2018 um 08:58 schrieb Zhang, Jerry (Junwei):
On 07/30/2018 06:47 PM, Christian König wrote:
Am 30.07.2018 um 12:02 schrieb Junwei Zhang
On 07/31/2018 04:52 PM, Christian König wrote:
Am 31.07.2018 um 09:51 schrieb Huang Rui:
On Mon, Jul 30, 2018 at 04:51:59PM +0200, Christian König wrote:
Instead of having extra handling just create an empty bo_list when no
handle is provided.
Reviewed-by: Huang Rui
In which case, when the
On 07/12/2018 02:36 PM, Nayan Deshmukh wrote:
Signed-off-by: Nayan Deshmukh
---
drivers/gpu/drm/scheduler/gpu_scheduler.c | 3 +++
include/drm/gpu_scheduler.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c
On 08/02/2018 02:08 PM, Nayan Deshmukh wrote:
On Thu, Aug 2, 2018 at 11:29 AM Zhang, Jerry (Junwei) mailto:jerry.zh...@amd.com>> wrote:
On 08/02/2018 01:50 PM, Nayan Deshmukh wrote:
>
>
> On Thu, Aug 2, 2018 at 10:31 AM Zhang, Jerry (Junwei) mailto:jerr
On 08/01/2018 07:31 PM, Christian König wrote:
Start to use the scheduler load balancing for userspace SDMA
command submissions.
In this case, each SDMA could load all SDMA(instances) rqs, and UMD will not
specify a ring id.
If so, we may abstract a set of rings for each type of IP,
On 08/02/2018 01:50 PM, Nayan Deshmukh wrote:
On Thu, Aug 2, 2018 at 10:31 AM Zhang, Jerry (Junwei) mailto:jerry.zh...@amd.com>> wrote:
On 07/12/2018 02:36 PM, Nayan Deshmukh wrote:
> Signed-off-by: Nayan Deshmukh mailto:nayan26deshm...@gmail.com>>
> ---
&
On 08/02/2018 08:00 AM, Marek Olšák wrote:
On Wed, Aug 1, 2018 at 2:29 PM, Christian König
wrote:
Am 01.08.2018 um 19:59 schrieb Marek Olšák:
On Wed, Aug 1, 2018 at 1:52 PM, Christian König
wrote:
Am 01.08.2018 um 19:39 schrieb Marek Olšák:
On Wed, Aug 1, 2018 at 2:32 AM, Christian
On 07/31/2018 05:26 PM, Huang Rui wrote:
On Tue, Jul 31, 2018 at 05:00:46PM +0800, Koenig, Christian wrote:
Am 31.07.2018 um 11:09 schrieb Huang Rui:
On Tue, Jul 31, 2018 at 10:52:06AM +0200, Christian König wrote:
Am 31.07.2018 um 09:51 schrieb Huang Rui:
On Mon, Jul 30, 2018 at 04:51:59PM
On 07/31/2018 05:04 PM, Christian König wrote:
Am 31.07.2018 um 10:58 schrieb Zhang, Jerry (Junwei):
On 07/31/2018 04:13 PM, Christian König wrote:
Am 31.07.2018 um 10:05 schrieb Zhang, Jerry (Junwei):
On 07/31/2018 03:03 PM, Christian König wrote:
Am 31.07.2018 um 08:58 schrieb Zhang, Jerry
On 08/03/2018 07:34 PM, Christian König wrote:
We have so few devices that just walking a linked list is probably
faster.
Signed-off-by: Christian König
Series is
Reviewed-and-Tested-by: Junwei Zhang
---
amdgpu/amdgpu_device.c | 49
On 08/09/2018 03:40 PM, Yu, Qiang wrote:
Comments inline.
Regards,
Qiang
From: amd-gfx on behalf of Junwei Zhang
Sent: Thursday, August 9, 2018 11:19 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jerry; Koenig, Christian
Subject: [PATCH libdrm]
On 08/08/2018 04:51 PM, Christian König wrote:
Am 08.08.2018 um 10:43 schrieb zhoucm1:
On 2018年08月08日 14:48, Christian König wrote:
Am 08.08.2018 um 06:23 schrieb zhoucm1:
On 2018年08月08日 12:08, Junwei Zhang wrote:
Userspace needs to know if the user memory is from BO or malloc.
v2:
On 08/08/2018 02:51 PM, Christian König wrote:
Am 08.08.2018 um 06:08 schrieb Junwei Zhang:
a helper function to create and initialize amdgpu bo
Can the new function be also used to initialize a BO structure during import?
Yeah, that's what I'm going to talk a bit more in this patch.
On 08/08/2018 02:48 PM, Christian König wrote:
Am 08.08.2018 um 06:23 schrieb zhoucm1:
On 2018年08月08日 12:08, Junwei Zhang wrote:
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu.h| 23
On 08/15/2018 07:25 PM, Christian König wrote:
Stupid me, max_key must always be larger than key.
Signed-off-by: Christian König
Good catch
Reviewed-by: Junwei Zhang
---
amdgpu/handle_table.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/amdgpu/handle_table.c
On 08/13/2018 06:14 PM, Christian König wrote:
Am 13.08.2018 um 12:06 schrieb Junwei Zhang:
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and free flink bo in
On 08/13/2018 06:16 PM, Christian König wrote:
Am 13.08.2018 um 11:58 schrieb Huang Rui:
From: Christian König
Add bulk move pos to store the pointer of first and last buffer object.
The list in between will be bulk moved on lru list.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
On 08/13/2018 05:58 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end
On 08/14/2018 04:26 PM, Christian König wrote:
Am 14.08.2018 um 05:00 schrieb Junwei Zhang:
Fix potential memory leak when handle flink bo in bo import.
Free the flink bo after bo import and in error handling.
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König for the series.
I
On 08/14/2018 05:58 PM, Michel Dänzer wrote:
From: Michel Dänzer
Arithmetic using void* pointers isn't defined by the C standard, only as
a GCC extension. Avoids compiler warnings:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:554:48: warning:
On 08/14/2018 05:58 PM, Michel Dänzer wrote:
From: Michel Dänzer
The compiler points out that an int doesn't work as intended if
dev->bo_handles.max_key > INT_MAX:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:550:16: warning: comparison of
On 08/03/2018 07:34 PM, Christian König wrote:
The kernel handles are dense and the kernel always tries to use the
lowest free id. Use this to implement a more efficient handle table
by using a resizeable array instead of a hash.
v2: add handle_table_fini function, extra key checks,
fix
On 08/07/2018 05:33 PM, Christian König wrote:
Am 07.08.2018 um 10:28 schrieb Zhang, Jerry (Junwei):
On 08/07/2018 04:20 PM, Christian König wrote:
Well NAK, that wasn't the intention of putting all BOs into the handle table.
You should still use the kernel implementation.
I thought we have
On 08/07/2018 04:20 PM, Christian König wrote:
Well NAK, that wasn't the intention of putting all BOs into the handle table.
You should still use the kernel implementation.
I thought we have discussed that in below mail thread. any gap?
[PATCH 1/2] drm/amdgpu: return bo itself if userptr is
On 08/07/2018 05:59 PM, Christian König wrote:
Am 07.08.2018 um 11:52 schrieb Zhang, Jerry (Junwei):
On 08/07/2018 05:33 PM, Christian König wrote:
Am 07.08.2018 um 10:28 schrieb Zhang, Jerry (Junwei):
On 08/07/2018 04:20 PM, Christian König wrote:
Well NAK, that wasn't the intention
On 08/07/2018 03:51 PM, zhoucm1 wrote:
On 2018年08月07日 15:26, Junwei Zhang wrote:
When create bo from user memory, add it to handle table
for future query.
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
On 08/10/2018 10:20 PM, Christian König wrote:
Am 10.08.2018 um 07:05 schrieb Junwei Zhang:
the flink bo is used to export
Why should we do this? That makes no sense, this way we would create a memory
leak.
Get the thought from bo_import code, but neglected the detail of
On 08/10/2018 10:21 PM, Christian König wrote:
Well NAK, that is intentionally kept local to the amdgpu_ttm.c file.
This way we can make sure that we don't accidentally leak the structure
somewhere else.
Thanks to explain that.
I thought those were left in the file accidentally.
Then fine to
On 08/13/2018 11:03 AM, Zhang, Jerry (Junwei) wrote:
On 08/10/2018 10:20 PM, Christian König wrote:
Am 10.08.2018 um 07:05 schrieb Junwei Zhang:
the flink bo is used to export
Why should we do this? That makes no sense, this way we would create a memory
leak.
Get the thought from
On 08/13/2018 04:29 PM, Christian König wrote:
Am 13.08.2018 um 08:43 schrieb Zhang, Jerry (Junwei):
On 08/13/2018 11:03 AM, Zhang, Jerry (Junwei) wrote:
On 08/10/2018 10:20 PM, Christian König wrote:
Am 10.08.2018 um 07:05 schrieb Junwei Zhang:
the flink bo is used to export
Why should we
On 08/20/2018 11:39 AM, Yintian Tao wrote:
Repeat enable dpm under pass-through because there is no actually
hardware-fini and real power-off when guest vm shutdown or reboot.
Otherwise, under pass-through it will be failed to populate populate
duplicate "populate"
and upload SCLK MCLK DPM
On 08/22/2018 05:25 AM, Felix Kuehling wrote:
Set the VM size based on system memory size between the ASIC-specific
limits given by min_vm_size and max_bits. GFXv9 GPUs will keep their
default VM size of 256TB (48 bit). Only older GPUs will adjust VM size
depending on system memory size.
This
On 08/22/2018 05:23 AM, Andrey Grodzovsky wrote:
Problem:
When executing echo 1 > /sys/class/drm/card0/device/remove kasan warning
as bellow and page fault happen because adev->gart.pages already freed by the
time amdgpu_gart_unbind is called.
BUG: KASAN: user-memory-access in
On 08/22/2018 04:33 PM, Huang Rui wrote:
On Wed, Aug 22, 2018 at 04:07:20PM +0800, Zhang, Jerry wrote:
On 08/22/2018 03:52 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle
On 08/22/2018 04:38 PM, Huang Rui wrote:
On Wed, Aug 22, 2018 at 04:33:30PM +0800, Huang Rui wrote:
On Wed, Aug 22, 2018 at 04:07:20PM +0800, Zhang, Jerry wrote:
On 08/22/2018 03:52 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
On 08/22/2018 03:52 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end
On 08/22/2018 11:05 PM, Christian König wrote:
Add a helper function to figure them out only once.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 --
1 file changed, 28 insertions(+), 33 deletions(-)
diff
On 08/23/2018 06:25 AM, Felix Kuehling wrote:
Hi all,
Oded has offered to make me co-maintainer of KFD, as he's super busy at
work and less responsive than he used to be.
At the same time we're about to send out the first patches to merge KFD
and AMDGPU into a single kernel module.
With that
On 08/22/2018 11:05 PM, Christian König wrote:
Add the necessary handling.
Signed-off-by: Christian König
Looks going to use GTT for page table.
What kind of scenario to use that?
could it be replaced by CPU updating page table in system memory?
Regards,
Jerry
---
On 08/23/2018 03:46 AM, Alex Deucher wrote:
On Wed, Aug 22, 2018 at 11:05 AM Christian König
wrote:
Just another leftover from radeon.
I can't remember exactly what chip this was for. Are you sure this
isn't still required for SI or something like that?
FYI.
Some projects still use SI
Patch 2 ~ 6 are
Reviewed-by: Junwei Zhang
Jerry
On 08/22/2018 11:05 PM, Christian König wrote:
Preparation for following changes. This validates the root PD twice,
but the overhead of that should be minimal.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8
On 08/22/2018 11:05 PM, Christian König wrote:
Add a helper to get the root PD address and remove the workarounds from
the GMC9 code for that.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +-
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