into component directory
- Fix 3dlut size for Fastloading on DCN401
- Fix write to non-existent reg on DCN401
- Remove USBC check for DCN32
- Remove unused code for some dc files
- Disable AC/DC codepath when unnecessary
- Create dcn401_clk_mgr struct
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers
From: Duncan Ma
[WHY]
DPIA boot option is set by VBIOS. It gets
overwritten when driver loads DMU.
[HOW]
Read PreOS boot options and determine if
dpia is enabled.
Reviewed-by: Ovidiu Bunea
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
tect the call to
get_max_flickerless_instant_vtotal_increase
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Ethan Bitnun
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +
.../gpu/drm/amd/display/dc/core/dc_stream.c | 64 +--
.../gpu/drm/amd/displa
From: Dillon Varone
[WHY & HOW]
Refactor complex code into manageable functions. This also cleans up
some updating logics.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h| 8 +-
.../dc/clk_mgr/dc
HW, DCN IP,
SI and SW driver agrees that we can reduce I2C speed to 95kHz to address
the I2C spped fluctuation in DCN401.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Chris Park
---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 4 ++--
1 file changed, 2
a DCN401 get_enc_caps function to allow the support for DSC slice count
higher than 4.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c| 412 ++
1 file changed, 39 insertions(+), 373 deletions(-)
diff --git
From: Alvin Lee
[WHAT & HOW]
Fast updates can consist of some stream updates as well (i.e., out_csc).
In these cases we should not offload the flip to FW as we can only
offload address only updates to FW.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers
From: George Shen
[WHY]
UHBR13.5 support is optional, even if UHBR20 is supported by the device.
If source supports max UHBR13.5 while sink, cable and LTTPR support
UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off
From: Daniel Miess
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/dccg/d
From: Sung Joon Kim
[WHY & HOW]
To support higher link rates that sink allows, we need to make
sure driver is ready and perform correct link-training sequence.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Sung Joon Kim
---
.../gpu/drm/amd/display/dc/link/proto
is slightly different than
expected. This is usually imperceptible visually, but it impacts test
pattern CRCs for compliance test automation.
[HOW]
Update logic to use the register for adding extra left edge pixel for
YCbCr422/420 ODM cases.
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off
From: Wenjing Liu
[WHY]
We need an unified location to perform ODM slice rect calculation.
[HOW]
Add three interfaces for ODM slice rect/width calucaltion in resource.h
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c
From: Samson Tam
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types.
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Revalla Hari Krishna
[WHY]
Clean up the code that requires dccg to be in its own component.
[HOW]
Move all files under newly created dccg dir and fix the makefiles.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display
From: Adam Nelson
[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.
[HOW]
Add register write to make valid.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Adam Nelson
---
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c| 8
From: Ilya Bakoulin
DP_DSC_CNTL no longer exists on DCN401.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Ilya Bakoulin
---
.../dc/dcn401/dcn401_dio_stream_encoder.c | 20 +++
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu
From: Rodrigo Siqueira
The CONNECTOR_ID_USBC check was removed to fix a regression, but it was
re-introduced by accident. This commit drops the USBC that causes the
regressions.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32
From: Rodrigo Siqueira
Cleanup unused code in DC.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 -
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 4
3
limits
- set limits present if any clock has distinct AC and DC values from SMU
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Joshua Aberback
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 28 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 1
From: Dillon Varone
Create dcn401 specific structure to encapsulate version specific
variables.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +--
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 23
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fixes on DCN401, 3dlut and I2C
* Improvements on AC/DC, link rates, DSC and ODM slice rect and pipe
* Refactoring on code styles and unused code
Cc: Daniel Wheeler
Adam Nelson (1):
drm/amd/display: Fix 3dlut size
void needing to allocate large amounts of memory every time
we create a new DC state.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_state.c| 1 -
drivers/gpu/drm/amd/displa
calculation and drop legacy TODO
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9629bd9252b4..e17ddda8ec38 100644
From: Rodrigo Siqueira
[WHY & HOW]
This commit just adds some simple comments to help understand the
calculation of V total duration for Freesync. Also, remove a legacy TODO
comment from link service type.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/dis
From: Rodrigo Siqueira
[WHY & HOW]
If the display is null when creating an HDCP session, return a proper
error code.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_p
- Add new flag to indicate if a new frame update needed for
ABM to ramp up into steady state
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dc/dce/dmub_replay.c | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 40 +--
2 files changed, 38
From: Allen Pan
[How]
Check wheather state is NULL before releasing it.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Allen Pan
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 ++-
1 file changed, 2
generator.
2. no pending dpg pattern update for each active OPP.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 56 ++-
.../gpu/drm/amd
-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 23 +++
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 ++
.../amd/display/dc/hwss/dcn32/dcn32_init.c| 2 +-
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
that would use extra free pipes such as Dynamic
ODM/MPC Combine, MPO or SubVp. Therefore there is no longer a need to
specially handle compatibility problems with transitions among those
features as they are now transparent to the new sequence.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-o
: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Revalla Hari Krishna
[WHY & HOW]
Move all dpp files to a new dpp directory.
Reviewed-by: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/Makefile | 2 +-
drivers
From: ChunTao Tso
[WHY]
The original coasting vtotal is 2 bytes, and it need to
be amended to 4 bytes because low hz case.
[HOW]
Amend coasting vtotal from 2 bytes to 4 bytes.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
...@vger.kernel.org
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++
.../gpu/drm/amd/display/dc/core/dc_resource.c | 37 +++
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 10 +
.../gpu/drm/amd/display/dc
From: Nicholas Kazlauskas
[WHY]
To have a log of the entry/exit counters in case the system hangs to
measure stability.
[HOW]
Read them from firmware state and pass them to the prints.
Reviewed-by: Duncan Ma
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd
From: Nicholas Kazlauskas
[WHY]
To control whether idle optimizations reallowed after the first cursor
update.
[HOW]
Add checks to the conditions.
Reviewed-by: Duncan Ma
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
1
not cover accesses from external clients outside of DM/DC
like firmware or the kernel mode driver.
Reviewed-by: Duncan Ma
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 9 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
2 files
...@vger.kernel.org
Reviewed-by: Duncan Ma
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display
is per OPP so we will need to
reprogram OPP based on the new pipe topology.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 41
From: Dillon Varone
[WHY & HOW]
DPPCLK ranges should be obtained from the SMU when available.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_m
...@vger.kernel.org # 6.5.x
Cc: Tsung-hua Lin
Cc: Chris Chi
Reviewed-by: Wayne Lin
Acked-by: Alex Hung
Signed-off-by: Ryan Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm
count2 : 0, 1, 2, 3, 4,
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: ChunTao Tso
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 33
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c
()
- Allow dirty rects to be sent to dmub when abm is active
- Add debug key to allow disabling dtbclk
- Add debug prints for IPS testing
- Exit idle optimizations before HDCP execution
- Add entry and exit counters
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h
From: Anthony Koo
[WHY & HOW]
Add new counters in the shared IPS firmware state.
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub
with the
link protection thread and the rest of DM operation.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c| 10 ++
drivers/gpu/drm/amd
From: Nicholas Kazlauskas
[WHY]
To log commit states and when we transition in/out of allow and idle
states and the caller.
[HOW]
Add a new logging helper and wrap idle optimization calls to receive
the caller.
Reviewed-by: Duncan Ma
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
From: Muhammad Ahmed
[HOW]
Add debug key to allow disabling dtbclk
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2
...@vger.kernel.org
Reviewed-by: Anthony Koo
Acked-by: Alex Hung
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5211c1c0f3c0
From: Roman Li
[WHY]
Incorrect function name in function banner.
[HOW]
Correct name and brief description.
Reviewed-by: Hersen Wu
Reviewed-by: Aurabindo Pillai
Acked-by: Alex Hung
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 2 +-
1 file changed, 1
: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Sohaib Nadeem
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 6 ++
.../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
.../gpu/drm/amd/display/dc/resource
From: Xi Liu
[WHY & HOW]
DCN351 and DCN35 should use the same bounding box and IP settings.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Xi Liu
---
.../gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
From: Aurabindo Pillai
Add DML2 compilation rule in the Makefile.
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml2/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2
From: Aurabindo Pillai
[WHAT]
Add DML2 pipe and config struct forward declaration as a
preparation for DML2.
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h | 2 ++
1 file changed, 2 insertions
From: Aurabindo Pillai
[WHY & HOW]
Enable DML2 related debug config options in DM for testing purposes.
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
1 file changed, 3 insertions(+)
diff -
ario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
Signed-off-by: Swapnil Patel
---
.../display/dc/dml2/dml2_translation_helper.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on HDCP, eDP and FW idle check.
* Enhancement in debug messages
* Improvement on updates sequences
* DPP refactoring to a new directory
* Enhancements in DMUB
Cc: Daniel Wheeler
Allen Pan (1):
On 2024-01-26 09:28, Melissa Wen wrote:
Replace raw edid handling (struct edid) with the opaque EDID type
(struct drm_edid) on amdgpu_dm_connector for consistency. It may also
prevent mismatch of approaches in different parts of the driver code.
Working in progress. There are a couple of cast
Thanks for catching this.
Reviewed-by: Alex Hung
On 2024-01-13 02:11, Srinivasan Shanmugam wrote:
Return value of 'to_amdgpu_crtc' which is container_of(...) can't be
null, so it's null check 'acrtc' is dropped.
Fixing the below:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
resource checks
- Add Replay IPS register for DMUB command table
- Init link enc resources in dc_state only if res_pool presents
- Allow IPS2 during Replay
Acked-by: Alex Hung
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
reported by legacy DP as EIO.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm
on the active stream case.
Z8 will still be blocked based on stutter duration, which is likely to
be the case for most multi plane configurations.
Reviewed-by: Gabe Teeger
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dml/dcn35
From: Nicholas Kazlauskas
[Why & How]
Match DCN314's policy.
Reviewed-by: Gabe Teeger
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
1 file changed, 1 insertion(+)
diff -
lse always get called when IPS
is supported.
Further rework/redesign is needed to decide whether we need a separate
level of DM allow vs DC allow and when to attempt re-entry.
Reviewed-by: Yihan Zhu
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/
() and amdgpu_dm_set_replay_caps()
to fix the issue in the earlier commit that cause PSR and Replay
enabled at the same time.
Reviewed-by: Sun peng Li
Acked-by: Alex Hung
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++-
.../amd/display/amdgpu_dm
scenarios.
[How]
Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST
cases and filter out modes that cannot be supported with the current
timing config.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/dce/dce_audio.c
ipes and guarantees
the head pipe will have matching otg inst and pipe idx.
Reviewed-by: Gabe Teeger
Acked-by: Alex Hung
Signed-off-by: Dmytro Laktyushkin
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 36 ++-
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm
for
SKUs that have low memory bandwidth. In this case we need to
populate the optimal UCLK for each DCFCLK STA targets as the max
UCLK freq.
- Also fix a bug in DML where start_state is not assigned and used
correctly.
Reviewed-by: Samson Tam
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
From: Charlene Liu
[Why]
Keep the same as previous APU and also insert clock dump
Reviewed-by: Ovidiu Bunea
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 25 +--
.../dc/resource/dcn35/dcn35_resource.c| 2 +-
2
these pipe transitions happen
automatically and quietly when the conditions are met without any visual
impacts to the user.
Reviewed-by: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
drivers/gpu/drm/amd
From: Ovidiu Bunea
[Why]
core_mode_programming in DML2 should output watermark calculations
to locals, but it incorrectly uses mode_lib
[How]
update code to match HW DML2
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed
Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 3 +++
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu
.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 40 +--
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 5 +++
2 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc
From: Nicholas Kazlauskas
[Why]
We can experience DENTIST hangs during optimize_bandwidth or TDRs if
FIFO is toggled and hangs.
[How]
Port the DCN35 fixes to DCN314.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off
From: Charlene Liu
[Why]
When mapping resources, resources could be unavailable.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Sung joon Kim
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
From: Alvin Lee
- Introduce a new Replay mode for DMUB version 0.0.199.0
Reviewed-by: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc
cked-by: Alex Hung
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 460a8010c79f..56feee0f
tive non-eDP screens.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on DCN35 and DML2.
* Enhancements in DMUB.
* Improvements on IPS, DP and MPO and others.
Cc: Daniel Wheeler
Alvin Lee (2):
drm/amd/display: Add Replay IPS register for DMUB command table
Thanks for catching this.
Reviewed-by: Alex Hung
On 2023-12-08 02:58, Harshit Mogalapalli wrote:
'wb_info' needs to be freed on error paths or it would leak the memory.
Smatch pointed this out.
Fixes: c81e13b929df ("drm/amd/display: Hande writeback request from userspace")
into component directory
- Fix DSC not Enabled on Direct MST Sink
- Guard against invalid RPTR/WPTR being set
- Enable CM low mem power optimization
- Fix a debugfs null pointer error
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion
From: Rodrigo Siqueira
[WHAT]
Add missing HDCP ID in the message id enum.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/include/hdcp_msg_types.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h
From: Anthony Koo
[WHY & HOW]
Add new command to disable replay timing resync
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 41 +++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub
From: Krunoslav Kovac
[WHY & HOW]
PB9 bit 5 was added to signal PQ EOTF in AMD vendor specific infoframe.
This change sets it when appropriate.
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Krunoslav Kovac
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 -
: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Nicholas Susanto
---
.../amd/display/dc/dcn35/dcn35_dio_stream_encoder.c| 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers
can fit into end to end bw, mode supported
Reviewed-by: Wayne Lin
Acked-by: Alex Hung
Signed-off-by: Fangzhi Zuo
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 44 +++
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgp
Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Lewis Huang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 22 -
.../gpu/drm/amd/display/dmub/src
Liu
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 3 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 29 +++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git
for the bit to assert.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 18 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
rent secondary pipes from ODM
or MPC combine.
Reviewed-by: Alvin Lee
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 37 ++-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 12 ++
2 files changed
From: Daniel Miess
[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Daniel Miess
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 6 ++-
.../gpu/drm
From: Wenjing Liu
[WHY & HOW]
The current otg master pipe allocation logic is not optimized based
current resource context. We should try to acquire a free OTG master not
used in cur cts first to avoid unnecessary pipe switch from current
state.
Acked-by: Alex Hung
Signed-off-by: Wenjing
, OLED and etc)
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Anthony Koo
Acked-by: Alex Hung
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/dc_types.h| 1 +
drivers/gpu/drm/amd/display/dc/link/link_detection.c | 3 +++
2 files changed, 4
...@vger.kernel.org
Reviewed-by: Aurabindo Pillai
Acked-by: Alex Hung
Signed-off-by: Tianci Yin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display
From: Muhammad Ahmed
[WHY & HOW]
Add some null checks to fix an issue where 8k60
tiled display fails to light up.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/dis
-by: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Mounika Adhuri
---
drivers/gpu/drm/amd/display/Makefile | 1 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/amd/display/dc/Makefile | 5 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 +-
.../gpu
From: Fangzhi Zuo
[WHY & HOW]
For the scenario when a dsc capable MST sink device is directly
connected, it needs to use max dsc compression as the link bw constraint.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Roman Li
Acked-by: Alex Hung
Signed
...@vger.kernel.org
Reviewed-by: Hansen Dsouza
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dmub/src/dmub_srv.c| 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd
From: Yihan Zhu
[WHY & HOW]
MPC MCM low mem power optimization still causes color distortion on
first SCE enablement, only forces light sleep for it.
DPP low memory power optimization still needs this bit to save power.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed
From: Aurabindo Pillai
[WHY & HOW]
Check whether get_subvp_en() callback exists before calling it.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alex Hung
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgp
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Add missing chips for HDCP
* Add new command to disable replay timing resync
* Fix encoder disable logic
* Enable DSC Flag in MST Mode Validation
* Change the DMCUB mailbox memory location from FB to inbox
* Add
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