[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Sonny
> Jiang
> Sent: Thursday, April 25, 2024 4:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Jiang, Sonny ; Jiang, Sonny
>
> Subject: [PATCH v3] drm/amd
On 2024-04-16 10:10, Harry Wentland wrote:
On 2024-04-16 04:01, Pekka Paalanen wrote:
On Mon, 15 Apr 2024 18:33:39 -0400
Leo Li wrote:
On 2024-04-15 04:19, Pekka Paalanen wrote:
On Fri, 12 Apr 2024 16:14:28 -0400
Leo Li wrote:
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri
-509,7 +509,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device
> *adev,
> ++num_rings;
> }
> ib_start_alignment = 256;
> - ib_size_alignment = 4;
> + ib_size_alignment = 64;
We don't want these impact on previous HW if that
On 2024-04-15 04:19, Pekka Paalanen wrote:
On Fri, 12 Apr 2024 16:14:28 -0400
Leo Li wrote:
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 11:08 AM Pekka Paalanen
wrote:
On Fri, 12 Apr 2024 10:28:52 -0400
Leo Li wrote:
On 2024-04-12 04:03, Pekka Paalanen wrote
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 11:08 AM Pekka Paalanen
wrote:
On Fri, 12 Apr 2024 10:28:52 -0400
Leo Li wrote:
On 2024-04-12 04:03, Pekka Paalanen wrote:
On Thu, 11 Apr 2024 16:33:57 -0400
Leo Li wrote:
...
That begs the question of what can
On 2024-04-12 04:03, Pekka Paalanen wrote:
On Thu, 11 Apr 2024 16:33:57 -0400
Leo Li wrote:
On 2024-04-04 10:22, Marius Vlad wrote:
On Thu, Apr 04, 2024 at 09:59:03AM -0400, Harry Wentland wrote:
Hi all,
On 2024-04-04 06:24, Pekka Paalanen wrote:
On Wed, 3 Apr 2024 17:32:46 -0400
On 2024-04-04 10:22, Marius Vlad wrote:
On Thu, Apr 04, 2024 at 09:59:03AM -0400, Harry Wentland wrote:
Hi all,
On 2024-04-04 06:24, Pekka Paalanen wrote:
On Wed, 3 Apr 2024 17:32:46 -0400
Leo Li wrote:
On 2024-03-28 10:33, Pekka Paalanen wrote:
On Fri, 15 Mar 2024 13:09:56 -0400
On 2024-03-28 10:33, Pekka Paalanen wrote:
On Fri, 15 Mar 2024 13:09:56 -0400
wrote:
From: Leo Li
These patches aim to make the amdgpgu KMS driver play nicer with compositors
when building multi-plane scanout configurations. They do so by:
1. Making cursor behavior more sensible.
2
On 2024-03-28 11:52, Harry Wentland wrote:
On 2024-03-28 11:48, Robert Mader wrote:
Hi,
On 15.03.24 18:09, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: Dhume, Samir
> Sent: Friday, March 15, 2024 3:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir ; Lazar, Lijo
> ; Wan, Gavin ; Liu, Leo
> ; Deucher, Alexander
> Sub
[AMD Official Use Only - General]
> -Original Message-
> From: Dhume, Samir
> Sent: Monday, March 4, 2024 10:20 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir ; Lazar, Lijo
> ; Wan, Gavin ; Liu, Leo
> ; Deucher, Alexander
> Subject: [PATCH 3/3]
[AMD Official Use Only - General]
The series of 4 patches are:
Reviewed-by: Leo Liu
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, February 21, 2024 12:00 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Yifan ; Deucher, Alex
licitly set the flag bit in hw_init
> every time and the data is repopulated after a WGR instead of
> assuming the data can survive the WGR.
>
I think this is part of sw_init, along with loading fw. Should not be in the
hw_init. I think you probably can try to save it to a saved_bo whe
The set looks good to me. The series is:
Reviewed-by: Leo Liu
On 2023-10-16 12:54, Bokun Zhang wrote:
- In VCN 4 SRIOV code path, add code to enable RB decouple feature
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 71 +--
1 file changed
union {
> + // 12 DWords
This can be removed.
> + struct {
> + uint32_t rb_addr_lo;
> + uint32_t rb_addr_hi;
> + uint32_t rb_size;
> + uint32_t rb4_addr_lo;
> +
On 2023-10-03 11:23, Lakha, Bhawanpreet wrote:
[AMD Official Use Only - General]
Why not just set replay_feature_enabled = true; to false?
Would that be the right fix? If so, we can send out a patch
with that instead.
- Leo
there's a quick fix, we should
revert for now. It sounds like this can break existing support for
PSR/PSR SU.
Acked-by: Leo Li
- Leo
Bhawan
*From:* LIPSKI, IVAN
*Sent:* October 2, 2023 1:47 PM
*To:* amd-gfx@lists.
[AMD Official Use Only - General]
Acked-by: Leo Liu
-Original Message-
From: Wu, David
Sent: Thursday, September 21, 2023 3:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher, Alexander
; Liu, Leo
Subject: [PATCH] drm/amdgpu: not to save bo in the case of RAS
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: Sundararaju, Sathishkumar
Sent: Thursday, September 14, 2023 12:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Liu, Leo ; Sundararaju,
Sathishkumar
Subject: [PATCH
at it doesn't make sense to require
zpos to be normalized between 0 and number of planes.
Thanks,
Leo
-
if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
plane_cap &&
(plane_cap->pixel_format_support.nv12 ||
--
2.41.0
The series is:
Acked-by: Leo Liu .
On 2023-08-08 12:26, Samir Dhume wrote:
The structures are the same as v4_0 except for the
init header
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h | 37 +++
1 file changed, 37 insertions
return r;
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
@@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
drm_dev_exit(idx);
}
+ amdgpu_virt_free_mm_table(adev);
Same as above.
Reviewed-by: Leo Liu
On 2023-07-17 23:20, sguttula wrote:
This patch will enable VCN FW workaround using
DRM KEY INJECT WORKAROUND method,
which is helping in fixing the secure playback.
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message as per veera's feedback
Changes
Reviewed-by: Leo Liu
On 2023-07-17 13:27, sguttula wrote:
This patch will enable secure decode playback on VCN4_0_2
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message only enabling for VCN402
-updated the logic as per Leo's feedback
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0
Since the changes will affect multiple ASICs, if you only tested with
VCN4_0_4, please just apply the set to that HW.
Regards,
Leo
On 2023-07-16 23:15, Guttula, Suresh wrote:
Hi Leo,
There are two issues here.
This change fixing the Crash while secure playback and we see below error
= {
.type = AMDGPU_RING_TYPE_VCN_ENC,
.align_mask = 0x3f,
+ .secure_submission_supported = true,
We should set it to true with VCN4_0_4 only for now, and check either
this boolean or VCN4_0_4 with your implementation from patch 2
Regards,
Leo
.nop = VCN_ENC_CMD_NO_OP
On 2023-07-10 16:19, Liu, Leo wrote:
[AMD Official Use Only - General]
[AMD Official Use Only - General]
-Original Message-
From: Jamadar, Saleemkhan
Sent: Monday, July 10, 2023 12:54 PM
To: Jamadar, Saleemkhan ; amd-gfx@lists.freedesktop.org; Liu, Leo
; Gopalakrishnan
[AMD Official Use Only - General]
-Original Message-
From: Jamadar, Saleemkhan
Sent: Monday, July 10, 2023 12:54 PM
To: Jamadar, Saleemkhan ;
amd-gfx@lists.freedesktop.org; Liu, Leo ; Gopalakrishnan,
Veerabadhran (Veera) ; Sundararaju,
Sathishkumar
Cc: Koenig, Christian ; Rao
[AMD Official Use Only - General]
-Original Message-
From: Jamadar, Saleemkhan
Sent: Monday, July 10, 2023 4:24 AM
To: Jamadar, Saleemkhan ;
amd-gfx@lists.freedesktop.org; Liu, Leo ; Gopalakrishnan,
Veerabadhran (Veera) ; Sundararaju,
Sathishkumar
Cc: Koenig, Christian ; Rao, Srinath
It looks good to me. The series is:
Reviewed-by: Leo Liu
On 2023-06-27 00:48, Lang Yu wrote:
Replace the old ones with psp_execute_load_ip_fw_cmd_buf.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 31 -
drivers/gpu/drm/amd/amdgpu
sure that also please specify the SRIOV from your patch
subject and commit message.
Regards,
Leo
On 2023-06-30 07:38, Christian König wrote:
Am 20.06.23 um 15:29 schrieb Horace Chen:
[Why]
VCN will use some framebuffer space as its cache. It needs to
be reset when reset happens, such as FLR
: Tsung-hua (Ryan) Lin
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
---
v1->v2:
* Fix a s/dcn31/dcn314/ mixup
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c | 5 +
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h | 2 ++
drivers/gpu/drm/amd/display/dmub/
firmware.
Cc: Sean Wang
Cc: Marc Rossi
Cc: Hamza Mahfooz
Cc: Tsung-hua (Ryan) Lin
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
---
v1->v2:
* Fix a s/dcn314/dcn31/ mixup
---
drivers/gpu/drm/amd/display/amdgpu
On 6/22/23 14:25, Mario Limonciello wrote:
This reverts commit 33eec907ce0eb50a56dca621aa7310f7fa904b93.
This is no longer necessary when using newer DMUB F/W.
Cc: Sean Wang
Cc: Marc Rossi
Cc: Hamza Mahfooz
Cc: Tsung-hua (Ryan) Lin
Signed-off-by: Mario Limonciello
Reviewed-by: Leo Li
-by: Mario Limonciello
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 7c9a2b34bd05..2a66a305679a 100644
dmub->regs_dcn31 = _srv_dcn316_regs;
- else
+ } else {
dmub->regs_dcn31 = _srv_dcn31_regs;
+ }
Should these hunks be rolled into 3/4? dmub_dcn314_is_psrsu_supported is
defined there.
Thanks,
Leo
f
Reviewed-by: Leo Liu
On 2023-06-20 21:29, Emily Deng wrote:
Need to unpause dpg first, or it will hit follow error during stop dpg:
"[drm] Register(1) [regUVD_POWER_STATUS] failed to reach value 0x0001 !=
0xn"
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/
in
fill_dc_dirty_rect().
Cc: sta...@vger.kernel.org # 6.1+
Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support")
Signed-off-by: Hamza Mahfooz
Reviewed-by: Leo Li
Thanks!
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 -
1 file changed, 4 insert
?
Regards,
Leo
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Monday, June 19, 2023 6:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/vcn: Need to pause dpg before stop dpg
Need to pause dpg first, or it will hit follow error during stop
[Public]
Reviewed-by: Leo Liu
From: amd-gfx on behalf of Sonny Jiang
Sent: June 8, 2023 10:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Jiang, Sonny
Subject: [PATCH] drm/amdgpu: vcn_4_0 set instance 0 init sched score to 1
From: Sonny Jiang
Only vcn0 can
/7414
- Leo
On 2/9/23 04:27, Mikhail Gavrilov wrote:
Harry, please don't ignore me.
This issue still happens in 6.1 and 6.2
Leo you are the author of the problematic commit please don't stand aside.
Really nobody is interested in clean logs without warnings and errors?
I am 100% sure that reverting
: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
...@amd.com
Cc: Joshua Ashton
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Leo Li
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 -
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 54 +++
2 files changed, 56 insertions
[AMD Official Use Only - General]
The series are:
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: January 17, 2023 3:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/4] drm/amdgpu/nv: don't expose AV1 if VCN0
Secure part requires PSP load VCN boot sequence which is with indirect sram
mode.
Regards,
Leo
From: Alex Deucher
Sent: January 16, 2023 4:50 PM
To: Guilherme G. Piccoli
Cc: amd-gfx@lists.freedesktop.org ; Jiang, Sonny
; ker...@gpiccoli.net ; Pan, Xinhui
129.421993: amdgpu_cs:
bo_list=92ffdb4c3400, ring=0, dw=48, fences=0
Fixes: 4624459c84d7 ("drm/amdgpu: add gang submit frontend v6")
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/driver
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: January 10, 2023 5:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/vcn4: add missing encoder cap
VCN4.x supports AV1
tor_signal & SIGNAL_TYPE_EDP))
return true;
Thanks,
Leo
+ return true;
+
+ pic_height = stream->timing.v_addressable +
+ stream->timing.v_border_top + stream->timing.v_border_bottom;
+ slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
+
+
Please try the latest AMDGPU driver:
https://gitlab.freedesktop.org/agd5f/linux/-/commits/amd-staging-drm-next/
On 2022-12-07 15:54, Alex Deucher wrote:
+ Leo, Thong
On Wed, Dec 7, 2022 at 3:43 PM Mikhail Gavrilov
wrote:
On Wed, Dec 7, 2022 at 7:58 PM Alex Deucher wrote:
What GPU do you
in fill_dc_dirty_rects().
Signed-off-by: Hamza Mahfooz
Thanks for the patch, it LGTM.
Reviewed-by: Leo Li
It would be good to add an IGT case to cover combinations of MPO &
damage clip commits. Perhaps something that covers the usecase of moving
a MPO video, while desktop UI updates. We'd expect th
So that uses PSP to initialize HW.
Fixes: 0c2c02b6 (drm/amdgpu/vcn: add firmware support for dimgrey_cavefish)
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm
ise, fallback to old FFU logic.
With MPO, the damage clips are more interesting, since the entire
plane's bounding box can be moved. I wonder if that is reflected in
DRM's damage clips. Do you know if a plane bb change will be reflected
in drm_plane_get_damage_clips()?
Tha
() that are only useful for debugging PSR
(and confusing otherwise). So, we can instead limit the filling of dirty
rectangles to only when PSR is enabled.
Signed-off-by: Hamza Mahfooz
Reviewed-by: Leo Li
Thanks
---
v2: give a more concrete reason.
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7
On 2022-10-07 00:28, Shirish S wrote:
[Why]
If psr_feature_enable is set to true by default, it continues to be enabled
for non capable links.
[How]
explicitly disable the feature on links that are not capable of the same.
Signed-off-by: Shirish S
Reviewed-by: Leo Li
Thanks
On 2022-10-06 03:46, S, Shirish wrote:
On 10/6/2022 4:33 AM, Leo Li wrote:
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr feature continues to be enabled for non capable links.
Do you have more info on what
On 2022-09-28 10:53, Hamza Mahfooz wrote:
On 2022-09-28 10:49, sunpeng...@amd.com wrote:
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status' is used
On 2022-09-28 09:52, Harry Wentland wrote:
On 2022-09-27 19:13, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we
Hi August,
I've sent a fix here: https://patchwork.freedesktop.org/patch/504993/
It's not the most ideal fix, but it should address the regression. Let
me know it works for you.
Thanks!
Leo
On 2022-09-27 10:22, August Wikerfors wrote:
Hi Leo,
On 2022-09-27 00:29, Leo Li wrote:
Hi
DPCD caps
0x70su_y_granularity 4 force_psrsu_cap **X**
Thanks,
Leo
On 2022-09-23 16:26, August Wikerfors wrote:
Hi Leo,
On 2022-09-23 20:41, Leo Li wrote:
Hi August,
Can you provide a dmesg log with drm.debug=0x16 enabled in kernel
cmdline?
Log is available here:
https://nam11.safelinks.protection.outloo
hitting a
corner case. The dmesg will shed some light.
Thanks
Leo
On 2022-09-22 14:13, August Wikerfors wrote:
Hi Alex,
On 2022-09-22 15:59, Alex Deucher wrote:
On Thu, Sep 22, 2022 at 8:54 AM Thorsten Leemhuis
wrote:
Hi, this is your Linux kernel regression tracker. Top-posting for once
Reviewed-by: Leo Liu
On 2022-09-22 15:30, Ruijing Dong wrote:
update VF_RB_SETUP_FLAG, add SMU_DPM_INTERFACE_FLAG,
and corresponding change in VCN4.
Signed-off-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 8 +++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4
2
pen to use the same HW ring as legacy
encode ring, so reuse the value, and that is the whole idea.
Thanks,
Leo
Instead we should just add the comment to AMDGPU_HW_IP_VCN_ENC.
Regards,
Christian.
#define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_NUM 9
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: Dong, Ruijing
Sent: July 15, 2022 4:04 PM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liu, Leo ;
Dong, Ruijing
Subject: [PATCH v4] drm/amdgpu: add HW_IP_VCN_UNIFIED type
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: Dong, Ruijing
Sent: July 15, 2022 12:09 PM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liu, Leo ;
Dong, Ruijing
Subject: [PATCH v3] drm/amdgpu: add comments
On 2022-07-12 13:00, Alex Deucher wrote:
On Tue, Jul 12, 2022 at 12:28 PM wrote:
From: Leo Li
When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain w
(
ln_align->raw = dpcd_buf[2];
if (is_repeater(link, offset)) {
+
With this extra newline dropped,
Reviewed-by: Leo Li
Thanks!
DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
" 0x%X Lane01Status = %x\n 0x%X L
>
>> Signed-off-by: Chandan Vurdigere Nataraj
>
> Acked-by: Alex Deucher
Reviewed-by: Leo Li
>
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>> index 4027f439a5a4..c8355acd3672 100644
display: Get VCO frequency from registers")
> Signed-off-by: Nathan Chancellor
Just hit this myself, thanks for the fix!
Reviewed-by: Leo Li
> ---
> drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&g
The series are:
Acked-by: Leo Liu
On 2022-06-07 14:36, Ruijing Dong wrote:
- remove multiple queue support.
- add unified queue related functions.
Signed-off-by: Ruijing Dong
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 563 +++---
1 file changed, 140 insertions
?
>
> --
I don't quite recall the details, but in FPU context, we should not malloc
since it can fault/sleep. More info here:
https://yarchive.net/comp/linux/kernel_fp.html
-
On 2022-06-07 13:58, Aurabindo Pillai wrote:
>
>
> On 2022-06-07 11:34, Leo wrote:
>>
>>
>> On 2022-06-07 05:40, Chandan Vurdigere Nataraj wrote:
>>> [Why]
>>> Getting below errors:
>>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dc
RequestChroma;
> + RequestType RequestLuma;
> + RequestType RequestChroma;
This might need a wider cleanup, enum RequestType is defined in
display_mode_enums.h and is already included in all the display_mode_vba*.c
files I've come across. Unless I'm missing something,
1_5->number_of_path; ++i)
>> ^~~~
>>
>> [How]
>> Fix compilation issues
>>
>> Signed-off-by: Chandan Vurdigere Nataraj
>
> Acked-by: Alex Deucher
Reviewed-by: Leo Li
Thanks for the fix!
>
>>
>> diff --gi
hange is really doing is identifying the panel instance to run PSR
commands on, instead of assuming that the eDP we want is always instance 0.
Will reword the message.
Thanks,
Leo
>
>> Signed-off-by: Mikita Lipski
>
> This says the author is David but it has only Mikita's sign-of
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: May 26, 2022 4:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: update VCN codec support for Yellow Carp
Supports AV1
: Thursday, May 12, 2022 7:22 AM
To: Alex Deucher
Cc: Zhang, Dingchen (David) ; amd-gfx list ; Wang, Chao-kai (Stylon) ; Li,
Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing (Lillian) ; Siqueira, Rodrigo
; Li, Roman ; Chiu, Solomon ; Zuo, Jerry ; Pillai, Aurabindo
; Lin, Wayne ; Lakha
Reviewed-by: Leo Liu
On 2022-03-30 20:59, boyuan.zh...@amd.com wrote:
From: Boyuan Zhang
For VCN FW to detect ASIC type, in order to use different mailbox registers.
V2: simplify codes and fix format issue.
V3: re-order if/else condition from the smallest version.
Signed-off-by: Boyuan
No need for encode. Encrypting uses TEE/TA to convert clear bitstream to
encrypted bitstream, and has nothing to do with VCN encode and tmz.
Regards,
Leo
On 2022-03-10 04:53, Christian König wrote:
Leo you didn't answered the question if we need TMZ for encode as well.
Regards,
Christian
On 2022-03-08 11:18, Leo Liu wrote:
On 2022-03-08 04:16, Christian König wrote:
Am 08.03.22 um 09:06 schrieb Lang Yu:
On 03/08/ , Christian König wrote:
Am 08.03.22 um 08:33 schrieb Lang Yu:
On 03/08/ , Christian König wrote:
Am 08.03.22 um 04:39 schrieb Lang Yu:
It is a hardware issue
BO
(%d)!\n", r);
+ return r;
+ }
Well, exactly that won't work.
The message structure isn't TMZ protected because otherwise the
driver won't
be able to stitch it together.
What is TMZ protected are the surfaces the message structure is
pointing to.
So what you would need to do
[AMD Official Use Only]
The series are:
Reviewed-by: Leo Liu
-Original Message-
From: Dong, Ruijing
Sent: March 2, 2022 4:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo ; Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu/vcn: Update fw shared data structure
Add fw log in fw
On 2022-02-15 16:44, Alex Deucher wrote:
From: Prike Liang
Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Reviewed-by: Leo Li
Thanks!
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu
@@ -106,6 +106,7 @@ GPIO_DCN30 = hw_translate_dcn30.o hw_factory_dcn30.o
AMD_DAL_GPIO_DCN30 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn30/,$(GPIO_DCN30))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN30)
+
Looks like we can drop this newline. Otherwise,
Reviewed-by: Leo Li
endif
On 2022-02-15 16:44, Alex Deucher wrote:
From: Prike Liang
- set DC version
- add construct/destroy dc clock management function
- register dcn interrupt handler
Signed-off-by: Prike Liang
Acked-by: Leo Li
Reviewed-by: Leo Li
Thanks.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm
uspend sends the destroy message if
there is still incomplete job, so it should be before the fini which
stops the hardware.
The series are:
Reviewed-by: Leo Liu
Signed-off-by: Qiang Ma
---
drivers/gpu/drm/radeon/cik.c | 2 +-
drivers/gpu/drm/radeon/evergreen.c | 2 +-
drivers/g
[AMD Official Use Only]
Agree.
Patch applied. Thanks for your review
-Leo
-Original Message-
From: Alex Deucher
Sent: Thursday, November 18, 2021 12:02 PM
To: Ma, Leo
Cc: Kazlauskas, Nicholas ; amd-gfx list
; Deucher, Alexander
; Choi, Nicholas ; Wentland,
Harry
Subject: Re
[Why & How]
It doesn't make sense to guard DC_LOG_DP2 by CONFIG_DRM_AMD_DCN, and
this also caused build failure for allmodconfig; So drop the guard
to fix the compile failure;
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/include/logger_types.h | 4
1 file change
[Why & How]
Dmesg errors are found on dcn3.1 during reset test, but it's not
a really failure. So reduce it to a debug print.
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
The series are:
Reviewed-by: Leo Liu
On 2021-10-19 4:10 p.m., Alex Deucher wrote:
No need to use the id variable, just use the constant
plus instance offset directly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 11 ++-
1 file changed, 2 insertions
The series are:
Reviewed-by: Leo Liu
On 2021-09-29 3:57 p.m., James Zhu wrote:
Move jpeg2 shared macro to header file
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 20
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 20
2 files
List
Cc: Arnd Bergmann
Cc: Leo Li
Cc: Alex Deucher
Cc: Christian König
Cc: Xinhui Pan
Cc: Nathan Chancellor
Cc: Guenter Roeck
Cc:l...@lists.linux.dev
---
Reviewed-by: Leo Li
in
pipe_ctx
Series LGTM,
Reviewed-by: Leo Li
Thanks!
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 55 ++--
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 158 +--
.../dc/dml/dcn20/display_rq_dlg_calc_20.h | 4
[AMD Official Use Only]
256 bytes alignment is for Video HW that is with GFX9, so it should be fine in
general.
Regards,
Leo
-Original Message-
From: Koenig, Christian
Sent: September 13, 2021 5:04 AM
To: Pan, Xinhui ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liu, Leo
On 2021-08-16 9:59 a.m., Leo Li wrote:
On 2021-08-13 3:21 p.m., Liu, Zhan wrote:
[AMD Official Use Only]
[AMD Official Use Only]
[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.
This issue has been fixed before by commit 0e4c0ae59d7e
("drm/a
.nv_entries are
under a union, with very different struct definitions.
Have you taken a look at whether the pstate latency and sr enter/exit
latency values being used after your change are sensible? It could be
that you simply needed to raise these watermarks.
Thanks,
Leo
.update
It looks good to me for the non-sriov part.
Regards,
Leo
On 2021-07-15 10:14 p.m., Zhou, Peng Ju wrote:
[AMD Official Use Only]
Hi @Liu, Leo
Can you help to review this patch?
Monk and Alex have reviewed it.
--
BW
Pengju
_device
>> *adev,
>> if (adev->uvd.harvest_config & (1 << i))
>> continue;
>> -if (adev->vcn.inst[i].ring_dec.sched.ready)
>> + if (adev->vcn.inst[i].ring_dec.sched.ready ||
>> +
_dec.sched.ready)
+ if (adev->vcn.inst[i].ring_dec.sched.ready ||
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev)))
Leo needs to take a closer look, but that looks fishy to me.
The decode is explicitly disabled with sriov cas
The series are:
Reviewed-by: Leo Liu
On 2021-05-19 12:22 p.m., James Zhu wrote:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
1 file changed, 5
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