Re: [PATCH] drm/amdgpu: Increase IH soft ring size for GFX v9.4.3

2023-09-18 Thread Christian König

Am 15.09.23 um 21:34 schrieb Philip Yang:

On GFX v9.4.3, application have random timeout failure when XNACK on,
with dmesg log "amdgpu: IH soft ring buffer overflow 0x900, 0x900",
means retry CAM has more than 256 entries. After increasing IH soft ring
to 512 entries, the test passed repeatly, no IH soft ring overflow
message.

Signed-off-by: Philip Yang 


I suggest to have a new define for those cases or maybe even completely 
drop the define and fixed values and a comment.


Christian.


---
  drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index ddfc6941f9d5..f9cde0d083fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -566,7 +566,7 @@ static int vega20_ih_sw_init(void *handle)
/* initialize ih control registers offset */
vega20_ih_init_register_offset(adev);
  
-	r = amdgpu_ih_ring_init(adev, >irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);

+   r = amdgpu_ih_ring_init(adev, >irq.ih_soft, IH_SW_RING_SIZE * 2, 
use_bus_addr);
if (r)
return r;
  




[PATCH] drm/amdgpu: Increase IH soft ring size for GFX v9.4.3

2023-09-15 Thread Philip Yang
On GFX v9.4.3, application have random timeout failure when XNACK on,
with dmesg log "amdgpu: IH soft ring buffer overflow 0x900, 0x900",
means retry CAM has more than 256 entries. After increasing IH soft ring
to 512 entries, the test passed repeatly, no IH soft ring overflow
message.

Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index ddfc6941f9d5..f9cde0d083fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -566,7 +566,7 @@ static int vega20_ih_sw_init(void *handle)
/* initialize ih control registers offset */
vega20_ih_init_register_offset(adev);
 
-   r = amdgpu_ih_ring_init(adev, >irq.ih_soft, IH_SW_RING_SIZE, 
use_bus_addr);
+   r = amdgpu_ih_ring_init(adev, >irq.ih_soft, IH_SW_RING_SIZE * 2, 
use_bus_addr);
if (r)
return r;
 
-- 
2.35.1