Am 21.11.2017 um 19:56 schrieb Alex Deucher:
Using the cached values has less latency for bare metal and
prevents reading back bogus values if the engine is powergated.
This was implemented for VI and SI, but somehow CIK got missed.
Signed-off-by: Alex Deucher
Using the cached values has less latency for bare metal and
prevents reading back bogus values if the engine is powergated.
This was implemented for VI and SI, but somehow CIK got missed.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik.c | 111