[PATCH 1/3] drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
Forgot to add vce pg support via smu for Kaveri/Mullins.
Fixes: 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
to set_powergating_by_smu")
v2: refine patch descriptions suggested by Michel
Tested-by: Michel Dänzer
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 41 +++--
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 3f57f64..a713c8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -66,7 +66,6 @@ static int kv_set_thermal_temperature_range(struct
amdgpu_device *adev,
static int kv_init_fps_limits(struct amdgpu_device *adev);
static void kv_dpm_powergate_uvd(void *handle, bool gate);
-static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
@@ -1374,6 +1373,8 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
static void kv_dpm_disable(struct amdgpu_device *adev)
{
+ struct kv_power_info *pi = kv_get_pi(adev);
+
amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
@@ -1387,7 +1388,8 @@ static void kv_dpm_disable(struct amdgpu_device *adev)
/* powerup blocks */
kv_dpm_powergate_acp(adev, false);
kv_dpm_powergate_samu(adev, false);
- kv_dpm_powergate_vce(adev, false);
+ if (pi->caps_vce_pg) /* power on the VCE block */
+ amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
kv_dpm_powergate_uvd(adev, false);
kv_enable_smc_cac(adev, false);
@@ -1551,7 +1553,6 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
int ret;
if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
- kv_dpm_powergate_vce(adev, false);
if (pi->caps_stable_p_state)
pi->vce_boot_level = table->count - 1;
else
@@ -1573,7 +1574,6 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
kv_enable_vce_dpm(adev, true);
} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk
> 0) {
kv_enable_vce_dpm(adev, false);
- kv_dpm_powergate_vce(adev, true);
}
return 0;
@@ -1702,24 +1702,32 @@ static void kv_dpm_powergate_uvd(void *handle, bool
gate)
}
}
-static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
+static void kv_dpm_powergate_vce(void *handle, bool gate)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
-
- if (pi->vce_power_gated == gate)
- return;
+ int ret;
pi->vce_power_gated = gate;
- if (!pi->caps_vce_pg)
- return;
-
- if (gate)
- amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
- else
- amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
+ if (gate) {
+ /* stop the VCE block */
+ ret = amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCE,
+AMD_PG_STATE_GATE);
+ kv_enable_vce_dpm(adev, false);
+ if (pi->caps_vce_pg) /* power off the VCE block */
+ amdgpu_kv_notify_message_to_smu(adev,
PPSMC_MSG_VCEPowerOFF);
+ } else {
+ if (pi->caps_vce_pg) /* power on the VCE block */
+ amdgpu_kv_notify_message_to_smu(adev,
PPSMC_MSG_VCEPowerON);
+ kv_enable_vce_dpm(adev, true);
+ /* re-init the VCE block */
+ ret = amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCE,
+
AMD_PG_STATE_UNGATE);
+ }
}
+
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
{
struct kv_power_info *pi = kv_get_pi(adev);
@@ -3313,6 +3321,9 @@ static int kv_set_powergating_by_smu(void *handle,
case AMD_IP_BLOCK_TYPE_UVD:
kv_dpm_powergate_uvd(handle, gate);
break;
+ case AMD_IP_BLOCK_TYPE_VCE:
+ kv_dpm_powergate_vce(handle, gate);
+ break;
default:
break;
}
--
1.9.1
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Re: [PATCH 1/3] drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
On 2018-08-23 2:59 p.m., Zhu, Rex wrote:
>> From: Michel Dänzer
>> On 2018-08-23 11:24 a.m., Rex Zhu wrote:
>>> Forgot to add vce pg support via smu for Kaveri/Mullins.
>>>
>>> Regresstion issue caused by
>>> 'commit 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
>> to
>>> set_powergating_by_smu")'
>>
>> You can replace this paragraph with
>>
>> Fixes: 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
>> to set_powergating_by_smu")
>>
>>
>> This patch fixes the VCE ring (and also IB) test on this laptop, thanks!
>>
>> Unfortunately though, there's still an oops if I let the amdkfd driver load
>> together with amdgpu (no issue when loading amdkfd manually later), see
>> the attached kernel.log excerpt. This is also a regression in the
>> 4.19 drm tree changes. It might be a separate issue, but TBH I don't feel
>> like
>> another day or two bisecting right now. :)
>
> Thanks Michel, I will check the oops issue tomorrow.
FWIW, it does seem related: I re-tested the commit before 561a5c83eadd,
the oops doesn't happen there. But it does happen with only this patch
on top of 561a5c83eadd.
I suspect https://bugs.freedesktop.org/107595 could similarly be at
least triggered by this change (I'm not using DC yet on this laptop).
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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RE: [PATCH 1/3] drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
> -Original Message-
> From: Michel Dänzer
> Sent: Thursday, August 23, 2018 6:59 PM
> To: Zhu, Rex
> Cc: amd-gfx@lists.freedesktop.org; Kuehling, Felix
>
> Subject: Re: [PATCH 1/3] drm/amdgpu: Fix vce initialize failed on
> Kaveri/Mullins
>
> On 2018-08-23 11:24 a.m., Rex Zhu wrote:
> > Forgot to add vce pg support via smu for Kaveri/Mullins.
> >
> > Regresstion issue caused by
> > 'commit 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
> to
> > set_powergating_by_smu")'
>
> You can replace this paragraph with
>
> Fixes: 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
> to set_powergating_by_smu")
>
>
> This patch fixes the VCE ring (and also IB) test on this laptop, thanks!
>
> Unfortunately though, there's still an oops if I let the amdkfd driver load
> together with amdgpu (no issue when loading amdkfd manually later), see
> the attached kernel.log excerpt. This is also a regression in the
> 4.19 drm tree changes. It might be a separate issue, but TBH I don't feel like
> another day or two bisecting right now. :)
Thanks Michel, I will check the oops issue tomorrow.
Regards
Rex
>
> Anyway, this series is
>
> Tested-by: Michel Dänzer
>
>
> --
> Earthling Michel Dänzer | http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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Re: [PATCH 1/3] drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
On 2018-08-23 11:24 a.m., Rex Zhu wrote:
> Forgot to add vce pg support via smu for Kaveri/Mullins.
>
> Regresstion issue caused by
> 'commit 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
> to set_powergating_by_smu")'
You can replace this paragraph with
Fixes: 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
to set_powergating_by_smu")
This patch fixes the VCE ring (and also IB) test on this laptop, thanks!
Unfortunately though, there's still an oops if I let the amdkfd driver
load together with amdgpu (no issue when loading amdkfd manually later),
see the attached kernel.log excerpt. This is also a regression in the
4.19 drm tree changes. It might be a separate issue, but TBH I don't
feel like another day or two bisecting right now. :)
Anyway, this series is
Tested-by: Michel Dänzer
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
Aug 23 12:25:30 thor kernel: [ 200.456163] [drm] amdgpu kernel modesetting enabled.
Aug 23 12:25:30 thor kernel: [ 200.465731] Parsing CRAT table with 1 nodes
Aug 23 12:25:30 thor kernel: [ 200.465741] Creating topology SYSFS entries
Aug 23 12:25:30 thor kernel: [ 200.465786] Topology: Add APU node [0x0:0x0]
Aug 23 12:25:30 thor kernel: [ 200.465789] Finished initializing topology
Aug 23 12:25:30 thor kernel: [ 200.465853] kfd kfd: Initialized module
Aug 23 12:25:30 thor kernel: [ 200.466288] checking generic (c000 30) vs hw (c000 1000)
Aug 23 12:25:30 thor kernel: [ 200.466296] fb: switching to amdgpudrmfb from EFI VGA
Aug 23 12:25:30 thor kernel: [ 200.466418] Console: switching to colour dummy device 80x25
Aug 23 12:25:30 thor kernel: [ 200.467646] [drm] initializing kernel modesetting (KAVERI 0x1002:0x130A 0x103C:0x2234 0x00).
Aug 23 12:25:30 thor kernel: [ 200.468031] [drm] register mmio base: 0xD680
Aug 23 12:25:30 thor kernel: [ 200.468035] [drm] register mmio size: 262144
Aug 23 12:25:30 thor kernel: [ 200.468058] [drm] add ip block number 0
Aug 23 12:25:30 thor kernel: [ 200.468062] [drm] add ip block number 1
Aug 23 12:25:30 thor kernel: [ 200.468064] [drm] add ip block number 2
Aug 23 12:25:30 thor kernel: [ 200.468067] [drm] add ip block number 3
Aug 23 12:25:30 thor kernel: [ 200.468071] [drm] add ip block number 4
Aug 23 12:25:30 thor kernel: [ 200.468074] [drm] add ip block number 5
Aug 23 12:25:30 thor kernel: [ 200.468077] [drm] add ip block number 6
Aug 23 12:25:30 thor kernel: [ 200.468080] [drm] add ip block number 7
Aug 23 12:25:30 thor kernel: [ 200.468082] [drm] add ip block number 8
Aug 23 12:25:30 thor kernel: [ 200.501755] [drm] BIOS signature incorrect 0 0
Aug 23 12:25:30 thor kernel: [ 200.501804] resource sanity check: requesting [mem 0x000c-0x000d], which spans more than PCI Bus :00 [mem 0x000c-0x000c3fff window]
Aug 23 12:25:30 thor kernel: [ 200.501812] caller pci_map_rom+0x58/0xe0 mapping multiple BARs
Aug 23 12:25:30 thor kernel: [ 200.503187] ATOM BIOS: BR45464.001
Aug 23 12:25:30 thor kernel: [ 200.503219] [drm] GPU posting now...
Aug 23 12:25:31 thor kernel: [ 200.966309] [drm] vm size is 64 GB, 2 levels, block size is 10-bit, fragment size is 9-bit
Aug 23 12:25:31 thor kernel: [ 200.966329] amdgpu :00:01.0: VRAM: 1024M 0x00F4 - 0x00F43FFF (1024M used)
Aug 23 12:25:31 thor kernel: [ 200.966333] amdgpu :00:01.0: GART: 1024M 0x - 0x3FFF
Aug 23 12:25:31 thor kernel: [ 200.966352] [drm] Detected VRAM RAM=1024M, BAR=1024M
Aug 23 12:25:31 thor kernel: [ 200.966354] [drm] RAM width 128bits UNKNOWN
Aug 23 12:25:31 thor kernel: [ 200.966695] [TTM] Zone kernel: Available graphics memory: 3568742 kiB
Aug 23 12:25:31 thor kernel: [ 200.966702] [TTM] Zone dma32: Available graphics memory: 2097152 kiB
Aug 23 12:25:31 thor kernel: [ 200.966705] [TTM] Initializing pool allocator
Aug 23 12:25:31 thor kernel: [ 200.966714] [TTM] Initializing DMA pool allocator
Aug 23 12:25:31 thor kernel: [ 200.966799] [drm] amdgpu: 1024M of VRAM memory ready
Aug 23 12:25:31 thor kernel: [ 200.966803] [drm] amdgpu: 3072M of GTT memory ready.
Aug 23 12:25:31 thor kernel: [ 200.966842] [drm] GART: num cpu pages 262144, num gpu pages 262144
Aug 23 12:25:31 thor kernel: [ 200.967622] [drm] PCIE GART of 1024M enabled (table at 0x00F4).
Aug 23 12:25:31 thor kernel: [ 200.967771] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
Aug 23 12:25:31 thor kernel: [ 200.967774] [drm] Driver supports precise vblank timestamp query.
Aug 23 12:25:31 thor kernel: [ 200.967803] [drm] Internal thermal controller without fan control
Aug 23 12:25:31 thor kernel: [ 200.967806] [drm] amdgpu: dpm initialized
Aug 23 12:25:31 thor kernel: [ 200.969641] [drm] amdgpu atom DIG backlight initialized
Aug 23 12:25:31 thor kernel: [ 200.969644] [drm] AMDGPU Display Connectors
Aug 23
[PATCH 1/3] drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
Forgot to add vce pg support via smu for Kaveri/Mullins.
Regresstion issue caused by
'commit 561a5c83eadd ("drm/amd/pp: Unify powergate_uvd/vce/mmhub
to set_powergating_by_smu")'
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 41 +++--
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 3f57f64..a713c8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -66,7 +66,6 @@ static int kv_set_thermal_temperature_range(struct
amdgpu_device *adev,
static int kv_init_fps_limits(struct amdgpu_device *adev);
static void kv_dpm_powergate_uvd(void *handle, bool gate);
-static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
@@ -1374,6 +1373,8 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
static void kv_dpm_disable(struct amdgpu_device *adev)
{
+ struct kv_power_info *pi = kv_get_pi(adev);
+
amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
@@ -1387,7 +1388,8 @@ static void kv_dpm_disable(struct amdgpu_device *adev)
/* powerup blocks */
kv_dpm_powergate_acp(adev, false);
kv_dpm_powergate_samu(adev, false);
- kv_dpm_powergate_vce(adev, false);
+ if (pi->caps_vce_pg) /* power on the VCE block */
+ amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
kv_dpm_powergate_uvd(adev, false);
kv_enable_smc_cac(adev, false);
@@ -1551,7 +1553,6 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
int ret;
if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
- kv_dpm_powergate_vce(adev, false);
if (pi->caps_stable_p_state)
pi->vce_boot_level = table->count - 1;
else
@@ -1573,7 +1574,6 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
kv_enable_vce_dpm(adev, true);
} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk
> 0) {
kv_enable_vce_dpm(adev, false);
- kv_dpm_powergate_vce(adev, true);
}
return 0;
@@ -1702,24 +1702,32 @@ static void kv_dpm_powergate_uvd(void *handle, bool
gate)
}
}
-static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
+static void kv_dpm_powergate_vce(void *handle, bool gate)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
-
- if (pi->vce_power_gated == gate)
- return;
+ int ret;
pi->vce_power_gated = gate;
- if (!pi->caps_vce_pg)
- return;
-
- if (gate)
- amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
- else
- amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
+ if (gate) {
+ /* stop the VCE block */
+ ret = amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCE,
+AMD_PG_STATE_GATE);
+ kv_enable_vce_dpm(adev, false);
+ if (pi->caps_vce_pg) /* power off the VCE block */
+ amdgpu_kv_notify_message_to_smu(adev,
PPSMC_MSG_VCEPowerOFF);
+ } else {
+ if (pi->caps_vce_pg) /* power on the VCE block */
+ amdgpu_kv_notify_message_to_smu(adev,
PPSMC_MSG_VCEPowerON);
+ kv_enable_vce_dpm(adev, true);
+ /* re-init the VCE block */
+ ret = amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCE,
+
AMD_PG_STATE_UNGATE);
+ }
}
+
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
{
struct kv_power_info *pi = kv_get_pi(adev);
@@ -3313,6 +3321,9 @@ static int kv_set_powergating_by_smu(void *handle,
case AMD_IP_BLOCK_TYPE_UVD:
kv_dpm_powergate_uvd(handle, gate);
break;
+ case AMD_IP_BLOCK_TYPE_VCE:
+ kv_dpm_powergate_vce(handle, gate);
+ break;
default:
break;
}
--
1.9.1
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