From: Noah Abradjian <noah.abradj...@amd.com>
[Why]
There is one opp per pipe. For certain RN parts, the fourth pipe is disabled,
so there is no opp for it.
res_cap->num_opp is hardcoded to 4, so if we use that to iterate over opps we
will crash.
[How]
Use the pipe_count value instead, which is not hardcoded and so will have the
correct number.
Signed-off-by: Noah Abradjian <noah.abradj...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 32878a65bdd7..cafbd08f1cf2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1357,7 +1357,7 @@ static void dcn20_update_dchubp_dpp(
// MPCC inst is equal to pipe index in practice
int mpcc_inst = pipe_ctx->pipe_idx;
int opp_inst;
- int opp_count = dc->res_pool->res_cap->num_opp;
+ int opp_count = dc->res_pool->pipe_count;
for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
if
(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
--
2.24.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
