From: Dillon Varone <dillon.var...@amd.com>

[WHY&HOW]
Add support for programming dp dto via dccg.

Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Stylon Wang <stylon.w...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h          | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index ed8936405dfa..75cf4ab8ae3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -34,6 +34,7 @@
 
 #include "dce_clock_source.h"
 #include "clk_mgr.h"
+#include "dccg.h"
 
 #include "reg_helper.h"
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 3e2f0f64c98c..65bb7cd05385 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode {
        DISPCLK_CHANGE_MODE_RAMPING,
 };
 
+struct dp_dto_params {
+       int otg_inst;
+       enum signal_type signal;
+       long long pixclk_hz;
+       long long refclk_hz;
+};
+
 enum pixel_rate_div {
    PIXEL_RATE_DIV_BY_1 = 0,
    PIXEL_RATE_DIV_BY_2 = 1,
@@ -182,6 +189,9 @@ struct dccg_funcs {
                        struct dccg *dccg,
                        uint32_t stream_enc_inst,
                        uint32_t link_enc_inst);
+       void (*set_dp_dto)(
+                       struct dccg *dccg,
+                       const struct dp_dto_params *params);
 };
 
 #endif //__DAL_DCCG_H__
-- 
2.42.0

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