From: Zeyu Fan <zeyu....@amd.com>
Change-Id: I621c2356319229c5e455d2fd6ccbedc4a74077ae
Signed-off-by: Zeyu Fan <zeyu....@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index cd9a371ae237..0eee135bfa54 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -160,7 +160,7 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst)
{
- if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO) {
+ if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
DP_DTO0_ENABLE, 1);
--
2.9.3
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