From: Joshua Aberback <joshua.aberb...@amd.com>
[Why]
Commit "Blank HUBP during pixel data blank for DCN30 v2"
modifies HW behaviour during blank, which might have OS
dependencies. We need to assess the impact on amdgpu_dm
and only re-enable HUBP blanking when all necessary
changes are understood.
[How]
- revert functional changes
- leave architectural changes intact
Signed-off-by: Joshua Aberback <joshua.aberb...@amd.com>
Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 27 ++-----------------
.../dc/dml/dcn30/display_mode_vba_30.c | 2 +-
2 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 6b6e92e261ef..a57e83428a77 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -809,29 +809,6 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
const struct tg_color *solid_color,
int width, int height, int offset)
{
- struct stream_resource *stream_res = &pipe_ctx->stream_res;
- struct pipe_ctx *mpcc_pipe;
-
- if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
- /* turning on DPG */
-
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp,
test_pattern, color_space,
- color_depth, solid_color, width, height, 0);
-
- /* wait for the next frame when enabling DPG */
- if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg))
-
dc->hwseq->funcs.wait_for_blank_complete(stream_res->opp);
-
- /* Blank HUBP to allow p-state during blank on all timings */
-
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
- for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
-
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
- } else {
- /* turning off DPG */
-
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
- for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
-
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
-
-
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp,
test_pattern, color_space,
- color_depth, solid_color, width, height, 0);
- }
+
pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp,
test_pattern,
+ color_space, color_depth, solid_color, width, height,
0);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 50b7d011705d..9e0ae18e71fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5558,7 +5558,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
}
}
- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0 && PrefetchMode ==
0) {
*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
} else if (((mode_lib->vba.SynchronizedVBlank == true ||
mode_lib->vba.TotalNumberOfActiveOTG == 1 ||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode ==
0)) {
*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
--
2.17.1
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