From: Leon Elazar <leon.ela...@amd.com>
This will fix the memory Input programing with MST tiled display.
This Fix should fix connectivity problems with MST tiled Display
Change-Id: I2cf36a325a44edd4198e30f9fc801208399e1a83
Signed-off-by: Leon Elazar <leon.ela...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index f90d586656ef..ec053c241901 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -92,6 +92,8 @@ struct dce_mem_input_registers {
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
--
2.9.3
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