From: Feifei Xu <feifei...@amd.com>
Signed-off-by: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Feifei Xu <feifei...@amd.com>
Acked-by: John Bridgman <john.bridg...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 ++
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3689f1d43685..6b172caa88f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -44,6 +44,8 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct
amdgpu_device *adev)
+ adev->vm_manager.vram_base_offset;
value &= 0x0000FFFFFFFFF000ULL;
value |= 0x1; /*valid bit*/
+ if (adev->gmc.zfb_size > 0)
+ value |= 0x2; /*system bit*/
WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
lower_32_bits(value));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 65aa28f14153..780a8fdb7369 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -472,6 +472,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct
amdgpu_device *adev,
if (flags & AMDGPU_VM_PAGE_WRITEABLE)
pte_flag |= AMDGPU_PTE_WRITEABLE;
+ if (adev->gmc.zfb_size > 0)
+ pte_flag |= AMDGPU_PTE_SYSTEM;
+
switch (flags & AMDGPU_VM_MTYPE_MASK) {
case AMDGPU_VM_MTYPE_DEFAULT:
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
@@ -507,6 +510,9 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev,
int level,
adev->gmc.vram_start;
BUG_ON(*addr & 0xFFFF00000000003FULL);
+ if (adev->gmc.zfb_size > 0)
+ *flags |= AMDGPU_PTE_SYSTEM;
+
if (!adev->gmc.translate_further)
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index dc0157093635..2721403f1452 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -54,6 +54,8 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device
*adev)
adev->vm_manager.vram_base_offset;
value &= 0x0000FFFFFFFFF000ULL;
value |= 0x1; /* valid bit */
+ if (adev->gmc.zfb_size > 0)
+ value |= 0x2; /* system bit*/
WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
lower_32_bits(value));
--
2.13.6
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