> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Friday, March 24, 2017 6:39 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 11/13] drm/amdgpu:fix missing programing critical registers
>
> those MC_VM registers won't be programed by VBIOS in VF
> so driver is responsible to programe them.
>
> Change-Id: I817371346d86bd5668ac80a486dadc1605d0b6ca
> Signed-off-by: Monk Liu <monk....@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +++-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 9 +++++++++
> 3 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 1ff019c..1d3c34d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -53,6 +53,15 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>
> mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
> (u32)(value >> 44));
>
> + if (amdgpu_sriov_vf(adev)) {
> + /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF,
> becuase they are VF copy registers so
> + vbios post doesn't program them, for SRIOV driver need to
> program them */
> + WREG32(SOC15_REG_OFFSET(GC, 0,
> mmMC_VM_FB_LOCATION_BASE),
> + adev->mc.vram_start >> 24);
> + WREG32(SOC15_REG_OFFSET(GC, 0,
> mmMC_VM_FB_LOCATION_TOP),
> + adev->mc.vram_end >> 24);
> + }
> +
> /* Disable AGP. */
> WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
> WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 88221bb..d841bc9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -383,7 +383,9 @@ static int gmc_v9_0_late_init(void *handle)
> static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
> struct amdgpu_mc *mc)
> {
> - u64 base = mmhub_v1_0_get_fb_location(adev);
> + u64 base = 0;
> + if (!amdgpu_sriov_vf(adev))
> + base = mmhub_v1_0_get_fb_location(adev);
> amdgpu_vram_location(adev, &adev->mc, base);
> adev->mc.gtt_base_align = 0;
> amdgpu_gtt_location(adev, mc);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index b1e0e6b..12025d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -67,6 +67,15 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>
> mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
> (u32)(value >> 44));
>
> + if (amdgpu_sriov_vf(adev)) {
> + /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF,
> becuase they are VF copy registers so
> + vbios post doesn't program them, for SRIOV driver need to
> program them */
> + WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmMC_VM_FB_LOCATION_BASE),
> + adev->mc.vram_start >> 24);
> + WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmMC_VM_FB_LOCATION_TOP),
> + adev->mc.vram_end >> 24);
> + }
> +
> /* Disable AGP. */
> WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE),
> 0);
> WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP),
> 0);
> --
> 2.7.4
>
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