[PATCH v2 05/16] drm/amd/powerplay: implement fw image related smu interface for Fiji.

Change-Id: I1bab73135461c289264b14972fbf15eb424734ee Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/Makefile |2 +- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c| 2371

[PATCH v2 08/16] drm/amd/powerplay: use smu7_hwmgr to manager tonga.

Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 4 +--- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 30 +--- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git

[PATCH v2 04/16] drm/amd/powerplay: use smu7 hwmgr to manager polaris10/11

Change-Id: Ia3dae5b7ef0889acd9479f83d5f3b8a91786f4bf Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 -- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 35 ++--

[PATCH v2 14/16] drm/amd/powerplay: implement fw related smu interface for iceland.

Change-Id: Ic5b83029c4e326ef4e02ee341ba8b1109d17328b Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- .../drm/amd/powerplay/hwmgr/iceland_powertune.h| 14 - drivers/gpu/drm/amd/powerplay/smumgr/Makefile |5 +-

[PATCH v2 11/16] drm/amd/powerplay: use smu7 common functions and data on Polars10.

Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- .../gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h | 3 +- .../gpu/drm/amd/powerplay/smumgr/polaris10_smc.c | 81 +-- .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 681

[PATCH v2 10/16] drm/amd/powerplay: use smu7 common functions and data on Tonga.

Change-Id: If9ca14557f99f3e13e17086e8c0a90c53f232631 Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c | 74 +-- .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c| 657 +

[PATCH v2 12/16] drm/amd/powerplay: use smu7 common functions and data on Fiji.

Change-Id: Ie63ee99aa515e37943aee726103260819c9e2913 Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c| 69 +-- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 605 +

[PATCH v2 13/16] drm/amd/powerplay: use smu7 common functions and data on icelannd.

Change-Id: I8144e52141f7e6a49a18be3523540a6edd898ec0 Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c| 50 +- .../drm/amd/powerplay/hwmgr/iceland_powertune.c| 6 +-

Re: [PATCH 0/3] rename file name.

This series is, Reviewed-by: Edward O'Callaghan On 09/12/2016 06:22 PM, Rex Zhu wrote: > As tonga/fiji/polaris10/11 use ppt table version 1. > so rename tonga_processtable to process_pptables_v1_0 > > > Rex Zhu (3): > drm/amd/powerplay: rename

[PATCH v2 09/16] drm/amd/powerplay: implement smu7_smumgr for asics with smu ip version 7.

Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 + drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 589

Re: [PATCH 0/3] rename file name.

Am 12.09.2016 um 10:36 schrieb Edward O'Callaghan: This series is, Reviewed-by: Edward O'Callaghan Acked-by: Christian König for the series. On 09/12/2016 06:22 PM, Rex Zhu wrote: As tonga/fiji/polaris10/11 use ppt table version 1.

Re: [PATCH v2 00/16] powerplay code refactoring.

A few coding style issues, but nothing major. Taking patch #7 as an example, but most of this applies to the rest as well: +/*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ That line looks

[PATCH 2/2] drm/amdgpu/cik: expose CB chicken bit registers via read reg interface

Useful for validating certain tests involving the CB where the chicken bit status may have an affect on the results. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 4 1 file changed, 4 insertions(+) diff --git

RE: [PATCH] drm/amdgpu: add the interface of waiting multiple fences (v3)

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Christian König > Sent: Monday, September 12, 2016 2:46 PM > To: Bas Nieuwenhuizen; Alex Deucher > Cc: Zhang, Jerry; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/amdgpu: add the

[PATCH 2/2] drm/amdgpu: return first signaled fence index in status parameter

From: "monk.liu" Return the index of the first signaled fence in the fences ioctl. This information is useful in some APIs like Vulkan. Signed-off-by: monk.liu Signed-off-by: Alex Deucher ---

Re: [PATCH] drm/amdgpu: add the interface of waiting multiple fences (v3)

Seems like this is missing the update corresponding to libdrm patch "amdgpu: cs_wait_fences now can return the first signaled fence index". Is the kernel patch for that update also available or going to be sent to the list? Yours sincerely, Bas Nieuwenhuizen On Mon, Sep 12, 2016 at 6:40 PM,

Re: [PATCH] drm/amdgpu: Avoid use-after-free

Am 12.09.2016 um 20:18 schrieb Tom St Denis: Switch to _SAFE variant of list macro to avoid use-after-free bug. Signed-off-by: Tom St Denis --- amdgpu/amdgpu_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/amdgpu/amdgpu_cs.c

[PATCH] drm/amdgpu: add the interface of waiting multiple fences (v2)

From: Junwei Zhang v2: agd: rebase and squash in all the previous optimizations and changes so everything compiles. Signed-off-by: Junwei Zhang Reviewed-by: Monk Liu Reviewed-by: Jammy Zhou ---

Re: [PATCH] drm/amdgpu: improve GTT BO alloc speed in OGL

Am 12.09.2016 um 18:44 schrieb Alex Deucher: From: "monk.liu" original we use ttm_dma path to allocate GTT bo, which is too much slower than the path of ttm_pool, in most cases. The swiotlb checks don't seem to work and we always end up in the slow path even when an IOMMU is

Re: [PATCH] drm/amdgpu: improve GTT BO alloc speed in OGL

On Mon, Sep 12, 2016 at 9:17 PM, Michel Dänzer wrote: > On 13/09/16 01:44 AM, Alex Deucher wrote: >> From: "monk.liu" >> >> original we use ttm_dma path to allocate GTT bo, which is too much >> slower than the path of ttm_pool, in most cases. >> >> The

[PATCH] drm/amdgpu: add the interface of waiting multiple fences (v3)

From: Junwei Zhang v2: agd: rebase and squash in all the previous optimizations and changes so everything compiles. v3: squash in Slava's 32bit build fix Signed-off-by: Junwei Zhang Reviewed-by: Monk Liu Reviewed-by: Jammy Zhou

[PATCH] drm/amdgpu: improve GTT BO alloc speed in OGL

From: "monk.liu" original we use ttm_dma path to allocate GTT bo, which is too much slower than the path of ttm_pool, in most cases. The swiotlb checks don't seem to work and we always end up in the slow path even when an IOMMU is available. Signed-off-by: monk.liu

Re: [PATCH] drm/amdgpu: improve GTT BO alloc speed in OGL

On 13/09/16 01:44 AM, Alex Deucher wrote: > From: "monk.liu" > > original we use ttm_dma path to allocate GTT bo, which is too much > slower than the path of ttm_pool, in most cases. > > The swiotlb checks don't seem to work and we always end up in the > slow path even when an

Re: [PATCH 5/6] drm/amdgpu: use expolicit limit fro VRAM<->GTT moves

On 13/09/16 06:05 AM, Alex Deucher wrote: > On Mon, Sep 12, 2016 at 10:39 AM, Christian König > wrote: >> From: Christian König >> >> Use an explicit limit when moving things around to >> force address space allocation. >> >> Signed-off-by:

Re: [PATCH 3/3] drm/amdgpu: add a custom GTT memory manager

Would it make sense to free the GTT address space in amdgpu_ttm_unbind? No, when amdgpu_ttm_unbind() is called the address space is about to be freed anyway. Currently any migration of VRAM to GTT would allocate GTT address space and never free that space until the BO is destroyed. But you

[PATCH 4/4] amdgpu: cs_wait_fences now can return the first signaled fence index

From: "monk.liu" Change-Id: Idf3d3bf0f2d2396a77341f97174d0a173fdd8932 Signed-off-by: monk.liu --- amdgpu/amdgpu.h| 3 ++- amdgpu/amdgpu_cs.c | 12 +--- include/drm/amdgpu_drm.h | 3 ++- tests/amdgpu/basic_tests.c | 2 +- 4

[PATCH 2/4] amdgpu: add the interface of waiting multiple fences

From: Junwei Zhang Signed-off-by: Junwei Zhang Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- amdgpu/amdgpu.h | 22 +++ amdgpu/amdgpu_cs.c | 72

[PATCH 1/4] amdgpu: add the function to get the marketing name (v2)

From: Junwei Zhang This function is used to look up the marking name for a specific board. v2: agd: Squash in subsequent updates to the table. Signed-off-by: Junwei Zhang Reviewed-by: Flora Cui --- amdgpu/amdgpu.h | 10

[PATCH 3/4] amdgpu/tests: add multi-fence test in base test

From: Junwei Zhang Signed-off-by: Junwei Zhang Reviewed-by: Jammy Zhou --- tests/amdgpu/basic_tests.c | 100 + 1 file changed, 100 insertions(+) diff --git a/tests/amdgpu/basic_tests.c

[PATCH 4/6] drm/amdgpu: use explicit GTT limit for evictions

From: Christian König This way the address space gets allocated immediately. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git

[PATCH 6/6] drm/amdgpu: add a custom GTT memory manager v2

From: Christian König Only allocate address space when we really need it. v2: fix a typo, add correct function description, stop leaking the node in the error case. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/Makefile

[PATCH 2/6] drm/amdgpu: add AMDGPU_BO_INVALID_OFFSET

From: Christian König An invalid offset to be used by custom VRAM/GGT manager when we don't have an offset for an BO. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 +

[PATCH 1/6] drm/amdgpu: validate size and offset of user fence BO

From: Christian König We need to validate the offset to make sure that we don't write after the BO. Additional to that a page should be enough and can make address space handling much easier. Signed-off-by: Christian König ---

use-after-free in libdrm

Attached image of scan-view's report. Basically the variable "sem" is free'ed but then used as sem->next in the for loop. Should use safe version of macro. Tom ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org