[PATCH] drm/amdgpu: Added more hqd debug messages v2

Dump register COMPUTE_PGM_RSRC1 and COMPUTE_PGM_RSRC2 in function kgd_hqd_dump v2: Update HQD_N_REGS (the number of registers dumped) accordingly Change-Id: I8e007f5bcc095d3283b642791860dd072dd43b1c Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

Re: [PATCH] drm/amdgpu: Added more hqd debug messages v2

On Wed, Mar 1, 2017 at 5:24 PM, ozeng wrote: > Dump register COMPUTE_PGM_RSRC1 and COMPUTE_PGM_RSRC2 > in function kgd_hqd_dump > > v2: Update HQD_N_REGS (the number of registers dumped) > accordingly > > Change-Id: I8e007f5bcc095d3283b642791860dd072dd43b1c > Signed-off-by:

Re: [PATCH 1/2] drm/amd/amdgpu: fix console deadlock if late init failed

On 01/03/17 06:35 PM, Jim Qu wrote: > Change-Id: Ia914fac083ebab39617dad046d4bb98ab1ddf0a8 > Signed-off-by: Jim Qu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git

RE: [PATCH] drm/amdgpu: Added more hqd debug messages

Hi Alex, COMPUTE_PGM* registers are per pipe per queue - each queue of each pipe has a copy of those registers. kgd_hqd_dump is called per pipe per queue. In kgd_hqd_dump, SRBM_GFX_CNTL register is set up to lock the correct pipe/queue. This is done through function acquire_queue(kgd,

RE: [PATCH] drm/amdgpu: Added more hqd debug messages v2

Sorry please ignore this code review. This went to the amd-gfx review group by mistake - the code modified are not on the upstream branch currently. Oak -Original Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: Wednesday, March 01, 2017 6:23 PM To: ozeng Cc: amd-gfx

RE: [PATCH] drm/amdgpu: Added more hqd debug messages

> -Original Message- > From: Zeng, Oak > Sent: Wednesday, March 01, 2017 5:29 PM > To: Deucher, Alexander; 'ozeng'; amd-gfx@lists.freedesktop.org > Subject: RE: [PATCH] drm/amdgpu: Added more hqd debug messages > > Hi Alex, > > COMPUTE_PGM* registers are per pipe per queue - each queue

答复: [PATCH 2/2] drm/amd/amdgpu: add atomic helper to suspend/resume functions

Hi Andrey: Yes, it is appropriate way to implement it in DC. it seems our base driver also need to be a bit change to adapt that. We encounter a custom P2 S4 issue on CI which need that fix. please go ahead , and push the change ASAP. Thanks JimQu

[PATCH 04/22] drm/amdgpu: remove duplicate definition of cik_mqd

The gfxv7 contains a slightly different version of cik_mqd called bonaire_mqd. This can introduce subtle bugs if fixes are not applied in both places. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 135 ++ 1 file

[PATCH 18/22] drm/amdgpu: add framework for HW specific priority settings v2

Add an initial framework for changing the HW priorities of rings. The framework allows requesting priority changes for the lifetime of an amdgpu_job. After the job completes the priority will decay to the next lowest priority for which a request is still valid. A new ring function set_priority()

[PATCH 10/22] drm/amdgpu: teach amdgpu how to enable interrupts for any pipe

The current implementation is hardcoded to enable ME1/PIPE0 interrupts only. This patch allows amdgpu to enable interrupts for any pipe of ME1. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 48 +--

[PATCH 16/22] drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v2

Use an LRU policy to map usermode rings to HW compute queues. Most compute clients use one queue, and usually the first queue available. This results in poor pipe/queue work distribution when multiple compute apps are running. In most cases pipe 0 queue 0 is the only queue that gets used. In

[PATCH 22/22] drm/amdgpu: workaround tonga HW bug in HQD programming sequence

Tonga based asics may experience hangs when an HQD's EOP parameters are modified. Workaround this HW issue by avoiding writes to these registers for tonga asics. Based on the following ROCm commit: 2a0fb8 - drm/amdgpu: Synchronize KFD HQD load protocol with CP scheduler From the ROCm git

[PATCH 15/22] drm/amdgpu: add a mechanism to untie user ring ids from kernel ring ids

Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's ring ids from the kernel's ring ids. The queue manager maintains a per-file descriptor map of user ring ids to amdgpu_ring pointers. Once a map is created it is permanent (this is required to maintain FIFO execution guarantees

[PATCH 20/22] drm/amdgpu: implement ring set_priority for gfx_v8 compute v2

Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over other queues on the same pipe. Multiple queues on a pipe are timesliced so this gives us full precedence over other queues. Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the wave as follows: 0x2:

[PATCH 11/22] drm/amdkfd: allow split HQD on per-queue granularity v4

Update the KGD to KFD interface to allow sharing pipes with queue granularity instead of pipe granularity. This allows for more interesting pipe/queue splits. v2: fix overflow check for res.queue_mask v3: fix shift overflow when setting res.queue_mask v4: fix comment in is_pipeline_enabled()

[PATCH 17/22] drm/amdgpu: add parameter to allocate high priority contexts v5

Add a new context creation parameter to express a global context priority. Contexts allocated with AMDGPU_CTX_PRIORITY_HIGH will receive higher priority to schedule their work than AMDGPU_CTX_PRIORITY_NORMAL (default) contexts. v2: Instead of using flags, repurpose __pad v3: Swap enum values of

[PATCH 03/22] drm/amdgpu: detect timeout error when deactivating hqd

Handle HQD deactivation timeouts instead of ignoring them. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[PATCH 02/22] drm/amdgpu: doorbell registers need only be set once v2

The CP_MEC_DOORBELL_RANGE_* and CP_PQ_STATUS.DOORBELL_ENABLE registers are not HQD specific. They only need to be set once if at least 1 pipe requested doorbell support. v2: move doorbell_enable to amdgpu_gfx instead of amdgpu_device Signed-off-by: Andres Rodriguez ---

[PATCH 21/22] drm/amdgpu: condense mqd programming sequence

The MQD structure matches the reg layout. Take advantage of this to simplify HQD programming. Note that the ACTIVE field still needs to be programmed last. Suggested-by: Felix Kuehling Signed-off-by: Andres Rodriguez ---

[PATCH 05/22] drm/amdgpu: unify MQD programming sequence for kfd and amdgpu

Use the same gfx_*_mqd_commit function for kfd and amdgpu codepaths. This removes the last duplicates of this programming sequence. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 51 ++-

[PATCH 01/22] drm/amdgpu: refactor MQD/HQD initialization

The MQD programming sequence currently exists in 3 different places. Refactor it to absorb all the duplicates. The success path remains mostly identical except for a slightly different order in the non-kiq case. This shouldn't matter if the HQD is disabled. The error handling paths have been

[PATCH 14/22] drm/amdgpu: new queue policy, take first 2 queues of each pipe

Instead of taking the first pipe and givint the rest to kfd, take the first 2 queues of each pipe. Effectively, amdgpu and amdkfd own the same number of queues. But because the queues are spread over multiple pipes the hardware will be able to better handle concurrent compute workloads. amdgpu

[PATCH 09/22] drm/amdgpu: allow split of queues with kfd at queue granularity

Previously the queue/pipe split with kfd operated with pipe granularity. This patch allows amdgpu to take ownership of an arbitrary set of queues. It also consolidates the last few magic numbers in the compute initialization process into mec_init. Signed-off-by: Andres Rodriguez

[PATCH 12/22] drm/amdgpu: remove duplicate magic constants from amdgpu_amdkfd_gfx*.c

This information is already available in adev. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 12 ++-- 2 files changed, 12 insertions(+), 12 deletions(-)

[PATCH] Add support for high priority scheduling in amdgpu v2

Updated based on feedback from last review. One commit was dropped: [PATCH 15/22] drm/amdgpu: add hw_ip member to amdgpu_ring One new commit in this version: [PATCH 19/22] drm/amdgpu: make amdgpu_job refcounted ___ amd-gfx mailing list

[PATCH 13/22] drm/amdgpu: allocate queues horizontally across pipes

Pipes provide better concurrency than queues, therefore we want to make sure that apps use queues from different pipes whenever possible. Optimize for the trivial case where an app will consume rings in order, therefore we don't want adjacent rings to belong to the same pipe. Signed-off-by:

[PATCH 08/22] drm/radeon: take ownership of pipe initialization

Take ownership of pipe initialization away from KFD. Note that hpd_eop_gpu_addr was already large enough to accomodate all pipes. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/radeon/cik.c| 27 ++- drivers/gpu/drm/radeon/radeon_kfd.c |

[PATCH 19/22] drm/amdgpu: make amdgpu_job refcounted

The job structure is shared between multiple components, gpu_scheduler and amdgpu. Make each user hold its own reference to simplify resource free-ing. This will also be useful for adding extra callbacks on job completion. Signed-off-by: Andres Rodriguez ---

[PATCH 07/22] drm/amdgpu: take ownership of per-pipe configuration

Make amdgpu the owner of all per-pipe state of the HQDs. This change will allow us to split the queues between kfd and amdgpu with a queue granularity instead of pipe granularity. This patch fixes kfd allocating an HDP_EOP region for its 3 pipes which goes unused. Signed-off-by: Andres

Re: [PATCH 19/22] drm/amdgpu: add framework for HW specific priority settings

On 2017-03-01 12:44 PM, Andres Rodriguez wrote: On 2017-03-01 10:49 AM, Alex Deucher wrote: On Wed, Mar 1, 2017 at 2:27 AM, zhoucm1 wrote: On 2017年03月01日 06:14, Andres Rodriguez wrote: Add an initial framework for changing the HW priorities of rings. The framework

Re: Add support for high priority scheduling in amdgpu

On 3/1/2017 11:14 AM, Bridgman, John wrote: In patch "drm/amdgpu: implement ring set_priority for gfx_v8 compute" can you remind me why you are only passing pipe and not queue to vi_srbm_select() ? +static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring, +

RE: [PATCH 2/2] drm/amd/amdgpu: add atomic helper to suspend/resume functions

Hi, We in DAL as part of upstream effort also implemented switch to using S3 atomic helpers - http://git.amd.com:8080/#/c/67108/ (currently AMD folks view only) please take a look It seems to me a more appropriate would be to call atomic APIs from DAL, maybe merging this change with the DAL

[PATCH 2/2] drm/amdgpu: Add a few members to support DAL atomic refactor.

From: Andrey Grodzovsky Signed-off-by: Andrey Grodzovsky Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 1 file changed, 4 insertions(+) diff --git

[PATCH 1/2] drm/amdgpu: Expose mode_config functions for DM

Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 33 + 2 files changed, 35 insertions(+), 2

Re: Add support for high priority scheduling in amdgpu

On 2017-03-01 12:13 PM, Andres Rodriguez wrote: On 3/1/2017 6:42 AM, Christian König wrote: Patches #1-#14 are Acked-by: Christian König . Patch #15: Not sure if that is a good idea or not, need to take a closer look after digging through the rest. In general

Re: [PATCH 19/22] drm/amdgpu: add framework for HW specific priority settings

On 2017-03-01 10:49 AM, Alex Deucher wrote: On Wed, Mar 1, 2017 at 2:27 AM, zhoucm1 wrote: On 2017年03月01日 06:14, Andres Rodriguez wrote: Add an initial framework for changing the HW priorities of rings. The framework allows requesting priority changes for the lifetime

Re: Add support for high priority scheduling in amdgpu

On 3/1/2017 6:42 AM, Christian König wrote: Patches #1-#14 are Acked-by: Christian König . Patch #15: Not sure if that is a good idea or not, need to take a closer look after digging through the rest. In general the HW IP is just for the IOCTL API and not for

RE: Add support for high priority scheduling in amdgpu

In patch "drm/amdgpu: implement ring set_priority for gfx_v8 compute" can you remind me why you are only passing pipe and not queue to vi_srbm_select() ? +static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring, + int priority) +{

Re: [PATCH 18/22] drm/amdgpu: add flag for high priority contexts v4

On 2017-02-28 08:13 PM, Emil Velikov wrote: Hi Andres, There's a couple of nitpicks below, but feel free to address those as follow-up. Considering they're correct of course ;-) As much as I'd like the to let future me deal with those issues, the UAPI behavior is something I'd like to get

[PATCH xf86-video-ati] Don't call radeon_cs_flush_indirect & radeon_bo_wait in drmmode_copy_fb

From: Michel Dänzer RADEONWindowExposures_oneshot takes care of it. Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/drmmode_display.c b/src/drmmode_display.c index

[PATCH 2/2] drm/amd/amdgpu: add atomic helper to suspend/resume functions

Change-Id: I7f5b4bddf1fe0538de81f2268fe80927bee09ec5 Signed-off-by: Jim Qu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 179 + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 7 +-

[PATCH 1/2] drm/amd/amdgpu: fix console deadlock if late init failed

Change-Id: Ia914fac083ebab39617dad046d4bb98ab1ddf0a8 Signed-off-by: Jim Qu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

[PATCH 0/2]

Jim Qu (2): drm/amd/amdgpu: fix console deadlock if late init failed drm/amd/amdgpu: add atomic helper to suspend/resume functions drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 182 +

答复: [PATCH] drm/amd/amdgpu: add atomit helper function into suspend/resume functions

Thanks to Michel. I have sent new patches, please help review. Thanks JimQu 发件人: Michel Dänzer 发送时间: 2017年3月1日 14:27 收件人: Qu, Jim 抄送: amd-gfx@lists.freedesktop.org 主题: Re: [PATCH] drm/amd/amdgpu: add atomit helper function into

[PATCH xf86-video-ati 1/2] Call drmmode_set_desired_modes from a WindowExposures hook

From: Michel Dänzer This is the earliest opportunity where the root window contents are guaranteed to be initialized, and prevents drmmode_set_mode_major from getting called before drmmode_set_desired_modes via RADEONUnblank -> drmmode_crtc_dpms. Also, in contrast to the

Re: Add support for high priority scheduling in amdgpu

Patches #1-#14 are Acked-by: Christian König . Patch #15: Not sure if that is a good idea or not, need to take a closer look after digging through the rest. In general the HW IP is just for the IOCTL API and not for internal use inside the driver. Patch #16:

Re: [PATCH 18/22] drm/amdgpu: add flag for high priority contexts v4

Hi David, On 1 March 2017 at 07:09, zhoucm1 wrote: >>> +ctx->priority = priority; >> >> seems not used. > > I see ctx->priority is used in following patches, so pls remove it there. > Fwiw, I don't think that's a good idea. Most places in the kernel are OK if you add

Re: [PATCH xf86-video-ati 1/2] Call drmmode_set_desired_modes from a WindowExposures hook

On Wed, Mar 1, 2017 at 5:02 AM, Michel Dänzer wrote: > From: Michel Dänzer > > This is the earliest opportunity where the root window contents are > guaranteed to be initialized, and prevents drmmode_set_mode_major from > getting called before

Re: [PATCH 05/15] drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

On 2017-02-28 08:17 PM, Michel Dänzer wrote: On 01/03/17 09:26 AM, Harry Wentland wrote: From: Jordan Lazare Gamma LUT shouldn't be used for 10-bit and above. Should instead be using prescale and bypassing input gamma. Change-Id:

Re: [PATCH 14/15] drm/amd/display: Enable warnings as errors

On 2017-02-28 08:20 PM, Emil Velikov wrote: Hi Harry, On 1 March 2017 at 00:26, Harry Wentland wrote: Change-Id: I48d38e4d0224c9f0e52055b3c4ddef8e872b3dac Signed-off-by: Harry Wentland Acked-by: Harry Wentland

Re: [PATCH 15/22] drm/amdgpu: add hw_ip member to amdgpu_ring

On Tue, Feb 28, 2017 at 5:14 PM, Andres Rodriguez wrote: > Keep track of a ring's HW IP block so we can identify it later. > I think this patch can be dropped. We already store the ring type in ring->funcs->type. We also shouldn't expose KIQ as a type to userspace. Alex

Re: [PATCH 19/22] drm/amdgpu: add framework for HW specific priority settings

On Wed, Mar 1, 2017 at 2:27 AM, zhoucm1 wrote: > > > On 2017年03月01日 06:14, Andres Rodriguez wrote: >> >> Add an initial framework for changing the HW priorities of rings. The >> framework allows requesting priority changes for the lifetime of an >> amdgpu_job. After the job

Re: [PATCH 05/15] drm/amd/display: Fix gamma colour corruption for 10 bit surfaces

On 2017-03-01 10:01 AM, Harry Wentland wrote: On 2017-02-28 08:17 PM, Michel Dänzer wrote: On 01/03/17 09:26 AM, Harry Wentland wrote: From: Jordan Lazare Gamma LUT shouldn't be used for 10-bit and above. Should instead be using prescale and bypassing input gamma.

[PATCH] drm/amdgpu: Added more hqd debug messages

Dump register COMPUTE_PGM_RSRC1 and COMPUTE_PGM_RSRC2 in function kgd_hqd_dump Change-Id: I8e007f5bcc095d3283b642791860dd072dd43b1c Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 ++ 2

Re: [PATCH] drm/amdgpu: Added more hqd debug messages

On 03/01/2017 04:28 PM, ozeng wrote: Dump register COMPUTE_PGM_RSRC1 and COMPUTE_PGM_RSRC2 in function kgd_hqd_dump Change-Id: I8e007f5bcc095d3283b642791860dd072dd43b1c Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 ++

RE: [PATCH] drm/amdgpu: Added more hqd debug messages

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of ozeng > Sent: Wednesday, March 01, 2017 4:28 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zeng, Oak > Subject: [PATCH] drm/amdgpu: Added more hqd debug messages > > Dump register