From: Christian König
Try to resize BAR0 to let CPU access all of VRAM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +
From: Christian König
This allows device drivers to request resizing their BARs.
The function only tries to reprogram the windows of the bridge directly above
the requesting device and only the BAR of the same type (usually mem, 64bit,
prefetchable). This is done to
From: Christian König
The address is 64bit, not 32bit.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Christian König
Just the defines and helper functions to read the possible sizes of a BAR and
update it's size.
See
https://pcisig.com/sites/default/files/specification_documents/ECN_Resizable-BAR_24Apr2008.pdf.
v2: provide read helper as well
Signed-off-by:
From: Christian König
Most BIOS don't enable this because of compatibility reasons.
Manually enable a 64bit BAR of 64GB size so that we have
enough room for PCI devices.
Signed-off-by: Christian König
---
arch/x86/pci/fixup.c | 53
Sorry I've hit enter to soon.
This set of patches tries to implement support for resizeable BARs
including an example of how the AMD GFX device driver can make use of it
to gain full CPU access to the VRAM on the hardware.
Patch #1 is just the second version of the basic RBAR support I've
Reviewed-by: Edward O'Callaghan
On 03/07/2017 12:54 AM, Christian König wrote:
> From: Christian König
>
> Based on commit "drm/radeon: remove useless and potentially wrong message".
>
> The size of the info printing is incorrect and the
From: Christian König
Based on commit "drm/radeon: remove useless and potentially wrong message".
The size of the info printing is incorrect and the PCI subsystems prints
the same info on boot anyway.
Signed-off-by: Christian König
---
On Mon, Mar 6, 2017 at 1:40 PM, Christian König wrote:
> From: Christian König
>
> Just the defines and helper functions to read the possible sizes of a BAR and
> update it's size.
>
> See
>
On Mon, Mar 6, 2017 at 1:40 PM, Christian König wrote:
> From: Christian König
>
> Try to resize BAR0 to let CPU access all of VRAM.
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@
On Mon, Mar 6, 2017 at 5:02 AM, Michel Dänzer wrote:
> From: Hans De Goede
>
> This fixes the xserver only seeing AMD/ATI devices supported by the amdgpu
> driver, as by the time xf86-video-ati gets a chance to probe them, the
> fd has been closed.
>
>
On Sun, Mar 5, 2017 at 10:37 PM, Rex Zhu wrote:
> Change-Id: I48a305f144f032b1b8d1ceda1653f004a56c9e77
Missing your signed-off-by. With that fixed:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 6 +++---
> 1 file
On Mon, Mar 6, 2017 at 4:33 AM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> Not used with older versions of Xorg. Fixes warning in that case:
>
> ../../src/amdgpu_kms.c:328:1: warning: ‘transform_region’ defined but not
> used [-Wunused-function]
>
On Mon, Mar 6, 2017 at 4:49 AM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This was only necessary with older versions for driving the FBO cache
> expiry mechanism.
>
> Signed-off-by: Michel Dänzer
Reviewed-by: Alex
Hi,
On 06-03-17 11:02, Michel Dänzer wrote:
From: Michel Dänzer
Preparation for the following change.
Assign pAMDGPUEnt->fd = -1 instead of 0 when we're not using the file
descriptor anymore.
Signed-off-by: Michel Dänzer
Thank you for
On Mon, Mar 6, 2017 at 1:40 PM, Christian König wrote:
> From: Christian König
>
> The address is 64bit, not 32bit.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1
Hello there,
1
[linux-4.11-rc1/drivers/gpu/drm/amd/amdgpu/vi.c:1041] ->
[linux-4.11-rc1/drivers/gpu/drm/amd/amdgpu/vi.c:1037]: (style) Same expression
on both sides of '|'.
Maybe the macro AMD_CG_SUPPORT_GFX_MGLS is used twice ?
2.
[linux-4.11-rc1/drivers/gpu/drm/amd/amdgpu/vi.c:1070] ->
On Sun, Mar 5, 2017 at 8:47 PM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This is the earliest opportunity where the root window contents are
> guaranteed to be initialized, and prevents drmmode_set_mode_major from
> getting called before
On 7 March 2017 at 00:45, Emil Velikov wrote:
> I have another ~20 patch series that builds on top ;-)
>
Correction - those are xf86-video-amdgpu ones independent of this series.
Pardon for the noise.
Emil
___
amd-gfx mailing
The MQD programming sequence currently exists in 3 different places.
Refactor it to absorb all the duplicates.
The success path remains mostly identical except for a slightly
different order in the non-kiq case. This shouldn't matter if the HQD
is disabled.
The error handling paths have been
Make amdgpu the owner of all per-pipe state of the HQDs.
This change will allow us to split the queues between kfd and amdgpu
with a queue granularity instead of pipe granularity.
This patch fixes kfd allocating an HDP_EOP region for its 3 pipes which
goes unused.
Reviewed-by: Edward
Handle HQD deactivation timeouts instead of ignoring them.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 --
Rename straggler instances of r(adeon)dev to a(mdgpu)dev
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 70
The CP_MEC_DOORBELL_RANGE_* and CP_PQ_STATUS.DOORBELL_ENABLE registers
are not HQD specific.
They only need to be set once if at least 1 pipe requested doorbell
support.
v2: move doorbell_enable to amdgpu_gfx instead of amdgpu_device
Reviewed-by: Edward O'Callaghan
Use an LRU policy to map usermode rings to HW compute queues.
Most compute clients use one queue, and usually the first queue
available. This results in poor pipe/queue work distribution when
multiple compute apps are running. In most cases pipe 0 queue 0 is
the only queue that gets used.
In
Take ownership of pipe initialization away from KFD.
Note that hpd_eop_gpu_addr was already large enough to accomodate all
pipes.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
Tonga based asics may experience hangs when an HQD's EOP parameters
are modified.
Workaround this HW issue by avoiding writes to these registers for
tonga asics.
Based on the following ROCm commit:
2a0fb8 - drm/amdgpu: Synchronize KFD HQD load protocol with CP scheduler
From the ROCm git
The MQD structure matches the reg layout. Take advantage of this to
simplify HQD programming.
Note that the ACTIVE field still needs to be programmed last.
Suggested-by: Felix Kuehling
Signed-off-by: Andres Rodriguez
---
Pipes provide better concurrency than queues, therefore we want to make
sure that apps use queues from different pipes whenever possible.
Optimize for the trivial case where an app will consume rings in order,
therefore we don't want adjacent rings to belong to the same pipe.
Reviewed-by: Edward
Add a new context creation parameter to express a global context priority.
Contexts allocated with AMDGPU_CTX_PRIORITY_HIGH will receive higher
priority to schedule their work than AMDGPU_CTX_PRIORITY_NORMAL
(default) contexts.
v2: Instead of using flags, repurpose __pad
v3: Swap enum values of
Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over
other queues on the same pipe. Multiple queues on a pipe are timesliced
so this gives us full precedence over other queues.
Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the
wave as follows:
0x2:
The current implementation is hardcoded to enable ME1/PIPE0 interrupts
only.
This patch allows amdgpu to enable interrupts for any pipe of ME1.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 48 +--
Instead of taking the first pipe and giving the rest to kfd, take the
first 2 queues of each pipe.
Effectively, amdgpu and amdkfd own the same number of queues. But
because the queues are spread over multiple pipes the hardware will be
able to better handle concurrent compute workloads.
amdgpu
Previously the queue/pipe split with kfd operated with pipe
granularity. This patch allows amdgpu to take ownership of an arbitrary
set of queues.
It also consolidates the last few magic numbers in the compute
initialization process into mec_init.
Reviewed-by: Edward O'Callaghan
Use the same gfx_*_mqd_commit function for kfd and amdgpu codepaths.
This removes the last duplicates of this programming sequence.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
On 22 January 2017 at 18:48, Emil Velikov wrote:
> All one needs is to establish if dev->fd is the flink (primary/card)
> node, rather than use DRM_IOCTL_GET_CLIENT to query the auth status.
>
> The latter is [somewhat] deprecated and incorrect. We need to know [and
>
Update the KGD to KFD interface to allow sharing pipes with queue
granularity instead of pipe granularity.
This allows for more interesting pipe/queue splits.
v2: fix overflow check for res.queue_mask
v3: fix shift overflow when setting res.queue_mask
v4: fix comment in is_pipeline_enabled()
The gfxv7 contains a slightly different version of cik_mqd called
bonaire_mqd. This can introduce subtle bugs if fixes are not applied in
both places.
Reviewed-by: Edward O'Callaghan
Acked-by: Christian König
Signed-off-by: Andres Rodriguez
Am 06.03.2017 um 08:32 schrieb Xiangliang Yu:
Because different HWs have different definition for CE & DE meta
data, follow mqd design to move the structures to vi_structs.h.
And change the prefix from amdgpu to vi as the structures is only
for VI family.
Signed-off-by: Xiangliang Yu
v2: fix merge error.
Change-Id: I68be9cf0afce98a1fdb11e32eb883bddda8e040c
Signed-off-by: Rex Zhu
Reviewed-by: Xiaojie Yuan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/atom.c | 22 --
From: Michel Dänzer
This fixes all errors down to Xorg 1.10.
One warning remains, see below. This could be silenced by casting the
return value of amdgpu_get_marketing_name to (char*), but that's ugly
and doesn't seem worth it.
../../src/amdgpu_kms.c: In function
From: Michel Dänzer
It was only added in xserver 1.15. Fixes build against older xserver.
Reported-by: Pali Rohár
(Ported from radeon commit 80cc892ee1ce54fad3cb7dd11bd9df18c359136f)
Signed-off-by: Michel Dänzer
---
From: Michel Dänzer
Looks like this snuck in accidentally.
Brings us back in line with the radeon driver, and fixes the build
against older versions of xserver which didn't have the is_gpu field
yet.
Fixes: 6bab8fabb37e ("Remove info->dri2.drm_fd and info->drmmode->fd")
From: Michel Dänzer
Not used with older versions of Xorg. Fixes warning in that case:
../../src/amdgpu_kms.c:328:1: warning: ‘transform_region’ defined but not used
[-Wunused-function]
transform_region(RegionPtr region, struct pict_f_transform *transform,
From: Michel Dänzer
This was only necessary with older versions for driving the FBO cache
expiry mechanism.
Signed-off-by: Michel Dänzer
---
src/amdgpu_kms.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/amdgpu_kms.c
From: Hans De Goede
This fixes the xserver only seeing AMD/ATI devices supported by the amdgpu
driver, as by the time xf86-video-ati gets a chance to probe them, the
fd has been closed.
This fixes e.g. Xorg not seeing the dGPU on a Lenovo Thinkpad E465 laptop
with a CARRIZO
From: Michel Dänzer
Preparation for the following change.
Assign pAMDGPUEnt->fd = -1 instead of 0 when we're not using the file
descriptor anymore.
Signed-off-by: Michel Dänzer
---
src/amdgpu_kms.c | 7 +--
src/amdgpu_probe.c | 10
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