I think something like this should fix it.
Alex
From: amd-gfx on behalf of Deucher,
Alexander
Sent: Wednesday, October 17, 2018 12:15:21 PM
To: StDenis, Tom; Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: Re: regression on RV1
IIRC, APUs do
Patch 1 and 2 are Reviewed-by: Nayan Deshmukh
On Wed, Oct 17, 2018 at 12:30 AM Grodzovsky, Andrey
wrote:
>
> Patches 1-3 Reviewed-by: Andrey Grodzovsky
>
> Patch 4 Acked-by: Andrey Grodzovsky
>
> Andrey
>
>
> On 10/16/2018 07:55 AM, Christian König wrote:
> > Make sure we always restart the
I had sent a patch to the list but yours is prettier. You can add my
Tested-By: to your patch.
Tom
On 2018-10-17 12:40 p.m., Deucher, Alexander wrote:
> I think something like this should fix it.
>
>
> Alex
>
>
>
Signed-off-by: Tom St Denis
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 46 --
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 33a62d5a4949..b7f6db39d357 100644
---
Sorry for the noise, didn't thought about the issue that this SDMA code is used
on RV as well.
Feel free to add my rb to the patch,
Christian.
Am 17.10.18 um 18:40 schrieb Deucher, Alexander:
I think something like this should fix it.
Alex
From: amd-gfx
IIRC, APUs do not have a paging queue. Only dGPUs have it.
Alex
From: amd-gfx on behalf of StDenis, Tom
Sent: Wednesday, October 17, 2018 11:54:33 AM
To: Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: regression on RV1
This commit:
commit
This commit:
commit 6cbd074831a423e0d30b386fc056d6c2c3559147 (HEAD, refs/bisect/bad)
Author: Christian König
Date: Mon Oct 8 14:38:22 2018 +0200
drm/amdgpu: activate paging queue on SDMA v4
Implement all the necessary stuff to get those extra rings working.
Signed-off-by:
On 2018年10月17日 18:24, Daniel Vetter wrote:
On Wed, Oct 17, 2018 at 11:29 AM Koenig, Christian
wrote:
Am 17.10.18 um 11:17 schrieb zhoucm1:
[SNIP]
+struct drm_syncobj_signal_pt {
+struct dma_fence_array *base;
Out of curiosity, why the pointer and not embedding? base is kinda
On 2018-10-17 4:42 p.m., Alex Deucher wrote:
> On Wed, Oct 17, 2018 at 4:16 PM Wentland, Harry
> wrote:
>>
>> On 2018-10-17 4:10 p.m., Alex Deucher wrote:
>>> On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry
>>> wrote:
On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are
Hi Dave,
Fixes for 4.20. Highlights:
- VCN DPG fixes for Picasso
- Add support for the latest vega20 vbios
- Scheduler timeout fix
- License fixes for radeon and amdgpu
- Misc other fixes
The following changes since commit ca4b869240d5810ebac6b1570ad7beffcfbac2f5:
Merge branch
On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added as branching of existing DCE8 implementation.
All your parents require a Signed-off-by. See
https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#developer-s-certificate-of-origin-1-1
Harry
> ---
>
On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> ---
> drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
> .../display/dc/bios/command_table_helper.c| 8 +
> .../display/dc/bios/command_table_helper.h| 3 +
>
On 2018-10-17 3:50 p.m., Wentland, Harry wrote:
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
>> DCE6 targets are added as branching of existing DCE8 implementation.
>
> All your parents require a Signed-off-by. See
>
On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> > ---
> > drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
> > .../display/dc/bios/command_table_helper.c| 8 +
On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
>
> NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
> only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
>
> IMPORTANT: Coding of
On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
>
> NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
> dce/dce_8_0_{d,sh_mask}.h headers were used instead of
> dce/dce_6_0_{d,sh_mask}.h
> but only as exception
On 2018-10-17 04:15 AM, Christian König wrote:
> Am 17.10.18 um 04:56 schrieb Yang, Philip:
>> Use HMM helper function hmm_vma_fault() to get physical pages backing
>> userptr and start CPU page table update track of those pages. Then use
>> hmm_vma_range_done() to check if those pages are updated
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of John Clements
> Sent: Wednesday, October 17, 2018 6:48 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: John Clements
> Subject: [PATCH] Revised PSP comments
>
> From: John Clements
>
>
VCE on Stoney seems to have problems after the first suspend/resume
cycle. Disable it before we destabilize the whole driver.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
On 2018年10月17日 16:09, Daniel Vetter wrote:
On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:
This patch is for VK_KHR_timeline_semaphore extension, semaphore is called
syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying
Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.
V2: update for mclk/pcie clock level settings also
Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0
Signed-off-by: Evan Quan
---
Am 17.10.18 um 11:17 schrieb zhoucm1:
> [SNIP]
>>> +struct drm_syncobj_signal_pt {
>>> + struct dma_fence_array *base;
>> Out of curiosity, why the pointer and not embedding? base is kinda
>> misleading for a pointer.
> Yeah, Christian doesn't like signal_pt lifecycle same as fence, so
>
On Wed, Oct 17, 2018 at 11:17 AM zhoucm1 wrote:
>
>
>
> On 2018年10月17日 16:09, Daniel Vetter wrote:
> > On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:
> >> This patch is for VK_KHR_timeline_semaphore extension, semaphore is called
> >> syncobj in kernel side:
> >> This extension
On Wed, Oct 17, 2018 at 11:29 AM Koenig, Christian
wrote:
>
> Am 17.10.18 um 11:17 schrieb zhoucm1:
> > [SNIP]
> >>> +struct drm_syncobj_signal_pt {
> >>> +struct dma_fence_array *base;
> >> Out of curiosity, why the pointer and not embedding? base is kinda
> >> misleading for a pointer.
>
On 2018年10月16日 20:54, Christian König wrote:
I've added my rb to patch #1 and pushed it to drm-misc-next.
I would really like to get an rb from other people on patch #2 before
proceeding.
Daniel, Dave and all the other usual suspects on the list what is your
opinion on this
Am 17.10.18 um 04:56 schrieb Yang, Philip:
Use HMM helper function hmm_vma_fault() to get physical pages backing
userptr and start CPU page table update track of those pages. Then use
hmm_vma_range_done() to check if those pages are updated before
amdgpu_cs_submit for gfx or before user queues
On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:
> This patch is for VK_KHR_timeline_semaphore extension, semaphore is called
> syncobj in kernel side:
> This extension introduces a new type of syncobj that has an integer payload
> identifying a point in a timeline. Such timeline
Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.
Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 5 -
From: John Clements
Revised comments in PSP SOS/Sysdriver loading sequence
Signed-off-by: John Clements
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled
(v2) Hainan is not supported, description updated accordingly
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
(v1) pre-requisite to have Kaveri and Hawaii is revert of d9fda24804
("drm/amdgpu: Don't default to DC support for Kaveri and older")
(v2) fix for bc011f9350 ("drm/amdgpu:
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
(v2) remove CHIP_HAINAN support since it does not have physical DCE6 module
add SI families except CHIP_HAINAN in load_dmcu_fw() new function
---
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c
IMPORTANT: Coding of
DCE6 targets are added replicating existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/i2caux/Makefile| 12 +
.../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
.../dc/i2caux/dce60/i2c_hw_engine_dce60.h | 54 ++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.c
Sending PATCH v2 series rebase on amd-staging-drm-next
dce/dce60/dce60_resources.c and irq/dce60/irq_service_dce60.c
are still using dce_8_0_{d,sh_mask}.h headers
dpm is used for power management, a non fatal message is generated:
[drm:dm_pp_get_static_clocks: [amdgpu]]
*ERROR* DM_PPLIB:
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c| 8 +
.../display/dc/bios/command_table_helper.h| 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
IMPORTANT: Coding of dce60_resource.c requires review to understand
if
DCE6 targets are added as branching of existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 12 +
.../display/dc/gpio/dce60/hw_factory_dce60.c | 174
.../display/dc/gpio/dce60/hw_factory_dce60.h | 32 ++
.../dc/gpio/dce60/hw_translate_dce60.c| 411
Am 17.10.18 um 04:56 schrieb Yang, Philip:
Use HMM helper function hmm_vma_fault() to get physical pages backing
userptr and start CPU page table update track of those pages. Then use
hmm_vma_range_done() to check if those pages are updated before
amdgpu_cs_submit for gfx or before user queues
+Jason as well.
On 2018年10月17日 18:22, Daniel Vetter wrote:
On Wed, Oct 17, 2018 at 11:17 AM zhoucm1 wrote:
On 2018年10月17日 16:09, Daniel Vetter wrote:
On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:
This patch is for VK_KHR_timeline_semaphore extension, semaphore is called
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Evan Quan
Sent: Wednesday, October 17, 2018 4:41:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Quan, Evan; Zhu, Rex
Subject: [PATCH] drm/amd/powerplay: error out when force clock level
Reviewed-by: Alex Deucher
From: Evan Quan
Sent: Wednesday, October 17, 2018 5:21:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex; Deucher, Alexander; Quan, Evan
Subject: [PATCH] drm/amd/powerplay: error out when force clock level under auto
dpm mode V2
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