Hi Slava,
xf86-video-amdgpu patches are submitted & reviewed as GitLab merge
requests now. Please log into your GitLab account, click the "Fork"
button on https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu ,
push the change to a new branch of your resulting personal GitLab
project, and
I'm leaving out for some days. Thanks very much for your detailed answer.
Best Regards.
Yanhua
-- --
??: "Koenig, Christian";
: 2019??9??6??(??) 7:23
??: "yanhua"<78666...@qq.com>;"amd-gfx";
: "Deucher, Alexander";
: R
Hi,
On 9/10/19 9:50 AM, Michel Dänzer wrote:
On 2019-09-07 10:32 p.m., Hans de Goede wrote:
Bail from the pci_driver probe function instead of from the drm_driver
load function.
This avoid /dev/dri/card0 temporarily getting registered and then
unregistered again, sending unwanted add / remove
Reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of
>jia...@amd.com
>Sent: Monday, September 9, 2019 6:37 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhao, Jiange
>Subject: [PATCH] drm/amdgpu: Add SRIOV mailbox backend for Navi1x
>
>From: Jiange Zhao
>
>Mimic the one
On 2019-09-10 11:36 a.m., Hans de Goede wrote:
> On 9/10/19 9:50 AM, Michel Dänzer wrote:
>> On 2019-09-07 10:32 p.m., Hans de Goede wrote:
>>> Bail from the pci_driver probe function instead of from the drm_driver
>>> load function.
>>>
>>> This avoid /dev/dri/card0 temporarily getting registered
Am 10.09.19 um 15:30 schrieb Zeng, Oak:
>
> Regards,
> Oak
>
> -Original Message-
> From: Koenig, Christian
> Sent: Monday, September 9, 2019 1:14 PM
> To: Zeng, Oak ; Kuehling, Felix ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 9/9] drm/amdgpu: add graceful VM fault handling v
except soc_bounding_box which is not integrated in discovery table yet
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_devi
From: Jiange Zhao
Mailbox functions and interrupts are only for Navi12 VF.
Register functions and irqs during initialization.
Signed-off-by: Jiange Zhao
---
drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
Set mp1 state properly for SW SMU suspend/reset routine.
Change-Id: I458d09e79bba2613bb85099938648782ff91b97a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 10 ++---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 40 +++
.../gpu/drm/amd/powerplay/i
This patch to add amdgpu_tmz structure which stores all tmz related fields.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +
2 files changed, 41 insertions(
This is especially needed for non-psp loading way.
Change-Id: I1e523168ed4892c34c8cbb66077c3f9288dd8006
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 28 ++
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerpla
From: Alex Deucher
Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel
module. Nomally, by default, it should be auto (rely on the hardware
capability).
But right now, it need to set "off" to avoid breaking other developers'
work because it's not totally completed.
Will set "auto" till
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
drivers/gpu/drm/amd/
From: Alex Deucher
Add a flag for when allocating a context to flag it as
secure. The kernel driver will use this flag to determine
whether a rendering context is secure or not so that the
engine can be transitioned between secure or unsecure
or the work can be submitted to a secure queue depend
From: Alex Deucher
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them. This is required in order
to properly access the data from the engines.
Signed-off-by: Alex Deucher
Reviewed
From: Alex Deucher
If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ bits of
PTEs that belongs that bo should be set. Then psp is able to protect the pages
of this bo to avoid the access from an "untrust" domain such as CPU.
v1: design and draft the skeletion of tmz bits se
Hi all,
These series of patches introduce a feature to support secure buffer object.
The Trusted Memory Zone (TMZ) is a method to protect the contents being written
to and read from memory. We use TMZ hardware memory protection scheme to
implement the secure buffer object support.
TMZ is the page
This patch adds tmz bit in frame control pm4 packet, and it will used in future.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nvd.h| 1 +
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
This patch is to add a helper to get corresponding buffer object with a pointer
to a struct ttm_mem_reg.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
include/drm/ttm/ttm_bo_driver.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/ttm/ttm_bo_driver.h b/in
amdgpu_ttm_tt_pte_flags will be used for updating tmz bits while the bo is
secure, so we need pass the ttm_mem_reg under a buffer object.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 ++
1 file changed, 10 insertions(+), 8 d
The is_secure flag will indicate the current conext is protected or not.
v2: while user mode asks to create a context, but if tmz is disabled, it should
return failure.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 +++
driv
While user mode submit a command with secure context, we should set the command
buffer with trusted mode.
v2: fix the null job pointer while in vmid 0 submission.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 +
drivers/gpu/drm/amd/amdgpu/am
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/dr
Add a function to check tmz capability with kernel parameter and ASIC type.
v2: use a per device tmz variable instead of global amdgpu_tmz.
v3: refine the comments for the function. (Luben)
v4: add amdgpu_tmz.c/h for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gp
Patches #1-#4, #8, #9 are Reviewed-by: Christian König
Patches #10, #11 are Acked-by: Christian König
Patches #7 and the resulting workaround in patch #13 are a clear NAK.
The ttm_mem_reg can't be used like this to get back to the ttm_bo object.
Going to reply separately on patch #14 regardi
Am 11.09.19 um 13:50 schrieb Huang, Ray:
> From: Alex Deucher
>
> If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ bits
> of
> PTEs that belongs that bo should be set. Then psp is able to protect the pages
> of this bo to avoid the access from an "untrust" domain such as CP
On 2019-09-10 3:05 p.m., Bhawanpreet Lakha wrote:
> This patch set introduces HDCP 1.4 capability to Asics starting with
> Raven(DCN 1.0).
>
> This only introduces the ability to authenticate and encrypt the link. These
> patches by themselves don't constitute a complete and compliant
> HDCP con
I like this much more, I will relocate to amdgpu_umc_process_ras_data_cb
an push.
Andrey
On 9/10/19 11:08 PM, Zhou1, Tao wrote:
> amdgpu_ras_reserve_bad_pages is only used by umc block, so another approach
> is to move it into amdgpu_umc_process_ras_data_cb.
> Anyway, either way is OK and the p
On second though this will break what about reserving bad pages when
resetting GPU for non RAS error reason such as manual reset ,S3 or ring
timeout, (amdgpu_ras_resume->amdgpu_ras_reset_gpu) so i will keep the
code as is.
Another possible issue in existing code - looks like no reservation wil
> -Original Message-
> From: Hans de Goede
> Sent: Tuesday, September 10, 2019 5:36 AM
> To: Michel Dänzer ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
>
> Cc: David Airlie ; dri-de...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org; Daniel Vetter
> Subje
Looks like the subject is wrong for this and patch 20:
s/3.4/3.2/
Will modify before merge.
Leo
On 2019-09-10 9:54 a.m., sunpeng...@amd.com wrote:
> From: Aric Cyr
>
> Signed-off-by: Aric Cyr
> Acked-by: Leo Li
> ---
> drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
> 1 file changed, 1 insertio
Hello,
I am testing latest rc8/Linus git tree on my new
Acer Nitro 5 (AN515-43-R8BF) Laptop.
The box has an Ryzen7 3750H APU+RX 560x hybrid GPU(s).
Suspending ( closing the Lid ) from tty without X up
is working fine, however with X running doing the same
does not work. The display remains black
These changes are based on Jason's latest hmm branch.
Patch 1 was previously posted here [1] but was dropped from the orginal
series. Hopefully, the tests will reduce concerns about edge conditions.
I'm sure more tests could be usefully added but I thought this was a good
starting point.
[1] https
hmm_range_fault() calls find_vma() and walk_page_range() in a loop.
This is unnecessary duplication since walk_page_range() calls find_vma()
in a loop already.
Simplify hmm_range_fault() by defining a walk_test() callback function
to filter unhandled vmas.
This also fixes a bug where hmm_range_faul
Allow hmm_range_fault() to return success (0) when the CPU pagetable
entry points to the special shared zero page.
The caller can then handle the zero page by possibly clearing device
private memory instead of DMAing a zero page.
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Guntho
Allow hmm_range_fault() to return success (0) when the range has no access
(!(vma->vm_flags & VM_READ)). The range->pfns[] array will be filled with
range->values[HMM_PFN_NONE] in this case.
This allows the caller to get a snapshot of a range without having to
lookup the vma before calling hmm_rang
Add self tests for HMM.
Signed-off-by: Ralph Campbell
---
MAINTAINERS|3 +
drivers/char/Kconfig | 11 +
drivers/char/Makefile |1 +
drivers/char/hmm_dmirror.c | 1504
include/Kbuild
From: Dhinakaran Pandiyan
Currently we restrict the number of encoders that can be linked to
a connector to 3, increase it to match the maximum number of encoders
that can be initialized(32).
To more effiently do that lets switch from an array of encoder ids to
bitmask.
v2: Fixing missed return
It's better to say "sdma engine" or just "sdma" instead of "sdma_v4".
Anyway, the patch is reviewed-by: Evan Quan
-Original Message-
From: Liang, Prike
Sent: Thursday, September 12, 2019 9:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ;
Huang, Ray ; Liu, Aaron
The sdma_v4 should be ungated when the IP resume back,
otherwise it will hang up and resume time out error.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 ++
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |
From: Jiange Zhao
In SRIOV case, SMU and powerplay are handled in HV.
VF shouldn't have control over SMU and powerplay.
Signed-off-by: Jiange Zhao
---
drivers/gpu/drm/amd/amdgpu/nv.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/
Comment inline.
Regards,
Guchun
-Original Message-
From: Grodzovsky, Andrey
Sent: Wednesday, September 11, 2019 10:41 PM
To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: Fix mutex lock from atomic context.
On second
On 2019-09-11 2:52 a.m., S, Shirish wrote:
> If CONFIG_HSA_AMD is not set, build fails:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function
> `amdgpu_device_ip_early_init':
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined reference to
> `sched_policy'
>
> Use CONFIG_HSA_AMD to
That not what I meant. Let's say you handled one bad page interrupt and as a
result have one bad page reserved. Now unrelated gfx ring timeout happens which
triggers GPU reset and VRAM loss. When you come back from reset
amdgpu_ras_reserve_bad_pages will be called but since last_reserved ==
dat
Thanks review and originally want emphasize the sequence only needed at sdma v4
case.
Thanks,
Prike
> -Original Message-
> From: Quan, Evan
> Sent: Thursday, September 12, 2019 10:20 AM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Huang, Ray
> ; Liu, Aaron
>
Series is:
Reviewed-by: Alex Deucher
On Wed, Sep 11, 2019 at 7:50 AM Quan, Evan wrote:
>
> This is especially needed for non-psp loading way.
>
> Change-Id: I1e523168ed4892c34c8cbb66077c3f9288dd8006
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 28
Reviewed-by: Emily Deng
>-Original Message-
>From: Zhao, Jiange
>Sent: Wednesday, September 11, 2019 6:25 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Nieto, David M ; Deng, Emily
>; Koenig, Christian ;
>Zhao, Jiange
>Subject: [PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox
>fun
From: Jiange Zhao
In SRIOV case, the autoload sequence is the same
as bare metal, except VF won't load TOC.
Signed-off-by: Jiange Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
Reviewed-by: Emily Deng
>-Original Message-
>From: Zhao, Jiange
>Sent: Thursday, September 12, 2019 1:22 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Nieto, David M ; Deng, Emily
>; Koenig, Christian ;
>Zhao, Jiange
>Subject: [PATCH] drm/amdgpu: Navi12 SRIOV VF doesn't load TOC
>
>From: J
define sched_policy in case CONFIG_HSA_AMD is not
enabled, with this there is no need to check for CONFIG_HSA_AMD
else where in driver code.
Suggested-by: Felix Kuehling
Signed-off-by: Shirish S
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |
On 9/12/2019 3:29 AM, Kuehling, Felix wrote:
> On 2019-09-11 2:52 a.m., S, Shirish wrote:
>> If CONFIG_HSA_AMD is not set, build fails:
>>
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function
>> `amdgpu_device_ip_early_init':
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined ref
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