Acked-by: Alex Deucher
On Wed, Oct 9, 2019 at 10:25 PM Yuan, Xiaojie wrote:
>
> Ping ...
>
> BR,
> Xiaojie
>
> From: Yuan, Xiaojie
> Sent: Wednesday, October 9, 2019 7:08 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Xiao, Jack ;
> Feng,
Hi Dave, Daniel,
Just a single fix this week for 5.4.
The following changes since commit da0c9ea146cbe92b832f1b0f694840ea8eb33cce:
Linux 5.4-rc2 (2019-10-06 14:27:30 -0700)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/linux tags/drm-fixes-5.4-2019-10-09
for
Ping ...
BR,
Xiaojie
From: Yuan, Xiaojie
Sent: Wednesday, October 9, 2019 7:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ;
Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Yuan, Xiaojie
Subject: [PATCH 1/2] drm/amd/powerplay: add
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.
Change-Id: I8397f9ccc5dec32dc86ef7635c5ed227c77e61a3
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 23 +
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 +++
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.
Change-Id: I4f2f7936a3bc6e1a32d590bc76ebfc9a5a53f9cb
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 6 ++
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++
On Tue, 2019-10-08 at 21:26 +, Mikita Lipski wrote:
>
> On 08.10.2019 12:24, Lyude Paul wrote:
> > ...
> > yikes
> > I need to apologize because I was going through my email and I realized
> > you
> > _did_ respond to me earlier regarding some of these questions, it just
> > appears
> > the
Hi Dave, Daniel,
New stuff for 5.5. There's an export of a cgroup function that
Tejun acked for merging through the drm tree. kfd uses it to handle
permissions in containers since there is only one /dev/kfd.
The following changes since commit 9a60b2990d6c2b7ab935fe0a5cc274de67d98bed:
Merge
Hi Evan,
Is there any use case for this interface?
Thanks.
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Quan,
Evan
Sent: Thursday, October 10, 2019 11:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2]
Reviewed-by: Kevin Wang
Best Regards,
Kevin
On 10/9/19 9:17 PM, Alex Deucher wrote:
> Add toggles for more power features. Helpful in debugging.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 --
> 1 file changed, 18
Hi All:
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:
The function to_amdgpu_fence() could return NULL, but callers
in this file does not check the return value but directly dereference it,
which seems potentially unsafe.
Such callers include amdgpu_fence_get_timeline_name(),
Hi,
When trying to build a Linux kernel with clang, I encountered a GPF
problem in the amdgpu module. Details of the issue can be found here:
https://github.com/ClangBuiltLinux/linux/issues/735
In short, the stack is aligned to 8 bytes while clang assumed the
stack is aligned to 16 bytes
Reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, October 9, 2019 9:17 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/swSMU/navi: add feature toggles for more things
Add toggles for more power
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: Alex Deucher
Sent: Thursday, October 10, 2019 10:33 AM
To: Yuan, Xiaojie
Cc: amd-gfx@lists.freedesktop.org ; Xiao, Jack
; Quan, Evan ; Feng, Kenneth
; Wang, Kevin(Yang) ; Zhang, Hawking
Subject: Re: [PATCH
Yes, we have to toggle DF-C state before/after programming DF Perf counter
registers. The series is to provide interface for such case.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Feng, Kenneth
Sent: 2019年10月10日 12:50
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
When index is 1, need to set compute ring timeout for sriov and passthrough.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 6 --
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 5a34d01f7f7c..44152c1f01c7 100644
---
SMU firmware has fix the bug, so remove this workaround.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
zhengbin (3):
drm/amd/display: Remove set but not used variables
'bl_pwm_cntl','pwm_period_cntl'
drm/amd/display: Remove set but not used variable 'value0'
drm/amd/display: Remove set but not used variables 'regval','speakers'
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c| 8
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c: In function
dce110_update_generic_info_packet:
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:68:11: warning:
variable regval set but not used [-Wunused-but-set-variable]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c: In function
dce110_link_encoder_update_mst_stream_allocation_table:
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c:1229:11: warning:
variable value0 set but not used
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c: In function
calculate_16_bit_backlight_from_pwm:
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c:83:11: warning: variable
bl_pwm_cntl set but not used [-Wunused-but-set-variable]
Am 08.10.19 um 21:29 schrieb Alex Deucher:
From: "Tianci.Yin"
add a generic helper function for accessing framebuffer via MMIO
Change-Id: I4baa0aa53c93a94c2eff98c6211a61f369239982
Reviewed-by: Alex Deucher
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +
On Tue, Oct 08, 2019 at 06:53:18PM +, Kuehling, Felix wrote:
> On 2019-08-29 2:05 a.m., Kenny Ho wrote:
> > drm.lgpu
> > A read-write nested-keyed file which exists on all cgroups.
> > Each entry is keyed by the DRM device's major:minor.
> >
> > lgpu stands for
Here is where you definitively set "ret" so DO NOT preinitialize it to 0,
just to avoid "pesky compiler unininitialized variable warnings"--those
are helpful to make the code more secure: a variable should be intentionally
initialized in all paths.
Rico: Still in confusion, pre-initialization can
Ok,
Thanks for your reviewing!
Rico
From: Christian K?nig
Sent: Wednesday, October 9, 2019 16:25
To: Alex Deucher ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Yin, Tianci (Rico)
Subject: Re: [PATCH 2/8] drm/amdgpu: add a generic fb accessing
Yin, Tianci (Rico) would like to recall the message, "[PATCH 7/8] drm/amdgpu:
reserve vram for memory training".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Yin, Tianci (Rico) would like to recall the message, "[PATCH 7/8] drm/amdgpu:
reserve vram for memory training".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Oh, I see, I thought we should eliminate warning, but it's a wrong idea,
actually we need it.
Thanks!
Rico
From: Christian K?nig
Sent: Wednesday, October 9, 2019 19:40
To: Yin, Tianci (Rico) ; Tuikov, Luben
; Alex Deucher ;
amd-gfx@lists.freedesktop.org
Cc:
What version of firmware has the fix? Was it recently fixed? We should check
the version if the old one may be out in the wild.
Alex
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Wednesday, October 9, 2019 7:08 AM
To: amd-gfx@lists.freedesktop.org
Cc:
Am 09.10.19 um 13:12 schrieb Yin, Tianci (Rico):
Here is where you definitively set "ret" so DO NOT preinitialize it to 0,
just to avoid "pesky compiler unininitialized variable warnings"--those
are helpful to make the code more secure: a variable should be
intentionally
initialized in all
Add toggles for more power features. Helpful in debugging.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 --
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
Hi Daniel,
Can you elaborate what you mean in more details? The goal of lgpu is
to provide the ability to subdivide a GPU device and give those slices
to different users as needed. I don't think there is anything
controversial or vendor specific here as requests for this are well
documented.
On Wed, Oct 09, 2019 at 03:53:42PM +, Kuehling, Felix wrote:
> On 2019-10-09 11:34, Daniel Vetter wrote:
> > On Wed, Oct 09, 2019 at 03:25:22PM +, Kuehling, Felix wrote:
> >> On 2019-10-09 6:31, Daniel Vetter wrote:
> >>> On Tue, Oct 08, 2019 at 06:53:18PM +, Kuehling, Felix wrote:
>
On Thu, Oct 03, 2019 at 11:08:03PM +0100, Colin Ian King wrote:
> Hi,
>
> Static analysis with Coverity has detected a potential issue with
> function validate_bksv in
> drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c with recent
> commit:
>
> commit
On 2019-10-09 6:31, Daniel Vetter wrote:
> On Tue, Oct 08, 2019 at 06:53:18PM +, Kuehling, Felix wrote:
>>
>> The description sounds reasonable to me and maps well to the CU masking
>> feature in our GPUs.
>>
>> It would also allow us to do more coarse-grained masking for example to
>>
On Wed, Oct 09, 2019 at 03:25:22PM +, Kuehling, Felix wrote:
> On 2019-10-09 6:31, Daniel Vetter wrote:
> > On Tue, Oct 08, 2019 at 06:53:18PM +, Kuehling, Felix wrote:
> >>
> >> The description sounds reasonable to me and maps well to the CU masking
> >> feature in our GPUs.
> >>
> >> It
On Fri, Sep 27, 2019 at 11:27:41AM -0400, Sean Paul wrote:
> On Thu, Sep 26, 2019 at 06:51:07PM -0400, Lyude Paul wrote:
> > This commit is seperate from the previous one to make it easier to
> > revert in the future. Basically, there's multiple userspace applications
> > that interpret
On Wed, Oct 09, 2019 at 11:08:45AM -0400, Kenny Ho wrote:
> Hi Daniel,
>
> Can you elaborate what you mean in more details? The goal of lgpu is
> to provide the ability to subdivide a GPU device and give those slices
> to different users as needed. I don't think there is anything
>
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Cc: Alex Deucher
Cc: Christian König
Cc: David (ChunMing) Zhou
Cc: amd-gfx@lists.freedesktop.org
Acked-by: Alex Deucher
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c |
On 2019-10-09 11:34, Daniel Vetter wrote:
> On Wed, Oct 09, 2019 at 03:25:22PM +, Kuehling, Felix wrote:
>> On 2019-10-09 6:31, Daniel Vetter wrote:
>>> On Tue, Oct 08, 2019 at 06:53:18PM +, Kuehling, Felix wrote:
The description sounds reasonable to me and maps well to the CU masking
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Wednesday, October 9, 2019 1:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Yuan, Xiaojie ;
Zhang, Hawking
Subject: [PATCH] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM
sdma will hang once sequence number to be polled reaches 0x1000_
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index
Hi Alex,
For now, gfxoff for navi10 is disabled by default, and I also verified on
navi14 with both GFXOFF and FW_DSTATE feature bits toggled on.
Hi Kenneth / Jack,
Could you help to confirm the firmware version?
BR,
Xiaojie
From: Deucher, Alexander
Sent:
Hey! Re: our discussion about this at XDC, I think I'm going to drop this
patch and just fix KASAN so it prints the hashed pointer as well, I'll cc you
on the patches for that as well
On Fri, 2019-09-27 at 10:25 -0400, Sean Paul wrote:
> On Tue, Sep 03, 2019 at 04:46:04PM -0400, Lyude Paul wrote:
Hi,
The reason we don't use drm_hdcp is because our policy is to do hdcp
verification using PSP/HW (onboard secure processor).
Bhawan
On 2019-10-09 12:32 p.m., Daniel Vetter wrote:
> On Thu, Oct 03, 2019 at 11:08:03PM +0100, Colin Ian King wrote:
>> Hi,
>>
>> Static analysis with Coverity has
> From: Daniel Vetter On Behalf Of Daniel Vetter
> Sent: Wednesday, October 9, 2019 11:07 AM
> On Wed, Oct 09, 2019 at 03:53:42PM +, Kuehling, Felix wrote:
> > On 2019-10-09 11:34, Daniel Vetter wrote:
> > > On Wed, Oct 09, 2019 at 03:25:22PM +, Kuehling, Felix wrote:
> > >> On 2019-10-09
This reverts commit 6f7fe9a93e6c09bf988c5059403f5f88e17e21e6.
This breaks some boards. Maybe just enable this on PPC for
now?
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205147
Signed-off-by: Alex Deucher
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/radeon/radeon_drv.c | 8
1
On Wed, Oct 9, 2019 at 8:23 PM Lakha, Bhawanpreet
wrote:
>
> Hi,
>
> The reason we don't use drm_hdcp is because our policy is to do hdcp
> verification using PSP/HW (onboard secure processor).
i915 also uses hw to auth, we still use the parts from drm_hdcp ...
Did you actually look at what's in
On Fri, 2019-09-27 at 09:52 -0400, Sean Paul wrote:
> On Tue, Sep 03, 2019 at 04:46:03PM -0400, Lyude Paul wrote:
> > Finally! For a very long time, our MST helpers have had one very
> > annoying issue: They don't know how to reprobe the topology state when
> > coming out of suspend. This means
On Wed, Oct 9, 2019 at 8:52 PM Greathouse, Joseph
wrote:
>
> > From: Daniel Vetter On Behalf Of Daniel Vetter
> > Sent: Wednesday, October 9, 2019 11:07 AM
> > On Wed, Oct 09, 2019 at 03:53:42PM +, Kuehling, Felix wrote:
> > > On 2019-10-09 11:34, Daniel Vetter wrote:
> > > > On Wed, Oct 09,
I misunderstood and was talking about the ksv validation specifically
(usage of drm_hdcp_check_ksvs_revoked()).
For the defines I will create patches to use drm_hdcp where it is usable.
Bhawan
On 2019-10-09 2:43 p.m., Daniel Vetter wrote:
> On Wed, Oct 9, 2019 at 8:23 PM Lakha, Bhawanpreet
>
On Wed, Oct 9, 2019 at 10:46 PM Lakha, Bhawanpreet
wrote:
>
> I misunderstood and was talking about the ksv validation specifically
> (usage of drm_hdcp_check_ksvs_revoked()).
Hm for that specifically I think you want to do both, i.e. both
consult your psp, but also check for revoked ksvs with
From: Dmytro Laktyushkin
Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to
From: Lewis Huang
[why]
driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box
[How]
Move the patch function before calculate wm.
Signed-off-by: Lewis Huang
Signed-off-by: joseph graveno
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 25
Hi all,
There was a delta betwwen internal dcn21 code and upstream dcn21 code.
These changes bring them inline.
Summary of Changes
*Add RN registors
*Add dcn12 hwseq and link_encoder
*RN specific fixes
*aux timeout support
*bounding box changes
Bhawanpreet Lakha (12):
drm/amd/display: Add
From: Lewis Huang
[Why]
Watermarks not propagated to DCHUBP after it is powered on
[How]
Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
[Why]
DCN20 and DCN21 have different phy programming sequences.
[How]
Create a separate dcn21_link_encoder for Renoir
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +-
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 +
DPM level is 8 these were incorrect before. Fix them
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
From: Eric Yang
[Why]
Renoir is gfx9, same as dcn10, not dcn20.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
This change adds renoir hw_seq, needed to do renoir
specific hw programing
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
use dcn20 common regs define to share some regs with dcn20
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
Detile buffer size affects dcc caps, it was already added for
dcn2. Now add it for dcn21
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
Use requested_dispclk_khz / 1000 directly
Signed-off-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
From: Michael Strauss
[WHY]
dprefclk is improperly read due to incorrect units used.
Causes an audio clock to be improperly set, making audio
non-functional and videos play back too fast
[HOW]
Scale dprefclk value from MHz to KHz (multiply by 1000)
to ensure that dprefclk_khz is in correct
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/include/renoir_ip_offset.h| 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
index 094648cac392..07633e22e99a 100644
---
From: abdoulaye berthe
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
From: Dmytro Laktyushkin
Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 40
From: Lewis Huang
[Why]
SMU fixed this issue after version 0x370c00
[How]
enable smu send message to set dcfclk after smu version 0x370c00
Signed-off-by: Lewis Huang
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4 ++--
1 file changed, 2
Handle 18 DecimalBPP like other cases
Signed-off-by: Bhawanpreet Lakha
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
From: Sung Lee
[Why]
Previously only dummy functions were added in Diags for FPGA.
On silicon, this would lead to a segmentation fault on silicon diags.
[How]
Check if diags silicon and if so, add dummy functions.
Signed-off-by: Sung Lee
Acked-by: Bhawanpreet Lakha
---
The values for bounding box and res_caps were incorrect. So
Fix them
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++-
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
From: Dmytro Laktyushkin
Renoir can use vm contexes as long as HOSTVM is off so
this should be initialized.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
it allows us to do urgent latency programming
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 16
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 39 +--
.../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17
Incorrect page table address and programming sys aperture for
stutter gather, so fix it.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 23 ++-
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git
From: joseph gravenor
[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of
the 0th table
of that is identical to the corrisponding value of MP0_BASE in the renoir
offset header file.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h| 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
index
From: Dmytro Laktyushkin
1 vmid limitation only exists for HOSTVM which is a custom
use case anyway.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: abdoulaye berthe
[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14
From: Eric Yang
[Why]
Handle the case where we don't get a valid table. Also fixes compiler
warning for variable potentially used before assignment.
[How]
If the entire table has no valid fclk, reject the table and use our own
hard code.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
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