[PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

From: changzhu It may fail to load guest driver in round 2 when using invalidate semaphore for SRIOV. So it needs to avoid using invalidate semaphore for SRIOV. Change-Id: I8db1dc6f990fd0c458953571936467551cd4102d Signed-off-by: changzhu --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21

[PATCH 2/2] drm/amdgpu: avoid using invalidate semaphore for picasso

From: changzhu It may cause timeout waiting for sem acquire in VM flush when using invalidate semaphore for picasso. So it needs to avoid using invalidate semaphore for piasso. Change-Id: I300e96af5c66b33a7d61e6420caa33d70471d44a Signed-off-by: changzhu --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

Hello Christian, My "setpci -s 0001:01:00.0 ECAP15+4.l ECAP15+8.l" output is; 0001f000 0820 Regards. Yusuf Altıparmak , 2 Ara 2019 Pzt, 19:31 tarihinde şunu yazdı: > Most likely not. There is support for resizing the VRAM BAR, but usually >> you can only make it larger and not smaller. >

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

Hi Yusuf, 0001f000 Exactly as I thought. The hardware does support BAR resize, but unfortunately 256MB is already the minimum. Sorry, but there isn't anything I could do from the GPU drivers point of view. The only good news I have is that 256M+2M+512K+128K=260M address space should be en

Re: [PATCH 1/2] drm/amdkfd: Contain MMHUB number in the implementation

Am 03.12.19 um 05:42 schrieb Yong Zhao: Adjust the exposed function prototype so that the caller does not need to know the MMHUB number. Change-Id: I4420d1715984f703954f074682b075fc59e2a330 Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 6 ++ drivers/gp

Re: [PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

Am 03.12.19 um 09:50 schrieb Changfeng.Zhu: From: changzhu It may fail to load guest driver in round 2 when using invalidate semaphore for SRIOV. So it needs to avoid using invalidate semaphore for SRIOV. That sounds like the registers are just not correctly initialized when the driver is re

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

Hi Christian, > 0001f000 > > Exactly as I thought. The hardware does support BAR resize, but > unfortunately 256MB is already the minimum. > > Sorry, but there isn't anything I could do from the GPU drivers point of > view. > Yes unfortunately there is nothing remained to about GPU side. The onl

RE: [PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

[AMD Official Use Only - Internal Distribution Only] OK Chris. I'll try and test it. BR, Changfeng. -Original Message- From: Christian König Sent: Tuesday, December 3, 2019 8:18 PM To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org; Koenig, Christian ; Huang, Ray ; Huang, Shimmer ;

[PATCH v8 02/17] drm/dp_mst: Parse FEC capability on MST ports

From: David Francis As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating if FEC can be supported up to that point in the MST network. The bit is the first byte of the ENUM_PATH_RESOURCES ack reply, bottom-most bit (refer to section 2.11.9.4 of DP standard, v1.4) That value is needed for FE

[PATCH v8 01/17] drm/dp_mst: Add PBN calculation for DSC modes

From: David Francis With DSC, bpp can be fractional in multiples of 1/16. Change drm_dp_calc_pbn_mode to reflect this, adding a new parameter bool dsc. When this parameter is true, treat the bpp parameter as having units not of bits per pixel, but 1/16 of a bit per pixel v2: Don't add separate

[PATCH v8 08/17] drm/amd/display: Validate DSC caps on MST endpoints

From: David Francis During MST mode enumeration, if a new dc_sink is created, populate it with dsc caps as appropriate. Use drm_dp_mst_dsc_aux_for_port to get the raw caps, then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd. Reviewed-by: Wenjing Liu Signed-off-by: David Francis Signed-of

[PATCH v8 11/17] drm/dp_mst: Add DSC enablement helpers to DRM

From: Mikita Lipski Adding a helper function to be called by drivers outside of DRM to enable DSC on the MST ports. Function is called to recalculate VCPI allocation if DSC is enabled and raise the DSC flag to enable. In case of disabling DSC the flag is set to false and recalculation of VCPI sl

[PATCH v8 03/17] drm/dp_mst: Add MST support to DP DPCD R/W functions

From: David Francis Instead of having drm_dp_dpcd_read/write and drm_dp_mst_dpcd_read/write as entry points into the aux code, have drm_dp_dpcd_read/write handle both. This means that DRM drivers can make MST DPCD read/writes. v2: Fix spacing v3: Dump dpcd access on MST read/writes v4: Fix call

[PATCH v8 14/17] drm/amd/display: MST DSC compute fair share

From: David Francis If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network Implement an algorithm to determine the correct DSC config for each stream The algorithm: This [ ] ( ) represents the range of b

[PATCH v8 00/17] DSC MST support for DRM and AMDGPU

From: Mikita Lipski This set of patches is a continuation of DSC enablement patches for AMDGPU. This set enables DSC on MST. It also contains implementation of both encoder and connector atomic check routines. These patches have been introduced in multiple iterations to the mailing list before.

[PATCH v8 12/17] drm/dp_mst: Add branch bandwidth validation to MST atomic check

From: Mikita Lipski Adding PBN attribute to drm_dp_vcpi_allocation structure to keep track of how much bandwidth each Port requires. Adding drm_dp_mst_atomic_check_bw_limit to verify that state's bandwidth needs doesn't exceed available bandwidth. The funtion is called in drm_dp_mst_atomic_check

[PATCH v8 07/17] drm/amd/display: Initialize DSC PPS variables to 0

From: David Francis For DSC MST, sometimes monitors would break out in full-screen static. The issue traced back to the PPS generation code, where these variables were being used uninitialized and were picking up garbage. memset to 0 to avoid this Reviewed-by: Nicholas Kazlauskas Signed-off-by

[PATCH v8 09/17] drm/amd/display: Write DSC enable to MST DPCD

From: David Francis Rework the dm_helpers_write_dsc_enable callback to handle the MST case. Use the cached dsc_aux field. Reviewed-by: Wenjing Liu Signed-off-by: David Francis Signed-off-by: Mikita Lipski --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++- 1 file cha

[PATCH v8 05/17] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux

From: David Francis Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED register might have to be written on the leaf port's DPCD, its parent's DPCD, or the MST manager's DPCD. This function finds the correct aux for the job. As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual D

[PATCH v8 06/17] drm/dp_mst: Add new quirk for Synaptics MST hubs

From: Mikita Lipski Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not support virtual DPCD registers, but do support DSC. The DSC caps can be read from the physical aux, like in SST DSC. These hubs have many different DEVICE_IDs. Add a new quirk to detect this case. Reviewed-by: Wenjing Liu Rev

[PATCH v8 13/17] drm/amd/display: Add PBN per slot calculation for DSC

From: Mikita Lipski [why] Need to calculate VCPI slots differently for DSC to take in account current link rate, link count and FEC. [how] Add helper to get pbn_div from dc_link Signed-off-by: Mikita Lipski --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 .../gpu/drm

[PATCH v8 04/17] drm/dp_mst: Fill branch->num_ports

From: David Francis This field on drm_dp_mst_branch was never filled It is initialized to zero when the port is kzallocced. When a port is added to the list, increment num_ports, and when a port is removed from the list, decrement num_ports. v2: remember to decrement on port removal v3: don't e

[PATCH v8 10/17] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots

From: Mikita Lipski [why] For DSC case we cannot always use topology manager's PBN divider variable. The default divider does not take FEC into account. Therefore we should allow driver to calculate its own divider based on the link rate and count its handling, as it is hw specific. [how] Pass pb

[PATCH v8 16/17] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs

From: Mikita Lipski [why] Whenever a connector on an MST network is changed or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stre

[PATCH v8 15/17] drm/amd/display: Recalculate VCPI slots for new DSC connectors

From: Mikita Lipski [why] Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector. [how] The function iterates through all the active streams to find, which have DSC enabled, then recalculates PBN for it an

[PATCH v8 17/17] drm/amd/display: Trigger modesets on MST DSC connectors

From: Mikita Lipski Whenever a connector on an MST network is attached, detached, or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if tha

[PATCH] drm/amdkfd: Contain MMHUB number in mmhub_v9_4_setup_vm_pt_regs()

Adjust the exposed function prototype so that the caller does not need to know the MMHUB number. Change-Id: I4420d1715984f703954f074682b075fc59e2a330 Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 6 ++ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 8

Re: [RFC PATCH] drm/amdgpu: allocate entities on demand

Hi Christian, On 12/2/19 3:59 PM, Christian König wrote: Am 02.12.19 um 15:43 schrieb Nirmoy: Do you mean something like diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 684692a8ed76..ac67f8f098fa 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_sched

Re: [PATCH] drm/amdkfd: Contain MMHUB number in mmhub_v9_4_setup_vm_pt_regs()

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Alex Deucher From: amd-gfx on behalf of Yong Zhao Sent: Tuesday, December 3, 2019 10:02 AM To: amd-gfx@lists.freedesktop.org Cc: Zhao, Yong Subject: [PATCH] drm/amdkfd: Contain MMHUB number in

Re: [PATCH RFC v4 16/16] drm/amdgpu: Integrate with DRM cgroup

Hey Joe, I don't have all the answers right now but one thing I want to mention is that, with cgroup, there's always a possibility for a user configuration that lead to under resource for the application. Your comments certainly highlight the needs to make under-resource situation obvious to debu

[PATCH v9] drm/dp_mst: Add PBN calculation for DSC modes

From: David Francis With DSC, bpp can be fractional in multiples of 1/16. Change drm_dp_calc_pbn_mode to reflect this, adding a new parameter bool dsc. When this parameter is true, treat the bpp parameter as having units not of bits per pixel, but 1/16 of a bit per pixel v2: Don't add separate

[PATCH] drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code

[Why] NV10/14 has released. Its time to get NV10/14 bounding box directly from code. [How] Retrieve NV10/14 bounding box data directly from code. Signed-off-by: Zhan Liu --- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 199 +++--- 1 file changed, 121 insertions(+), 2 deletions(-)

Re: [PATCH] drm/radeon: fix r1xx/r2xx register checker for POT textures

On 2019-11-26 3:43 p.m., Alex Deucher wrote: > Shift and mask were reversed. Noticed by chance. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/radeon/r100.c | 4 ++-- > drivers/gpu/drm/radeon/r200.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/

Re: [PATCH] drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code

On 2019-12-03 12:02 p.m., Zhan Liu wrote: [Why] NV10/14 has released. Its time to get NV10/14 bounding box directly from code. [How] Retrieve NV10/14 bounding box data directly from code. Signed-off-by: Zhan Liu --- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 199 +++--- 1 f

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

Right now I am trying to increase MMIO size config to 512 MB What you could try as well is to use the size 320MB for the MMIO. Those ranges usually don't need to be a power of two (only the BARs itself are a power of two) and this way it might even be easier to fit everything together. By the

Re: [RFC PATCH] drm/amdgpu: allocate entities on demand

Am 03.12.19 um 16:02 schrieb Nirmoy: Hi Christian, On 12/2/19 3:59 PM, Christian König wrote: Am 02.12.19 um 15:43 schrieb Nirmoy: Do you mean something like diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 684692a8ed76..ac67f8f098fa 100644 --- a/include/drm/gpu_s

Re: [RFC PATCH] drm/amdgpu: allocate entities on demand

Am 03.12.19 um 18:33 schrieb Christian König: Am 03.12.19 um 16:02 schrieb Nirmoy: Hi Christian, On 12/2/19 3:59 PM, Christian König wrote: Am 02.12.19 um 15:43 schrieb Nirmoy: Do you mean something like diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 684692a8ed

[PATCH v2] drm/amd/display: Loading NV10/14 Bounding Box Data Directly from Code

[Why] NV10/14 has released. Its time to get NV10/14 bounding box directly from code. [How] Retrieve NV10/14 bounding box data directly from code. Retrieve NV12 bounding box data from firmware. Signed-off-by: Zhan Liu --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++ 1 file

RE: [PATCH v2] drm/amd/display: Loading NV10/14 Bounding Box Data Directly from Code

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: hersen wu < hersenxs...@amd.com> -Original Message- From: Liu, Zhan Sent: Tuesday, December 3, 2019 12:49 PM To: amd-gfx@lists.freedesktop.org; Wu, Hersen ; Kazlauskas, Nicholas Cc: Liu, Zhan Subject: [PATCH v2] drm/a

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian didn't pull to amd-staging-drm-next yet. Andrey On 12/2/19 2:24 PM, Deng, Emily wrote: [AMD Official Use Only - Internal Distribution Only] Hi Andrey, Seems this patch is still not in amd-staging-drm-next? Best wis

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[AMD Official Use Only - Internal Distribution Only] Please go ahead an apply whatever version is necessary for amd-staging-drm-next. Alex From: Grodzovsky, Andrey Sent: Tuesday, December 3, 2019 2:10 PM To: Deng, Emily ; Deucher, Alexander Cc: dri-de...@lists

RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[AMD Official Use Only - Internal Distribution Only] Hi Alex, When we will cherry pick those patches to drm-next? >-Original Message- >From: Grodzovsky, Andrey >Sent: Tuesday, December 3, 2019 11:10 AM >To: Deng, Emily ; Deucher, Alexander > >Cc: dri-de...@lists.freedesktop.org; amd-

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

I don't think i can apply this patch 'as is' as this has dependency on patch by Steven which also wasn't applied yet - 588b982 Steven Price    6 weeks ago    drm: Don't free jobs in wait_event_interruptible() Andrey On 12/3/19 2:44 PM, Deucher, Alexander wrote: [AMD Official Use Only

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[AMD Official Use Only - Internal Distribution Only] Cherry pick whatever dependencies you need or pick the older version of the patch. Either way works. Alex From: Grodzovsky, Andrey Sent: Tuesday, December 3, 2019 2:57 PM To: Deucher, Alexander ; Deng, Emily

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

Turns out Steven's patch was already in so i just cherry-picked the change from drm-next-misc Emily - it's in. Andrey On 12/3/19 2:59 PM, Deucher, Alexander wrote: [AMD Official Use Only - Internal Distribution Only] Cherry pick whatever dependencies you need or pick the older version

[pull] amdgpu, amdkfd, radeon drm-next-5.5

Hi Dave, Daniel, Fixes for 5.5. The following changes since commit acc61b8929365e63a3e8c8c8913177795aa45594: Merge tag 'drm-next-5.5-2019-11-22' of git://people.freedesktop.org/~agd5f/linux into drm-next (2019-11-26 08:40:23 +1000) are available in the Git repository at: git://people.fre

[PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

SPI limits total CS waves in flight per SE to no more than 32 * num_cu and we need to stuff 40 waves on a CU to completely clean the SGPR. This is accomplished in the WR by cleaning the SE in two steps, half of the CU per step. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |

RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[AMD Official Use Only - Internal Distribution Only] Hi Andrey, Thanks very much. Best wishes Emily Deng From: Grodzovsky, Andrey Sent: Tuesday, December 3, 2019 12:33 PM To: Deucher, Alexander ; Deng, Emily Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig, Chris

Re: [PATCH v8 02/17] drm/dp_mst: Parse FEC capability on MST ports

Hi, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20191203] [cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 v5.4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to

Re: [PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

Not sure whether we should add the issue ticket info here. Reviewed-by: Yong Zhao On 2019-12-03 3:45 p.m., James Zhu wrote: SPI limits total CS waves in flight per SE to no more than 32 * num_cu and we need to stuff 40 waves on a CU to completely clean the SGPR. This is accomplished in the

Re: [PATCH v8 11/17] drm/dp_mst: Add DSC enablement helpers to DRM

Hi, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20191203] [cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 v5.4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to

Re: [PATCH v8 16/17] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs

Hi, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20191203] [cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 v5.4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to

RE: [PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Zhu, James Sent: 2019年12月4日 4:45 To: amd-gfx@lists.freedesktop.org Cc: Zhu, James ; Zhang, Hawking Subject: [PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds SPI limits total CS waves in flight per SE to no

RE: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI

[AMD Official Use Only - Internal Distribution Only] From: Grodzovsky, Andrey Sent: Wednesday, December 4, 2019 2:44 AM To: Ma, Le ; amd-gfx@lists.freedesktop.org; Zhou1, Tao ; Deucher, Alexander ; Li, Dennis ; Zhang, Hawking Cc: Chen, Guchun Subject: Re: [PATCH 07/10] drm/amdgpu: add concur

[PATCH] drm/amdkfd: fix a minor typo on user queue init

Fix PQM -> DQM. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index d3eacf7..

RE: [PATCH] drm/amdkfd: fix a minor typo on user queue init

Sorry, please ignore this patch. Just misunderstood before. Thanks, Ray -Original Message- From: Huang, Ray Sent: Wednesday, December 4, 2019 3:22 PM To: amd-gfx@lists.freedesktop.org; Kuehling, Felix ; Zhao, Yong Cc: Deucher, Alexander ; Huang, Ray Subject: [PATCH] drm/amdkfd: fix