[PATCH] drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V2)

From: "Tianci.Yin" [why] In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU, since there is no pre-OS console using that memory. Then the bottom region of VRAM was allocated as GTT, unfortunately a small region of bottom VRAM was encroached by UMC firmware during GDDR6

Re: [PATCH 0/2] drm/radeon: have the callers of set_memory_*() check the return value

Hi Am 09.01.20 um 11:15 schrieb Christian König: > Am 08.01.20 um 18:51 schrieb Alex Deucher: >> On Wed, Jan 8, 2020 at 12:39 PM Kees Cook wrote: >>> On Wed, Jan 08, 2020 at 01:56:47PM +0100, Christian König wrote: Am 07.01.20 um 20:25 schrieb Tianlin Li: > Right now several

[PATCH] drm/amdgpu: check sdma ras funcs pointer before accessing

sdma ras funcs are not supported by ASIC prior to vega20 Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index

[PATCH] drm/amdgpu: error out on entity with no run queue

Disabled HW IP's entity initialized with NULL rq. We should not process any submit request from userspace for a disabled HW IP. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

RE: [PATCH] drm/amdgpu: check sdma ras funcs pointer before accessing

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Le Ma -Original Message- From: amd-gfx On Behalf Of Hawking Zhang Sent: Thursday, January 9, 2020 7:42 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking Subject: [PATCH] drm/amdgpu: check sdma ras funcs pointer

[PATCH] drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V3)

From: "Tianci.Yin" [why] In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU, since there is no pre-OS console using that memory. Then the bottom region of VRAM was allocated as GTT, unfortunately a small region of bottom VRAM was encroached by UMC firmware during GDDR6

Re: [PATCH 1/2] drm/amdgpu/gmc10: remove dead code

Am 09.01.20 um 04:16 schrieb Alex Deucher: Leftover from bring up. We look up the actual pre-OS memory usage value later in the same function. Signed-off-by: Alex Deucher Reviewed-by: Christian König for the series. --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 9 - 1 file

Re: [PATCH] drm/amdgpu: fix modprobe failure of the 2nd GPU when GDDR6 training enabled

[AMD Official Use Only - Internal Distribution Only] Hi Christian, Thanks very much for your suggestions, I checked the original version of gmc_v10_0.c on branch origin/ruihuang/amd-temp-navi10-part1, amdgpu_bo_late_init() is not invoked by gmc_v10_0_late_init(), so I think it was missed from

Re: [PATCH] drm/amdgpu: fix modprobe failure of the 2nd GPU when GDDR6 training enabled

Hi Rico, maybe it is a good idea to look into the git history and/or google the mailing list history a bit more. I do briefly remember that we disabled freeing up the stolen VGA memory on some hardware generations because somebody was accessing that memory even after VGA was turned off.

Re: [PATCH 0/2] drm/radeon: have the callers of set_memory_*() check the return value

Am 08.01.20 um 18:51 schrieb Alex Deucher: On Wed, Jan 8, 2020 at 12:39 PM Kees Cook wrote: On Wed, Jan 08, 2020 at 01:56:47PM +0100, Christian König wrote: Am 07.01.20 um 20:25 schrieb Tianlin Li: Right now several architectures allow their set_memory_*() family of functions to fail, but

Re: [PATCH 1/3] drm/amdgpu/display: set gpu vm flag for all asics which support it

Am 08.01.20 um 23:49 schrieb Alex Deucher: It won't get used unless the driver allows the gtt domain for display buffers which is controlled elsewhere. Signed-off-by: Alex Deucher Acked-by: Christian König --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 -- 1

Re: [PATCH] drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V2)

Am 09.01.20 um 11:17 schrieb Tianci Yin: From: "Tianci.Yin" [why] In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU, since there is no pre-OS console using that memory. Then the bottom region of VRAM was allocated as GTT, unfortunately a small region of bottom VRAM

Re: [PATCH] drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file

note: I have since fixed the #ifndef/#define lines for when I eventually push it out On Thu, Jan 9, 2020 at 10:40 AM Tom St Denis wrote: > Signed-off-by: Tom St Denis > --- > .../include/asic_reg/umc/umc_6_1_2_sh_mask.h | 91 +++ > 1 file changed, 91 insertions(+) > create

[PATCH] drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file

Signed-off-by: Tom St Denis --- .../include/asic_reg/umc/umc_6_1_2_sh_mask.h | 91 +++ 1 file changed, 91 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h

Re: [PATCH] drm/dp_mst: fix documentation of drm_dp_mst_add_affected_dsc_crtcs

Thank you, Reviewed-by: Mikita Lipski On 1/8/20 10:24 PM, Alex Deucher wrote: the parameter is the mst manager, not the port. Signed-off-by: Alex Deucher --- drivers/gpu/drm/drm_dp_mst_topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH] drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file

On Thu, Jan 9, 2020 at 10:59 AM Tom St Denis wrote: > > note: I have since fixed the #ifndef/#define lines for when I eventually push > it out Reviewed-by: Alex Deucher > > On Thu, Jan 9, 2020 at 10:40 AM Tom St Denis wrote: >> >> Signed-off-by: Tom St Denis >> --- >>

Re: [PATCH 2/2] drm/amd/display: Allow current eDP link settings to override verified ones.

On 2020-01-09 10:20 a.m., Mario Kleiner wrote: > If the current eDP link settings, as read from hw, provide a higher > bandwidth than the verified_link_cap ones (= reported_link_cap), then > override verified_link_cap with current settings. > > These initial current eDP link settings have been

Re: [PATCH 1/2] drm/amd/display: Reorder detect_edp_sink_caps before link settings read.

On 2020-01-09 10:20 a.m., Mario Kleiner wrote: > read_current_link_settings_on_detect() on eDP 1.4+ may use the > edp_supported_link_rates table which is set up by > detect_edp_sink_caps(), so that function needs to be called first. > > Signed-off-by: Mario Kleiner > Cc: Martin Leung

[PATCH 1/2] drm/amd/display: Reorder detect_edp_sink_caps before link settings read.

read_current_link_settings_on_detect() on eDP 1.4+ may use the edp_supported_link_rates table which is set up by detect_edp_sink_caps(), so that function needs to be called first. Signed-off-by: Mario Kleiner Cc: Martin Leung --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- 1 file

Some eDP fixes/improvements.

Hi and happy new year! Since i now have a MBP 2017 to play with, with a 10 bit Retina panel, and Polaris gpu, i'm trying to get it to get 10 bits, and found one small bug [fix: patch1], and a quirk of Apples Retina eDP sink, for which i propose patch2 as solution. I sent a similar patch to i915

[PATCH 2/2] drm/amd/display: Allow current eDP link settings to override verified ones.

If the current eDP link settings, as read from hw, provide a higher bandwidth than the verified_link_cap ones (= reported_link_cap), then override verified_link_cap with current settings. These initial current eDP link settings have been set up by firmware during boot, so they should work on the

Re: [PATCH] drm/amdgpu: check sdma ras funcs pointer before accessing

[AMD Official Use Only - Internal Distribution Only] I just got hit by this bug. Reviewed-by: Nirmoy Das mailto:le...@amd.com>> Thanks, Nirmoy From: amd-gfx on behalf of Hawking Zhang Sent: Thursday, January 9, 2020 12:42:13 PM To:

Re: [PATCH 0/2] drm/radeon: have the callers of set_memory_*() check the return value

On Thu, Jan 9, 2020 at 5:49 AM Thomas Zimmermann wrote: > > Hi > > Am 09.01.20 um 11:15 schrieb Christian König: > > Am 08.01.20 um 18:51 schrieb Alex Deucher: > >> On Wed, Jan 8, 2020 at 12:39 PM Kees Cook wrote: > >>> On Wed, Jan 08, 2020 at 01:56:47PM +0100, Christian König wrote: > Am

Re: [PATCH 1/3] drm/amdgpu/display: set gpu vm flag for all asics which support it

On Thu, Jan 9, 2020 at 12:36 AM Huang Rui wrote: > > On Wed, Jan 08, 2020 at 05:49:08PM -0500, Alex Deucher wrote: > > It won't get used unless the driver allows the gtt domain for > > display buffers which is controlled elsewhere. > > > > Signed-off-by: Alex Deucher > > Series are Acked-by:

[PATCH] drm/amdgpu/powerplay: fix warning in smu_v11_0.c

Cast to make min() happy. The values are well within range. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index

[pull] amdgpu, amdkfd, radeon, scheduler drm-next-5.6

Hi Dave, Daniel, More new stuff for 5.6. A few more things I forgot to put in the tag: amdgpu: - Use a task barrier to properly synchronize multi-GPU reset radeon: - Misc cleanups drm: - Add a task barrier helper for synchronizing threads scheduler: - Entity creation rework to separate

[PATCH] drm/amdgpu/psp: declare navi1x ta firmware

So that it gets included in the initrd. At the moment this is optional firmware that contains support for HDCP. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

[PATCH 1/7] drm/amdgpu: Avoid reclaim fs while eviction lock

[Why] Avoid reclaim filesystem while eviction lock is held called from MMU notifier. [How] Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked. Using memalloc_nofs_save / memalloc_nofs_restore API. Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c Signed-off-by: Alex Sierra ---

[PATCH 6/7] drm/amdgpu: implement tlbs invalidate on gfx9 gfx10

tlbs invalidate pointer function added to kiq_pm4_funcs struct. This way, tlb flush can be done through kiq member. TLBs invalidatation implemented for gfx9 and gfx10. Change-Id: I1b77b364f3ae0038ff3e70e869be5f2ef6e6d293 Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |

[PATCH 5/7] drm/amdgpu: kiq pm4 function implementation for gfx_v9

Functions implemented from kiq_pm4_funcs struct members for gfx_v9 version. Change-Id: I8fd3e160c4bd58f19d35d29e39517db967063afe Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 115 ++ 1 file changed, 115 insertions(+) diff --git

[PATCH 3/7] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd

[Why] TLB flush method has been deprecated using kfd2kgd interface. This implementation is now on the amdgpu_amdkfd API. [How] TLB flush functions now implemented in amdgpu_amdkfd. Change-Id: Ic51cccdfe6e71288d78da772b6e1b6ced72f8ef7 Signed-off-by: Alex Sierra ---

[PATCH 2/7] drm/amdgpu: export function to flush TLB via pasid

This can be used directly from amdgpu and amdkfd to invalidate TLB through pasid. It supports gmc v7, v8, v9 and v10. Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490 Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 87

[PATCH 7/7] drm/amdgpu: tlbs invalidate replaced by kiq_pm4_funcs

TLBs invalidation was removed from gmc_v9 and gmc_v10 files. This implementation has been moved to kiq_pm4_funcs calls. Change-Id: I66463e2e5fdf7611ef4a802eb517ae0d269987c3 Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32 ++

[PATCH 4/7] drm/amdgpu: flush TLB functions removal from kfd2kgd interface

[Why] kfd2kgd interface will be deprecated. This removal only covers TLB invalidation for now. They have been replaced in amdgpu_amdkfd API. [How] TLB invalidate functions removed from the different amdkfd_gfx_v* versions. Change-Id: Ic2c7d4a0d19fe1e884dee1ff10a520d31252afee Signed-off-by: Alex

[pull] drm DP MST DSC support

Hi Dave, Daniel, Ideally this would have gone through drm-misc, but it had dependencies on some changes in the DC code which were in my latest PR, so I sent this as a separate PR on top of my amdgpu PR. The following changes since commit 0f899fd466b693a129b16994c1b2b4db2fcde4a4: drm/amdkfd:

[PATCH 1/8] drm/amdgpu: Avoid reclaim fs while eviction lock

[Why] Avoid reclaim filesystem while eviction lock is held called from MMU notifier. [How] Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked. Using memalloc_nofs_save / memalloc_nofs_restore API. Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c Signed-off-by: Alex Sierra ---

[PATCH 7/8] drm/amdgpu: tlbs invalidate replaced by kiq_pm4_funcs

TLBs invalidation was removed from gmc_v9 and gmc_v10 files. This implementation has been moved to kiq_pm4_funcs calls. Change-Id: I66463e2e5fdf7611ef4a802eb517ae0d269987c3 Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 32 ++

[PATCH 8/8] drm/amdgpu: replace kcq enable function on gfx_v9

[Why] There's a HW-indpendent function that enables kcq. This function uses the kiq_pm4_funcs implementation. [How] Local kcq enable function removed and replace it by the generic kcq enable under amdgpu_gfx Change-Id: I7709bdba93742c234941a5936c82eb67e346077c Signed-off-by: Alex Sierra ---

[PATCH 5/8] drm/amdgpu: kiq pm4 function implementation for gfx_v9

Functions implemented from kiq_pm4_funcs struct members for gfx_v9 version. Change-Id: I8fd3e160c4bd58f19d35d29e39517db967063afe Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 115 ++ 1 file changed, 115 insertions(+) diff --git

[PATCH 2/8] drm/amdgpu: export function to flush TLB via pasid

This can be used directly from amdgpu and amdkfd to invalidate TLB through pasid. It supports gmc v7, v8, v9 and v10. Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490 Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 87

[PATCH 6/8] drm/amdgpu: implement tlbs invalidate on gfx9 gfx10

tlbs invalidate pointer function added to kiq_pm4_funcs struct. This way, tlb flush can be done through kiq member. TLBs invalidatation implemented for gfx9 and gfx10. Change-Id: I1b77b364f3ae0038ff3e70e869be5f2ef6e6d293 Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |

[PATCH 4/8] drm/amdgpu: flush TLB functions removal from kfd2kgd interface

[Why] kfd2kgd interface will be deprecated. This removal only covers TLB invalidation for now. They have been replaced in amdgpu_amdkfd API. [How] TLB invalidate functions removed from the different amdkfd_gfx_v* versions. Change-Id: Ic2c7d4a0d19fe1e884dee1ff10a520d31252afee Signed-off-by: Alex

[PATCH 3/8] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd

[Why] TLB flush method has been deprecated using kfd2kgd interface. This implementation is now on the amdgpu_amdkfd API. [How] TLB flush functions now implemented in amdgpu_amdkfd. Change-Id: Ic51cccdfe6e71288d78da772b6e1b6ced72f8ef7 Signed-off-by: Alex Sierra ---

Re: [PATCH 2/2] drm/amd/display: Allow current eDP link settings to override verified ones.

On Thu, Jan 9, 2020 at 7:44 PM Harry Wentland wrote: > On 2020-01-09 10:20 a.m., Mario Kleiner wrote: > > If the current eDP link settings, as read from hw, provide a higher > > bandwidth than the verified_link_cap ones (= reported_link_cap), then > > override verified_link_cap with current

Re: [PATCH 2/2] drm/amd/display: Allow current eDP link settings to override verified ones.

On 2020-01-09 4:13 p.m., Mario Kleiner wrote: > On Thu, Jan 9, 2020 at 7:44 PM Harry Wentland > wrote: > > On 2020-01-09 10:20 a.m., Mario Kleiner wrote: > > If the current eDP link settings, as read from hw, provide a higher > > bandwidth than the

[PATCH 1/1] drm/amdgpu: Fix kernel oops in amdgpu_dpm_switch_power_profile

Pass the correct pp_handle to pp_dpm_switch_power_profile. Fixes: 9bbdc6e48ec0 ("drm/amd/powerplay: cover the powerplay implementation details V2") Change-Id: Ia6998a836815c274509bd7967c1c148475252fa6 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 3 ++- 1 file

[PATCH 4/5] drm/amdkfd: use map_queues for hiq on gfx v10 as well

To align with gfx v9, we use the map_queues packet to load hiq MQD. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 82 -- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 10 ++- 2 files changed, 70 insertions(+), 22 deletions(-) diff

RE: [PATCH 1/1] drm/amdgpu: Fix kernel oops in amdgpu_dpm_switch_power_profile

Thanks for the fix. Reviewed-by: Evan Quan > -Original Message- > From: Kuehling, Felix > Sent: Friday, January 10, 2020 2:00 PM > To: amd-gfx@lists.freedesktop.org > Cc: Quan, Evan > Subject: [PATCH 1/1] drm/amdgpu: Fix kernel oops in > amdgpu_dpm_switch_power_profile > > Pass the

[PATCH 2/5] drm/amdkfd: use kiq to load the mqd of hiq queue for gfx v9 (v5)

From: Aaron Liu There is an issue that CP will check the HIQ queue to be configured and mapped with KIQ ring, otherwise, it will be unable to read back the secure buffer while the gfxoff is enabled even with trusted IP blocks. v1 -> v2: - Fix to remove surplus set_resources packets. - Fill the

[PATCH 5/5] drm/amdkfd: use map_queues for hiq on gfx v8 as well

Align with gfx v9, use map_queues packet to load hiq MQD. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 69 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 10 +++- 2 files changed, 63 insertions(+), 16 deletions(-) diff --git

[PATCH 1/5] drm/amdgpu: only set cp active field for kiq queue

The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped by MAP_QUEUES packet. So we only need set cp active field for kiq queue. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +--

[PATCH 3/5] drm/amdkfd: use map_queues for hiq on arcturus as well

Align with gfx v9, use the map_queues packet to load hiq MQD. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 3 +++ 3 files changed, 7

[PATCH 2/3] drm/amdgpu: add defines for DF and TCP Hashing

On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in

Rework DF to prepare for VBIOS that turns on channel hashing

When we start receiving Arcturus VBIOS that turns on channel hashing in the data fabric, we need to make sure that the texture cache's channel hashing setting match up. To do this, we query the DF's settings and cache them in adev, then mirror them into the cache confirmation on init. This

RE: [PATCH] drm/amdgpu/psp: declare navi1x ta firmware

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Friday, January 10, 2020 7:30 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/psp: declare navi1x ta firmware > > So that it gets included in

RE: [PATCH] drm/amdgpu/powerplay: fix warning in smu_v11_0.c

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Friday, January 10, 2020 4:45 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/powerplay: fix warning in smu_v11_0.c > > Cast to make min()

[PATCH 3/3] drm/amdgpu: Match TC hash settings to DF settings

On Arcturus, data fabric hashing is set by the VBIOS, and affects which addresses map to which memory channels. The gfx core's caches also need to know this mapping, but the hash settings for these these caches is set by the driver. This change queries the DF to understand how the VBIOS

[PATCH 1/3] drm/amdgpu: Create generic DF struct in adev

The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev to old. Right now, it only containst the old function pointer

[PATCH] drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V4)

From: "Tianci.Yin" [why] In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU, since there is no pre-OS console using that memory. Then the bottom region of VRAM was allocated as GTT, unfortunately a small region of bottom VRAM was encroached by UMC firmware during GDDR6