Since on early phase of bringup, the SMU IP may be not enabled or
supported. Without this, we may hit null pointer dereference on
accessing smu->adev.
Change-Id: I644175e926cd4fef8259f89002d6f8eda04fe42c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 266
On 2020-05-22 8:03 p.m., Nicholas Kazlauskas wrote:
> [Why]
> Warnings in the kernel are generally treated as errors.
>
> The BREAK_TO_DEBUGGER macro is not a critical error or warning, but
> rather intended for developer use to help investigate behavior and
> sequences for other issues.
>
> We
On Tue, May 12, 2020 at 11:04 AM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2020-05-12 09:59:29)
> > Design is similar to the lockdep annotations for workers, but with
> > some twists:
> >
> > - We use a read-lock for the execution/worker/completion side, so that
> > this explicit
Hi Daniel,
We are trying to enable this feature in the Modesetting driver based on AMD
DDX driver as a reference.
Do you have any pointers to make this work ?
Thanks
Uday Kiran
On Mon, May 25, 2020 at 8:45 PM Daniel Vetter wrote:
> On Mon, May 25, 2020 at 07:01:21PM +0530, uday kiran pichika
Hello,
Am working on enabling the Adaptive sync feature as part of the
Xorg/Modesetting DDX driver by taking the reference of AMD DDX Driver
(xf86-video-amdgpu). Below is the commit which i submitted.
https://gitlab.freedesktop.org/pichika/xserver/-/commit/682565a645bda7371cc3731ee805cc4a0ace80db
On Mon, May 25, 2020 at 07:01:21PM +0530, uday kiran pichika wrote:
> Hello,
>
> Am working on enabling the Adaptive sync feature as part of the
> Xorg/Modesetting DDX driver by taking the reference of AMD DDX Driver
> (xf86-video-amdgpu). Below is the commit which i submitted.
>
On Monday, May 25, 2020 5:15 PM, Daniel Vetter wrote:
> On Mon, May 25, 2020 at 07:01:21PM +0530, uday kiran pichika wrote:
>
> > Hello,
> > Am working on enabling the Adaptive sync feature as part of the
> > Xorg/Modesetting DDX driver by taking the reference of AMD DDX Driver
> >
On 2020-05-25 3:31 p.m., uday kiran pichika wrote:
> Hello,
>
> Am working on enabling the Adaptive sync feature as part of the
> Xorg/Modesetting DDX driver by taking the reference of AMD DDX Driver
> (xf86-video-amdgpu). Below is the commit which i submitted.
>
Thanks Michel..
sorry if my description is not clear.
Yes I have used with glxgears in fullscreen mode and also a simple glxapp
which actually opens in fullscreen by default.
In both the cases, the issue is same.
Just wanted to know if AMD has done anything different apart from the
Thanks for the input simon. Sway Compositor is based on the wayland
protocol right !!
But we are trying to do it through Xorg modesetting driver..
On Mon, May 25, 2020 at 8:50 PM Simon Ser wrote:
> On Monday, May 25, 2020 5:15 PM, Daniel Vetter wrote:
>
> > On Mon, May 25, 2020 at 07:01:21PM
On Tue, May 12, 2020 at 11:00 AM Daniel Vetter wrote:
>
> If the scheduler rt thread gets stuck on a mutex that we're holding
> while waiting for gpu workloads to complete, we have a problem.
>
> Add dma-fence annotations so that lockdep can check this for us.
>
> I've tried to quite carefully
On 2020-05-25 4:58 p.m., uday kiran pichika wrote:
> Thanks Michel..
>
> sorry if my description is not clear.
> Yes I have used with glxgears in fullscreen mode and also a simple glxapp
> which actually opens in fullscreen by default.
>
> In both the cases, the issue is same.
>
> Just wanted
On 2020-05-25 6:39 p.m., uday kiran pichika wrote:
> Thanks for your quick check Michel. I had removed the condition in my local
> source in ms_present_check_unflip() method and moved the assignment to
> ms_present_check_flip() method. Below is the snippet.
>
> static Bool
Thanks for your quick check Michel. I had removed the condition in my local
source in ms_present_check_unflip() method and moved the assignment to
ms_present_check_flip() method. Below is the snippet.
static Bool ms_present_check_flip(RRCrtcPtr crtc,
WindowPtr window,
From: Anthony Koo
[Why]
We want to better encapsulate all driver-fw dependencies into a single
file.
[How]
Combine all the headers under inc folder into a single header
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
From: David Galiffi
[WHY]
To facilitate DM removing the dependency between dc and the firmware
binary.
[HOW]
Setting the default values to match VBIOS: 64 KB. These values are only
used if meta is absent.
Signed-off-by: David Galiffi
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
From: Dmytro Laktyushkin
Current implementation is slightly inaccurate and will often
result in truncation/floor operation decrementing an exact
integer output by 1.
Only rounded down output is ever expected, just extract the fp
exponent for this to increase performance and avoid any
truncation
From: Aric Cyr
[Why]
Link loss currently only retrains and re-enables the stream. This can
cause issues for some sinks.
[How]
When link loss occurs, the link and stream(s) should be completely
disabled and then reenabled.
Signed-off-by: Aric Cyr
Reviewed-by: Wenjing Liu
Acked-by: Qingqing
From: Aric Cyr
[Why]
There are scenarios where no OPP is assigned to an OTG so its value is
0xF which is outside the size of the OPP array causing a potential
driver crash.
[How]
Change the assert to an early return to guard against access. If
there's no OPP assigned already, then OTG will be
From: Hugo Hu
[why]
We hit an issue which driver reallocate a pipe from desktop bottom
pipe to video bottom pipe. In this case, driver need to re-enable
plane.
[how]
Enable plane if container of plane status changed.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
From: Alvin Lee
[Why]
When determining synchronzied vblank we don't need to compare the stream
with itself
[How]
If comparing same stream, continue to next iteration
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
This DC patchset brings improvements in multiple areas.
In summary, we have:
* Fixes on HDCP, eDP, etc.
* Enhancements on interrupt handling, code security and others.
---
Alvin Lee (2):
drm/amd/display: Disable PG on NV12
From: Paul Hsieh
[Why]
Unit enter to S4, garbage show on screen when do OPTC blank.
[How]
Wait for vblank then do OPTC blank
Signed-off-by: Paul Hsieh
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
1 file changed, 3
From: Bhawanpreet Lakha
[Why]
Previously we used link signal type to get the caps. We should use the
sink signal type
[How]
Use sink signal type instead of link signal type
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Anthony Koo
[Header Changes]
- Combine all interface dependencies between driver and fw into a
single header file
- Add FW Versioning to the dmub_cmd.h file
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
From: Paul Hsieh
[Why]
The link_status is incorrect cause driver power off eDP when backlight
on. Some eDP panels may show garbage on screen.
[How]
Correct link_status when power off encoder
Signed-off-by: Paul Hsieh
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
From: Eric Bernstein
[Why]
Diagnostics DIO test with eDP not connected is required to run
[How]
Allow Diagnostics test with eDP not connected to skip link detection but
still execute DIO test
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
From: Aric Cyr
[Why]
If VUPDATE_END is before VUPDATE_START the delay calculated can become
very large, causing a soft hang.
[How]
Take the absolute value of the difference between START and END.
Signed-off-by: Aric Cyr
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
From: Alvin Lee
[Why]
HW team request to disable PG on NV12 (fixing missed cases)
[How]
Disable dpp and hubp PG
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 +-
1 file changed, 5 insertions(+), 1
If a user mode driver is changed to rely on the existence of implicit sync,
it results in corruption and flickering as reported here:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/2950
Marek
On Mon, May 25, 2020 at 6:05 PM Marek Olšák wrote:
> Hi Christian,
>
> Bas and Michel wanted to
Hi Christian,
Bas and Michel wanted to discuss this. The main disadvantage of no implicit
(pipeline) sync within the same queue is that we get lower performance and
lower GPU utilization in some cases.
We actually never really needed the kernel to have implicit sync, because
all user mode
[AMD Official Use Only - Internal Distribution Only]
Thanks Yong.
I get your point. But you know some of those APIs are called by other IPs(like
smu_get_clock_by_type_with_latency called by DAL in amdgpu_dm_pp_smu.c).
And caller need to know whether the SMU ip added or even whether the interface
GCC 10 was complaining about how we append data to a buffer using snprintf:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c: In function ‘perf_show’:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:214:3: warning: ‘snprintf’
argument 4 overlaps destination object ‘buf’ [-Wrestrict]
214
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