During reboot test on arm64 platform, it may failure
on boot.
The error message are as follows:
[6.996395][ 7] [ T295] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR*
late_init of IP block failed -22
[7.006919][ 7] [ T295] amdgpu :04:00.0:
During reboot test on arm64 platform, it may failure
on boot.
The error message are as follows:
[6.996395][ 7] [ T295] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR*
late_init of IP block failed -22
[7.006919][ 7] [ T295] amdgpu :04:00.0:
> -Original Message-
> From: amd-gfx On Behalf Of
> Zhenneng Li
> Sent: Friday, March 10, 2023 3:40 PM
> To: Deucher, Alexander
> Cc: David Airlie ; Pan, Xinhui ;
> linux-ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; Zhenneng Li
> ; amd-gfx@lists.freedesktop.org; Daniel
From: Alvin Lee
[Description]
- For pipe harvesting cases we must use DPP inst instead of
pipe index for DPP related programming
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 38 ++-
From: Mustapha Ghaddar
[WHY]
To validate the BW used for DPIAs per HostRouter
[HOW]
Add the Validate function in C source file
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Mustapha Ghaddar
---
.../dc/link/protocols/link_dp_dpia_bw.c | 34 +++
From: Fangzhi Zuo
8b/10b encoding needs to add 3% fec overhead into the pbn.
In the Synapcis Cascaded MST hub, the first stage MST branch device
needs the information to determine the timeslot count for the
second stage MST branch device. Missing this overhead will leads to
insufficient timeslot
From: Wesley Chalmers
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
Cc: sta...@vger.kernel.org
Cc: Mario Limonciello
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Wesley Chalmers
---
From: Robin Chen
[Why]
This is the fix for the defect of commit 11ec7d8f2263
("drm/amd/display: Allow individual control of eDP hotplug support").
[How]
To revise the default eDP hotplug setting and use the enum to git rid
of the magic number for different options.
Fixes: 11ec7d8f2263
From: Ayush Gupta
[Why]
Framedrops are observed while playing Vp9 and Av1 10 bit
video on 8k resolution using VSR while playback controls
are disappeared/appeared
[How]
Now ODM 2 to 1 is disabled for 5k or greater resolutions on VSR.
Cc: sta...@vger.kernel.org
Cc: Mario Limonciello
From: Cruise Hung
[Why]
In USB4 DP tunneling, it's possible to have this scenario that
the path becomes unavailable and CM tears down the path a little bit late.
So, in this case, the HPD is high but fails to read any DPCD register.
That causes the link connection type to be set to sst.
And not
Hi Christian
On 2/28/23 09:33, Christian König wrote:
This adds the infrastructure for an execution context for GEM buffers
which is similar to the existinc TTMs execbuf util and intended to replace
it in the long term.
The basic functionality is that we abstracts the necessary loop to lock
On Fri, 10 Mar 2023, Guchun Chen wrote:
> In order to catch issues in other drivers to ensure proper call
> sequence of polling function.
>
> v2: drop Fixes tag in commit message
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2411
> Reported-by: Bert Karwatzki
> Suggested-by: Dmitry
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- FW Release 0.0.158.0
- Fixes to HDCP, DP MST and more
- Improvements on USB4 links and more
- Code re-architecture on link.h
Cc: Daniel Wheeler
Alvin Lee (1):
drm/amd/display: Use DPP inst instead of pipe idx
From: Bhawanpreet Lakha
[Why]
On resume some displays are not ready for HDCP, so they will fail if we
start the hdcp authentintication too soon.
Add a delay so that the displays can be ready before we start.
NOTE: Previoulsy this delay was set to 3 seconds but it was causing
issues with
From: Zhikai Zhai
[WHY]
The VBIOS select the black boundary mode when using auto
scale mode. But it doesn't recover if there is no reset.
[HOW]
Clean the scaler boundary mode to default edge in the manual
scale mode.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by:
On 3/9/2023 3:42 PM, Luís Mendes wrote:
Hi,
Ping? This is actually a regression.
If there is no one available to work this, maybe I can have a look in
my spare time, in accordance with your suggestion.
Regards,
Luís
On Tue, Jan 3, 2023 at 8:44 AM Christian König wrote:
Am 25.12.22 um
From: Saaem Rizvi
[WHY]
Hot plugging and then hot unplugging leads to k1 and k2 values to
change, as signal is detected as a virtual signal on hot unplug. Writing
these values to OTG_PIXEL_RATE_DIV register might cause primary display
to blank (known hw bug).
[HOW]
No longer write k1 and k2
From: Wenjing Liu
[Why & How]
All dc subcomponents should call another dc component via function pointers
stored in a component structure. This is part of dc coding convention since
the beginning. The reason behind this is to improve encapsulation and
polymorphism. The function contract is
From: Fangzhi Zuo
Traditional synaptics hub has one MST branch device without virtual dpcd.
Synaptics cascaded hub has two chained MST branch devices. DSC decoding
is performed via root MST branch device, instead of the second MST branch
device.
Reviewed-by: Hersen Wu
Acked-by: Qingqing Zhuo
From: Swapnil Patel
[why]
Currently if invalid luminescence range is reported in edid,
then the driver doesn't have default range to fallback to.
[How]
Add default range if, the range is 0.
Reviewed-by: Roman Li
Acked-by: Qingqing Zhuo
Signed-off-by: Swapnil Patel
---
From: Aric Cyr
This version brings along the following:
- FW Release 0.0.158.0
- Fixes to HDCP, DP MST and more
- Improvements on USB4 links and more
- Code re-architecture on link.h
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
From: Samson Tam
[Why]
For dual displays where pixel rate is much higher on one display,
we may get underflow when DET is evenly allocated.
[How]
Allocate less DET segments for the lower pixel rate display and
more DET segments for the higher pixel rate display
Reviewed-by: Alvin Lee
From: Samson Tam
[Why & How]
Reversed assert condition when checking that phy_pix_clk[] is not 0
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Stylon Wang
[Why]
The log "DMUB HPD callback" is crucial to identify when DP tunneling
is been established and driver is notified of this event from DMUB.
Same log is shared for long and short hotplug event and we need to
check trailing DC debug log to distinguish between them two, making
From: Anthony Koo
[Why & How]
Add boot control bit to control dispclk and dppclk deep sleep
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Wesley Chalmers
[Why & How]
Make DCN32 functions available for more DCNs.
Reviewed-by: Chris Park
Acked-by: Qingqing Zhuo
Signed-off-by: Wesley Chalmers
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 8
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h | 13
On 2023-03-08 21:27, YuBiao Wang wrote:
> v2: Add comments to clarify in the code.
>
> [Why]
> For engines not supporting soft reset, i.e. VCN, there will be a failed
> ib test before mode 1 reset during asic reset. The fences in this case
> are never signaled and next time when we try to free
On 3/9/23 14:30, Hamza Mahfooz wrote:
We should be checking if drm_dp_dpcd_read() returns the size that we are
asking it to read instead of just checking if it is greater than zero.
Also, we should WARN_ON() here since this condition is only ever met, if
there is an issue worth investigating.
[Why]
Firmware Assisted Memclk Switching enables lowering mclk using DMCUB
when it cannot be normally done due to not having enough time within
vblank. FAMS extends vblank on monitors that support variable refresh
rate thereby allowing enough time to do an mclk switch sequence
during vblank.
When
On Thu, Mar 09, 2023 at 04:30:27PM -0500, Hamza Mahfooz wrote:
> We should be checking if drm_dp_dpcd_read() returns the size that we are
> asking it to read instead of just checking if it is greater than zero.
> Also, we should WARN_ON() here since this condition is only ever met, if
> there is
[Why]
Provides description for some enums used by DMCUB
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
--
Brandi B Gulbin
On 3/10/23 01:43, Shirish S wrote:
[Why]
Currently there aren't any methods to determine PSR state residency.
[How]
create a sysfs entry for reading residency and internally hook it up
to existing functionality of reading PSR residency from firmware.
Signed-off-by: Shirish S
Applied,
On 3/10/23 12:48, Aurabindo Pillai wrote:
[Why]
Firmware Assisted Memclk Switching enables lowering mclk using DMCUB
when it cannot be normally done due to not having enough time within
vblank. FAMS extends vblank on monitors that support variable refresh
rate thereby allowing enough time to
On 3/9/23 13:18, Rodrigo Siqueira wrote:
Since DC version 3.2.226, DC started to use a new internal commit
sequence that better deals with hardware limitations. Usually, DC adopts
split pipe dynamics to improve the display bandwidth and, in some cases,
to save power. This commit sets
On Fri, Mar 10, 2023 at 3:18 AM Chen, Guchun wrote:
>
>
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Zhenneng Li
> > Sent: Friday, March 10, 2023 3:40 PM
> > To: Deucher, Alexander
> > Cc: David Airlie ; Pan, Xinhui ;
> > linux-ker...@vger.kernel.org;
[AMD Official Use Only - General]
I recall that there was a previous discussion around this and that time we
found that the range is already set earlier during DPM enablement.
The suspected root cause was enable/disable of thermal alert within this call
to set range again.
Thanks,
Lijo
On Fri, Mar 10, 2023 at 07:48:04PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 09, 2023 at 04:30:27PM -0500, Hamza Mahfooz wrote:
> > We should be checking if drm_dp_dpcd_read() returns the size that we are
> > asking it to read instead of just checking if it is greater than zero.
> > Also, we
Reviewed-by: Alex Deucher
On Fri, Mar 10, 2023 at 1:57 PM Xiaogang.Chen wrote:
>
> From: Xiaogang Chen
>
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c: In function
> ‘svm_migrate_copy_to_vram’:
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c:393:1: warning: label
> ‘out’ defined
We should be checking if drm_dp_dpcd_read() returns the size that we are
asking it to read instead of just checking if it is greater than zero.
So, compare the return value of drm_dp_dpcd_read() to the requested
read size.
Signed-off-by: Hamza Mahfooz
---
v2: drop the WARN_ON().
---
[AMD Official Use Only - General]
Reviewed-by: Bhawanpreet Lakha
From: amd-gfx on behalf of Aurabindo
Pillai
Sent: March 10, 2023 12:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Pillai, Aurabindo
; Siqueira, Rodrigo ;
Mahfooz, Hamza
[AMD Official Use Only - General]
Reviewed-by: Bhawanpreet Lakha
From: amd-gfx on behalf of Aurabindo
Pillai
Sent: March 10, 2023 12:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Siqueira, Rodrigo
; Mahfooz, Hamza
Subject: Re: [PATCH 2/2]
From: Xiaogang Chen
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c: In function
‘svm_migrate_copy_to_vram’:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c:393:1: warning: label ‘out’
defined but not used [-Wunused-label]
393 | out:
| ^~~
Hi Hans,
Which AMD device do you have available for testing this series?
P.s.: If you have a new version of this series, could you also Cc me?
Thanks for your patchset.
Siqueira
On 3/8/23 14:58, Hans de Goede wrote:
Hi All,
Here is version 2 of my patch series to pass the proper parent
On 3/10/23 14:16, Felix Kuehling wrote:
> +static inline void kfd_flush_tlb(struct kfd_process_device *pdd,
>enum TLB_FLUSH_TYPE type)
Whitespace damage?
Regards,
Daniel
This will make it possible for amdgpu GEM ioctls to flush TLBs on compute
VMs.
This removes VMID-based TLB flushing and always uses PASID-based
flushing. This still works because it scans the VMID-PASID mapping
registers to find the right VMID. It's only slightly less efficient. This
is not a
Use dummy command submissions with a 0-sized IB on a compute VM to flush
TLBs and signal the fence in SW. This allows applications with user mode
queues to sync with asynchronous VM updates through the CS API.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 24469a0e5052ba01a35a15f104717a82b7a4798b Add linux-next specific
files for 20230310
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202302111601.jty4lkra-...@intel.com
https
> -Original Message-
> From: Jani Nikula
> Sent: Friday, March 10, 2023 8:05 PM
> To: Chen, Guchun ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Deucher,
> Alexander ; Zhang, Hawking
> ; dmitry.barysh...@linaro.org;
> spassw...@web.de; m...@fireburn.co.uk
> Cc:
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