[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, February 22, 2024 10:49 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Kim, Jonathan ;
> Poag, Charis ; Cheung, Donald
> ; Yat Sin, David ;
> Chaudhary, Jatin Jaikishan
> Subject:
In a future commit, the cwsr trap handler code size for gfx10.1 will
increase to slightly above the one page mark. Since the TMA does not
need to be page aligned, and only 2 pointers are stored in it, push
the TMA offset by 2 KiB and keep the TBA+TMA reserved memory size
to two pages.
On 2024-02-23 08:42, Shashank Sharma
wrote:
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve
[AMD Official Use Only - General]
Reviewed By Zhigang Luo mailto:zhigang@amd.com>>
From: Lu, Victor Cheng Chi (Victor)
Sent: Friday, February 16, 2024 1:50 PM
To: Luo, Zhigang
Subject: Fw: [PATCH 2/4] drm/amdgpu: Do not program SQ_TIMEOUT_CONFIG in SRIOV
[AMD Official Use Only -
On 2024-02-23 11:04, Michel Dänzer wrote:
> On 2024-02-23 10:34, Christian König wrote:
>> Am 23.02.24 um 09:11 schrieb Michel Dänzer:
>>> On 2024-02-23 08:06, Christian König wrote:
Am 22.02.24 um 18:28 schrieb Michel Dänzer:
> From: Michel Dänzer
>
> Pinning the BO storage to
Similarly to gfx9, gfx10.1 drops vector stores when an xnack error is
raised. To work around this issue, use scalar stores instead of vector
stores when trapsts.xnack_error == 1.
Signed-off-by: Laurent Morichetti
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 543 --
On Fri, Feb 23, 2024 at 4:20 AM Ma Jun wrote:
>
> It's unreasonable to use 0 as the power1_min_cap when
> OD is disabled. So, use the same lower limit as the value
> used when OD is enabled.
>
> Signed-off-by: Ma Jun
Fixes: 1958946858a6 ("drm/amd/pm: Support for getting power1_cap_min value")
On Fri, Feb 23, 2024 at 4:48 AM Pierre-Eric Pelloux-Prayer
wrote:
>
> Using the ring_muxer without preemption adds overhead for no
> reason since mcbp cannot be triggered.
>
> Moving back to a single queue in this case also helps when
> high priority app are used: in this case the gpu_scheduler
>
On Thu, Feb 22, 2024 at 9:48 PM Prike Liang wrote:
>
> Currently, GPU resets can now be performed successfully on the Raven
> series. While GPU reset is required for the S3 suspend abort case.
> So now can enable gpu reset for S3 abort cases on the Raven series.
>
> Signed-off-by: Prike Liang
On 2024-02-23 14:05, Laurent Morichetti wrote:
In a future commit, the cwsr trap handler code size for gfx10.1 will
increase to slightly above the one page mark. Since the TMA does not
need to be page aligned, and only 2 pointers are stored in it, push
the TMA offset by 2 KiB and keep the
This ensures that the memory mapped by ioremap for adev->rmmio, is
properly handled in amdgpu_device_init(). If the function exits early
due to an error, the memory is unmapped. If the function completes
successfully, the memory remains mapped.
Fixes the below:
Missing break statement in the ATOM_ARG_IMM case of a switch statement,
adds the missing break statement, ensuring that the program's control
flow is as intended.
Fixes the below:
drivers/gpu/drm/amd/amdgpu/atom.c:323 atom_get_src_int() warn: ignoring
unreachable code.
Fixes: d38ceaf99ed0
Refactors the dml32_TruncToValidBPP function by removing a
redundant return statement.
The function previously had a return statement at the end that was
never executed because all execution paths in the function ended with
a return statement before this line.
Fixes the below:
logical operator in a condition check in the get_meta_and_pte_attr
function bitwise AND operator '&' was used in an 'if' statement, but the
logical AND operator '&&' was likely intended.
The condition check was changed from:
if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert)
to
pipe_ctx->plane_res.mpcc_inst is of a type that can only hold values
between 0 and 255, so it's always greater than or equal to 0.
Thus the condition 'pipe_ctx->plane_res.mpcc_inst >= 0' was always true
and has been removed.
Fixes the below:
On 2024-02-23 08:06, Christian König wrote:
> Am 22.02.24 um 18:28 schrieb Michel Dänzer:
>> From: Michel Dänzer
>>
>> Pinning the BO storage to VRAM for scanout would make it inaccessible
>> to non-P2P dma-buf importers.
>
> Thinking more about it I don't think we can do this.
>
> Using the BO
[AMD Official Use Only - General]
This patch is :
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: Huang, Tim
Sent: Friday, February 23, 2024 2:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH]
Implement it for gfxhub 1.0 and 1.2.
v2: input logical xcc id for poison query interface.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 17 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 15
Add UCE and FED bit definitions.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
Replace it with related interface in gfxhub functions.
v2: replace node id with xcc id.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 1 -
Obtain it from ring entry.
v2: replace node id with logical xcc id.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c | 14 --
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 14 --
2 files changed, 24 insertions(+), 4 deletions(-)
diff
Let kfd interrupt handler process it.
v2: return 0 instead of 1 for fed error.
drop the usage of strcmp in interrupt handler.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
Hi,
MUTTER_SYNC=0/1 complains, client/server and both?
example:
xorg_xfree_server((mutter_sync[0]) +
steam_linux_client(listening_local_server)) + game(x)
xorg_xfree_server((mutter_sync[1]) +
steam_linux_client(listening_local_server)) + game (x)
wayland_mutter_sync((0)
In the header file dc/dcn301/dcn301_dccg.h, the function dccg301_create
is declared twice, so remove duplication.
Signed-off-by: David Tadokoro
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h | 6 --
1 file changed, 6 deletions(-)
diff --git
It's unreasonable to use 0 as the power1_min_cap when
OD is disabled. So, use the same lower limit as the value
used when OD is enabled.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 9 -
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 9
Using the ring_muxer without preemption adds overhead for no
reason since mcbp cannot be triggered.
Moving back to a single queue in this case also helps when
high priority app are used: in this case the gpu_scheduler
priority handling will work as expected - much better than
ring_muxer with its
On 2024-02-23 09:11, Michel Dänzer wrote:
> On 2024-02-23 08:06, Christian König wrote:
>>
>> So rejecting things during CS and atomic commit is the best thing we can do.
>
> It's problematic for a Wayland compositor:
>
> The CS ioctl failing is awkward. With GL, I'm pretty sure it means the
>
Am 23.02.24 um 09:11 schrieb Michel Dänzer:
On 2024-02-23 08:06, Christian König wrote:
Am 22.02.24 um 18:28 schrieb Michel Dänzer:
From: Michel Dänzer
Pinning the BO storage to VRAM for scanout would make it inaccessible
to non-P2P dma-buf importers.
Thinking more about it I don't think we
Am 23.02.24 um 10:19 schrieb Ma Jun:
It's unreasonable to use 0 as the power1_min_cap when
OD is disabled. So, use the same lower limit as the value
used when OD is enabled.
Signed-off-by: Ma Jun
Acked-by: Christian König
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 9
On 2024-02-23 10:34, Christian König wrote:
> Am 23.02.24 um 09:11 schrieb Michel Dänzer:
>> On 2024-02-23 08:06, Christian König wrote:
>>> Am 22.02.24 um 18:28 schrieb Michel Dänzer:
From: Michel Dänzer
Pinning the BO storage to VRAM for scanout would make it inaccessible
to
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve this by moving the TLB flush into a DMA-fence object which
can be used to delay the
From: Christian König
The callback we installed for the SDMA update were actually pretty
horrible. since we now have seq64 use that one and HW seq writes
instead.
V2:(Shashank)
- rebased on amd-drm-staging-next
- changed amdgpu_seq64_gpu_addr
Cc: Christian König
Cc: Alex Deucher
Cc: Felix
This patch:
- adds a new list in amdgou_vm to hold the VM PT entries being freed
- waits for the TLB flush using the vm->tlb_flush_fence
- actually frees the PT BOs
V2: rebase
V3: Do not attach the tlb_fence to the entries, rather add the entries
to a list and delay their freeing (Christian)
33 matches
Mail list logo
