Clear build warning: suggest explicit braces to avoid ambiguous
‘else’ [-Wparentheses]. Introduced by commits:
bc0123e4f0d8d072a3144e7662846c5221245dc3
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 de
Hi Leo,
Sure, I will reset 0 in header file
Thanks!
James Zhu
On 2017-10-05 11:39 AM, Leo Liu wrote:
On 10/05/2017 11:24 AM, James Zhu wrote:
In uvd encode parameter package, parameters input_pic_luma_pitch and
input_pic_chroma_pitch should be picture width align with hardware
alignment
-by: James Zhu <james@amd.com>
---
tests/amdgpu/uvd_enc_tests.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
index 7518103..bbda131 100644
--- a/tests/amdgpu/uvd_enc_tests.c
+++ b/tests/amdgpu/uvd_enc_t
Query hardware IP information to find out if there are uvd encode rings
ready for use in kernel driver.
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/uvd_enc_tests.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/tests/
-by: James Zhu <james@amd.com>
---
tests/amdgpu/uvd_enc_tests.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
index 7518103..bbda131 100644
--- a/tests/amdgpu/uvd_enc_tests.c
+++ b/tests/amdgpu/uvd_enc_t
Query hardware IP information to find out if there are uvd encode rings
ready for use in kernel driver.
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/uvd_enc_tests.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/tests/
Add new UVD encode ring methods get/set/emit/flush/sync to support uvd6.3 HEVC
encoding
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 117 ++
1 file changed, 117 insertions(+)
diff --git a/drivers/gpu/drm/amd/
These patches add headers/rings/test_cases/IRQs to support uvd6.3 HEVC
encode in amdgpu
Signed-off-by: James Zhu <james@amd.com>
---
James Zhu (9):
drm/amdgpu: add uvd enc registers in header
drm/amdgpu: add uvd enc command in header
drm/amdgpu: add new uvd enc ring methods
Generate create/destroy messages to test UVD encode indirect buffer function.
And enable UVD encode IB test during device initialization.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 172 ++
1 file change
Add UVD encode ring test functions. And enable UVD encode ring test
during UVD encode hardware initialization.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 55 ++-
1 file changed, 54 insertions(+), 1 deletion(-)
UVD 6.3 has two UVD encode rings. Add the ring structures and initialize the
hw ring buffers.
Currently only ASIC Polaris10/11/12 uses UVD6.3 encode engine on HEVC encoding.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.
Add UVD encode ring vm functions to handle frame ecoding.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 43 ++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_
Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_r
Add UVD encode command interface definition for uvd6.3 HEVC encoding
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vid.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index a
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index f4f56c9..26b5ef4 100644
--- a/drivers/gpu/drm/amd/
Add UVD encode IRQ handle and enable the UVD encode trap
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 40 +--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_
Hi Christian, leo,
Thanks for comments. I will correct them accordingly.
Best Regards!
James Zhu
On 2017-10-02 11:59 AM, Leo Liu wrote:
On 10/02/2017 11:56 AM, Christian König wrote:
Some minor nit picks on patch #4 and #9, but apart from that it looks
good to me.
With those fixed
Reviewed-by: James Zhu <james@amd.com>
On 2018-05-17 06:36 PM, Alex Deucher wrote:
Take the encode rings into account in the idle work handler.
v2: fix typo: s/num_uvd_inst/num_enc_rings/
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/dr
Reviewed-by: James Zhu <james@amd.com>
On 2018-05-17 06:36 PM, Alex Deucher wrote:
Current multi-UVD hardware uses a single clock and power source
so handle all instances in the idle handler.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/dr
Reviewed-by: James Zhu <james@amd.com>
On 2018-05-17 06:36 PM, Alex Deucher wrote:
This reverts commit 4f7b8507bb4ba19f994e0d72eedd6029961be402.
We don't need separate idle work handles for UVD 7.2. Both instances are
driven by the same clock and power.
Signed-off-by: Alex D
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for decode interface minor
[7, 0] for hardware family id
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 15 +--
1
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for decode interface minor
[7, 0] for hardware family id
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 21
On 2018-06-07 03:10 AM, Christian König wrote:
Am 06.06.2018 um 20:59 schrieb James Zhu:
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for firmware revision
[7, 0] for hardware family id
On 2018-06-07 08:38 AM, Leo Liu wrote:
On 06/07/2018 03:10 AM, Christian König wrote:
Am 06.06.2018 um 20:59 schrieb James Zhu:
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for firmware
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for firmware revision
[7, 0] for hardware family id
Inside kernel log UVD firmware Version: 1.1.2 (denote major.minor.revision)
Signed-off-by: James Zhu
All UVD instanses have only one dpm control, so it is better
to share one idle_work handle.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git
+Peter
On 2018-06-14 11:51 AM, Leo Liu wrote:
On 06/14/2018 11:29 AM, Alex Deucher wrote:
The uvd version information was not set correctly for vega20.
Rearrange the logic to set it correctly and fix the warnings
as a result.
Fixes: 7b3c773f405 (drm/amdgpu/vg20:support new UVD FW version
On 2018-06-13 04:45 PM, Alex Deucher wrote:
On Tue, Jun 12, 2018 at 11:46 AM, James Zhu wrote:
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for decode interface minor
[7, 0] for hardware
Fixes: 10dd74eac4db ("drm/amdgpu/vg20:Restruct uvd.inst to support multiple
instances")
Cc: James Zhu
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for firmware revision
[7, 0] for hardware family id
Inside kernel log UVD firmware Version: 1.1.2 (denote major.minor.revision)
Signed-off-by: James Zhu
.
Hi Timothy,
From design of view, it is not right to just change
AMDGPU_MAX_UVD_INSTANCES to 3.
Could you tell me some detail of UBSAN test and attach the dmesg also?
thanks!
James Zhu
Signed-off-by: Timothy Pearson
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 2 +-
1 file changed, 1
On 2018-06-25 04:19 PM, Leo Liu wrote:
[3.866656] index 2 is out of range for type 'amdgpu_uvd_inst [2]'
[3.87] CPU: 0 PID: 59 Comm: kworker/0:1 Not tainted 4.16.0-rc7+ #3
[3.866677] Hardware name: Gigabyte Technology Co., Ltd.
GA-990FXA-UD7/GA-990FXA-UD7, BIOS F9 06/08/2012
[
num_uvd_inst = 1;*
I didn't know when ring->me is set to 2. Maybe there is some leakage
somewhere.
Best regards!
James zhu
On 2018-06-25 01:29 PM, Deucher, Alexander wrote:
Odd. The structure should be 0 initialized. Does this patch help?
Alex
On 2018-06-25 02:53 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 2:37 PM, James Zhu wrote:
For one UVD instance case,:
In function amdgpu_driver_load_kms, all ring->me should be set to zero.
adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
For two UVD instances ca
On 2018-06-25 03:02 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 2:59 PM, James Zhu wrote:
On 2018-06-25 02:53 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 2:37 PM, James Zhu wrote:
For one UVD instance case,:
In function amdgpu_driver_load_kms, all ring->me should be set to z
On 2018-06-25 04:32 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 4:26 PM, James Zhu wrote:
On 2018-06-25 04:02 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 3:17 PM, Leo Liu wrote:
[3.866656] index 2 is out of range for type 'amdgpu_uvd_inst [2]'
[3.87] CPU: 0 PID: 59
NC also:
if ( ring->funcs->type != AMDGPU_RING_TYPE_UVD &&
ring->funcs->type != AMDGPU_RING_TYPE_UVD_ENC ) {
After this, this patch is Reviewed-by: James Zhu
James
ring->fence_drv.cpu_addr = >wb.wb[ring->fence_offs];
naming convention is present.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 3f2a5e73
Reviewed-by: James Zhu for the series
On 2018-06-25 01:42 PM, Alex Deucher wrote:
Set the me instance in early init and use that rather than
calculating the instance based on the ring pointer.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 55 +++
1 file changed, 23 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 612455d..3
Add Polaris version check if firmware support UVD encode
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uv
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22ef..612455d 100644
--- a/drivers/gpu/d
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 38 ++---
2 files changed, 40 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f1a5bd..5b39d13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 08e3857..edb7baf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b
Hi Alex
Sure, I will send out V2 with the fix.
thanks!
James Zhu
On 2018-08-09 11:48 AM, Alex Deucher wrote:
On Thu, Aug 9, 2018 at 11:41 AM, James Zhu wrote:
Signed-off-by: James Zhu
Please include a commit message. E.g.,
Track the TMR address for VCN PSP firmware loading
From: Feifei Xu
With PSP firmware loading, TMR mc address is supposed to be used.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd
From: Evan Quan
Added psp fw loading support for vega20 2nd UVD instance.
Change-Id: Ib1eeeb1308641c0d64ca2f8f465f17c567434c68
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 3 ++-
With PSP firmware loading, TMR mc address is supposed to be used.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
PSP engine only allocate space for firmware.
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH is for firmware TMR address.
The other two address are for HEAP/Session.
Regards!
James Zhu
On 2018-08-13 12:16 AM, Quan, Evan wrote:
Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new
From: Likun Gao
Add the new firmware id for VCN into the enum
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu
From: Likun Gao
Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 38
Update tmr mac address with firmware loading address
which is returned from PSP firmware
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers
amdgpu IP blocks booting need Trust Memory Region(tmr) mac address
of its firmware which is loaded by PSP
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Likun Gao
Add VCN support in PSP driver
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 0ff136d
On 2018-07-18 10:11 AM, Christian König wrote:
Am 18.07.2018 um 15:40 schrieb James Zhu:
On 2018-07-18 08:55 AM, Christian König wrote:
Going to completely rework the context to ring mapping with Nayan's
GSoC
work, but for now just stopping to expose the second UVD instance
should
do
Hi Christian,
Sure, Let me find a time to try this afternoon.
Best Regards!
James Zhu
On 2018-07-25 08:18 AM, Christian König wrote:
Hi James,
can you give those two patches another try on a Vega20? At least in
theory it should work now.
Thanks in advance,
Christian.
Am 25.07.2018 um
Yes, it works great.
Reviewed-by: James Zhu
Tested-by: James Zhu for the series
On 2018-07-25 07:05 AM, Christian König wrote:
We are going to need that for the second UVD instance on Vega20.
v2: rename to patch_cs_in_place
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu
lace. With this fix,
Reviewed-by: James Zhu
James
.emit_frame_size =
6 + /* hdp invalidate */
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On 2018-07-23 05:53 PM, Alex Deucher wrote:
Properly handle cases where one or more instance of the IP
block may be harvested.
v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 -
This patch is James Zhu
On 2018-07-25 05:02 PM, Alex Deucher wrote:
Properly handle cases where one or more instance of the IP
block may be harvested.
v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
v3: rebase on Christian's UVD changes, drop unused var
Signed-off-by: Alex
Missing out the RB,
Reviewed-by: James Zhu
On 2018-07-25 05:29 PM, Alex Deucher wrote:
On Wed, Jul 25, 2018 at 5:26 PM, James Zhu wrote:
This patch is James Zhu
Is that an RB or an AB or?
Alex
On 2018-07-25 05:02 PM, Alex Deucher wrote:
Properly handle cases where one or more
On 2018-07-18 08:55 AM, Christian König wrote:
Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13
Signed-off-by: James Zhu
Add error message when register failed to reach expected value, It will
help discover potential issue.
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
b/drivers/gpu/drm/amd
Signed-off-by: James Zhu
When VCN PG state is unchanged, it is unnecessary to reset
power gate state again.
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd
Signed-off-by: James Zhu
Add error message when register failed to reach expected value, It will
help discover potential issue.
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
b/drivers/gpu/drm/amd
On 2018-09-11 11:36 AM, Christian König wrote:
Am 11.09.2018 um 17:29 schrieb James Zhu:
On 2018-09-11 11:17 AM, Christian König wrote:
Am 11.09.2018 um 17:06 schrieb James Zhu:
On 2018-09-11 10:44 AM, Alex Deucher wrote:
On Mon, Sep 10, 2018 at 4:34 PM James Zhu wrote:
Signed-off
On 2018-09-11 11:17 AM, Christian König wrote:
Am 11.09.2018 um 17:06 schrieb James Zhu:
On 2018-09-11 10:44 AM, Alex Deucher wrote:
On Mon, Sep 10, 2018 at 4:34 PM James Zhu wrote:
Signed-off-by: James Zhu
When VCN PG state is unchanged, it is unnecessary to reset
power gate state
On 2018-09-11 10:44 AM, Alex Deucher wrote:
On Mon, Sep 10, 2018 at 4:34 PM James Zhu wrote:
Signed-off-by: James Zhu
When VCN PG state is unchanged, it is unnecessary to reset
power gate state again.
Don't you need to initialize and store the PG state somewhere? You
are just using
When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021
Signed-off-by: James Zhu <james@amd.com>
---
drive
Max uvd handles should use adev->uvd.max_handles instead of
AMDGPU_MAX_UVD_HANDLES here.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021
Signed-off-by: James Zhu <james@amd.com>
Reviewed-b
When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021
Signed-off-by: James Zhu <james@amd.com>
Reviewed-b
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/vce_ib.h| 21 -
tests/amdgpu/vce_tests.c | 224 ++-
2 files changed, 240 insertions(+), 5 deletions(-)
diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h
index 8
On 2018-04-04 02:44 PM, Leo Liu wrote:
On 04/04/2018 12:43 PM, James Zhu wrote:
Signed-off-by: James Zhu<james@amd.com>
---
tests/amdgpu/vce_ib.h| 21 -
tests/amdgpu/vce_tests.c | 224 ++-
2 files changed, 240 insertions
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/vce_ib.h| 17
tests/amdgpu/vce_tests.c | 221 ++-
2 files changed, 235 insertions(+), 3 deletions(-)
diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h
index 8
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/vce_ib.h| 21 -
tests/amdgpu/vce_tests.c | 221 ++-
2 files changed, 237 insertions(+), 5 deletions(-)
diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h
index 8
Vega20 uses vce_4_1 engine. By hacking vega20 VCE_BASE,
vce_4_1 can reuse vce_4.0 header file.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/include/vega20_ip_offset.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/i
Motion vector packet needs support in physic mode.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/
On 2018-03-31 01:51 PM, Christian König wrote:
Am 29.03.2018 um 23:02 schrieb James Zhu:
Motion vector packet needs support in physic mode.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 24
1 file changed, 24 inse
Motion vector packet needs support in physic mode.
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/
Hi Christian,
Thanks for correction.
Since MV dump is not normal encoding, its size is HxW/8. So the 2nd
buffer size if 1/12 of the 1st one.
Thanks and Best Regards!
James Zhu
On 2018-04-03 05:11 AM, Christian König wrote:
Am 02.04.2018 um 22:27 schrieb James Zhu:
On 2018-03-31 01:51
On 2018-04-03 03:14 PM, Leo Liu wrote:
On 04/03/2018 03:02 PM, James Zhu wrote:
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/Makefile.am | 1 +
tests/amdgpu/amdgpu_test.c | 11 +
tests/amdgpu/amdgpu_test.h | 20 ++
tests/amdgpu/vce_ib.h | 21 +-
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/Makefile.am| 1 +
tests/amdgpu/amdgpu_test.c | 11 +
tests/amdgpu/amdgpu_test.h | 20 ++
tests/amdgpu/vce_ib.h | 21 +-
tests/amdgpu/vce_mv_tests.c | 537
5 files c
On 2018-04-03 04:21 PM, Leo Liu wrote:
On 04/03/2018 03:48 PM, James Zhu wrote:
On 2018-04-03 03:14 PM, Leo Liu wrote:
On 04/03/2018 03:02 PM, James Zhu wrote:
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/Makefile.am | 1 +
tests/amdgpu/amdgpu_test.c
Emit frame size should match with corresponding function,
uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write
Signed-off-by: James Zhu <james@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 +++-
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 24
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu
Add ring write/read pointer check for VCN dynamic power gate mode
stop,to make sure that no job is left in ring before turn off DPG mode.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
Add Dynamic Power Gate mode Register XX check
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index de57e6d..afc7a1d 100644
--- a/drivers
Apply new UMC enable for VNC Dynamic Power Gate mode start
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 5740cca
Set VCPU busy after gate power during vcn Static Power Gate start
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 153f23a..d8fe14d
Remove Sitatic Power Gate mode unused steps during vcn start
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 30 ++
1 file changed, 2 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu
Remove Dynamic Power Gate mode unused steps during VCN start
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 +---
1 file changed, 1 insertion(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu
Update Static Power Gate mode VCN memory control
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 624a255
Move Static Power Gate mode mc resume after MPC control
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 29f711b
Apply new UMC enable for VNC Dynamic Power Gate mode
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 93e2a40
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