automatically
If so, we need a separate patch to cleanup them in a batch.
BR,
Xiaojie
From: Christian König
Sent: Monday, July 13, 2020 4:38 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: use ARRAY_SIZE() to add amdgpu
[AMD Official Use Only - Internal Distribution Only]
The logic in sdma2.4, sdma3 and sdma4 look fine.
I sent v2 to add fix for sdma5.2 as well.
BR,
Xiaojie
From: Christian König
Sent: Tuesday, July 14, 2020 4:47 PM
To: Yuan, Xiaojie; amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Sure Tom, here it is.
BR,
Xiaojie
From: StDenis, Tom
Sent: Tuesday, July 14, 2020 10:11 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH UMR] Fix off-by-one error for decoding
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e8e70b74ea5b..dfe85a1d79a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index dfe85a1d79a5..4eb5bacb55f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_
1. no need to allocate an extra member for 'mqd_backup' array
2. backup/restore mqd to/from the correct 'mqd_backup' array slot
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +
2 files changed, 6 insertions(+),
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7e882999abad..0f7504ae2395 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v1
Hi Emily,
Thanks for catching this.
I think freeing Discovery TMR bo should be put at amdgpu_ttm_fini() instead of
amdgpu_ttm_late_init() because unlike VGA stolen bo, touching PSP-protected
Discovery TMR bo will cause GPU hang. Therefore, it should be reserved across
the life-cycle of amdgpu
Please use 'drm/amdgpu/discovery: ' prefix in commit message to let us easily
track all discovery-releated changes.
Other than this, patch is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Emily Deng
Sent: Monday, November 4, 2019 11
Hi Alex,
IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block will
be immediately powered up, so I'm not sure MMIO register access will be
successful within this time window(maybe GRBM access will be pending until gfx
block is powered up?)
If you are not in a hurry to com
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Nov 16, 2019, at 12:12 AM, Alex Deucher wrote:
>
> Ping?
>
>> On Wed, Nov 13, 2019 at 2:29 PM Alex Deucher wrote:
>>
>> Needed as a fallback if the vbios can't be fetched by other means.
>>
>> Signed-off-by: Alex Deucher
>> ---
>> drivers/gpu/drm
Yes. IIRC, some asics' amdgpu_gfx_ctrl() is implemented as synchronous (upon
function returns, gfx block is guaranteed to be in power-up state). Anyway, let
me confirm about that soon.
BR,
Xiaojie
> On Nov 16, 2019, at 12:52 AM, Alex Deucher wrote:
>
>> On Fri, Nov 15, 2019
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Nov 15, 2019, at 10:51 PM, Alex Deucher wrote:
>
> 5.4 and newer works fine with navi14.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a
lose;
printf("gb_addr_config: 0x%08x\n", gb_addr_config);
close:
close(fd);
return r;
}
BR,
Xiaojie
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Saturday, November 16, 2019 1:02 AM
To: Alex Deucher
Cc: Deucher, Alexander
Acked-by: Xiaojie Yuan
BR,
Xiaojie
From: Alex Deucher
Sent: Tuesday, November 19, 2019 1:24 AM
To: Yuan, Xiaojie
Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
From: Christian König
Sent: Tuesday, November 19, 2019 12:18 AM
To: Yuan, Xiaojie; Alex Deucher
Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: disable gfxoff when using register read
interface
Hi Xiaojie,
could you add that test to the unit tests w
this small time window, no firmware touches csb and it should prove that
vram lost causes csb corrupt.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 4:43 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack; Long, Gang
I can try this approach as well.
This csb is similar to the kiq mqd which are allocated in vram and might
corrupt after baco reset.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 4:54 PM
To: Koenig, Christian; Yuan, Xiaojie; amd-gfx
Got it.
Thanks Hawking and Chris for your attention.
BR,
Xiaojie
From: Zhang, Hawking
Sent: Wednesday, November 20, 2019 5:04 PM
To: Yuan, Xiaojie; Koenig, Christian; amd-gfx@lists.freedesktop.org
Cc: Long, Gang; Xiao, Jack; Ma, Le
Subject: RE: [PATCH
Original Message-
> From: amd-gfx On Behalf Of Yuan,
> Xiaojie
> Sent: Wednesday, November 20, 2019 5:10 PM
> To: Zhang, Hawking ; Koenig, Christian
> ; amd-gfx@lists.freedesktop.org
> Cc: Long, Gang ; Xiao, Jack ; Ma, Le
>
> Subject: Re: [PATCH] drm/amdgpu/gfx10:
Hi Monk,
hw_fini() is called in suspend code path as well. I'm wondering how csb can be
evicted if it's not unpined before suspend.
BR,
Xiaojie
> On Nov 26, 2019, at 7:50 PM, Monk Liu wrote:
>
> kernel would report a warning on double unpin
> on the csb BO because we unpin it during hw_fini
>
Signed-off-by: Xiaojie Yuan
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
BR,
Xiaojie
From: Liu, Monk
Sent: Thursday, November 28, 2019 10:53 AM
To: Yuan, Xiaojie; Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.
[AMD Official Use Only - Internal Distribution Only]
Tested on navi14 and s3/baco works fine with patch applied.
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Monk Liu
Sent: Thursday, November 28, 2019 2:57 PM
To: amd-gfx@lists.fre
Hi Evan,
Just out of curiosity, may I know what issue are you trying to fix?
I used to see vbios post failure (hangs in atombios init table) after baco exit
occasionally on navi.
BR,
Xiaojie
> On Dec 6, 2019, at 11:37 AM, Evan Quan wrote:
>
> This is needed for coming asic init on performing
Would be better to add a is-null check for 'tmp_topology' after kzalloc(). With
that fixed, patch is
Reviewed-by: Xiaojie Yuan
Regards,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Wednesday, November 7, 2018 11:29 AM
To: amd-gfx@lists.freedeskto
[AMD Official Use Only - Internal Distribution Only]
Hi Evan,
Does this patch also fix the baco failure on Navi14 with display connected?
BR,
Xiaojie
From: amd-gfx on behalf of Evan Quan
Sent: Wednesday, March 11, 2020 4:18 PM
To: amd-gfx@lists.freede
Reviewed-by: Xiaojie Yuan
From: amd-gfx on behalf of Hawking
Zhang
Sent: Sunday, May 12, 2019 11:20 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: fix -Wswitch warning due to missing of default case
[CAUTION: Exter
, Hawking; Xu,
Feifei; Yuan, Xiaojie; Long, Gang; Wang, Kevin(Yang); Yin, Tianci (Rico)
Subject: [PATCH 2/2] drm/amdgpu: remove memory training p2c buffer
reservation(V2)
From: "Tianci.Yin"
IP discovery TMR(occupied the top VRAM with size DISCOVERY_TMR_SIZE)
has been reserved, and the p2c
[AMD Official Use Only - Internal Distribution Only]
Hi Nirmoy,
Seems like documentation for struct drm_sched_entity@gpu_scheduler.h need
update as well.
BR,
Xiaojie
From: amd-gfx on behalf of Nirmoy Das
Sent: Tuesday, January 14, 2020 5:58 PM
To: am
[AMD Official Use Only - Internal Distribution Only]
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Friday, January 17, 2020 2:57 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Gao, Likun
Cc:
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Evan Quan
Sent: Monday, February 10, 2020 3:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Feb 12, 2020, at 9:53 PM, Alex Deucher wrote:
>
> Otherwise we readback all ones. Fixes rlc counter
> readback while gfxoff is active.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
> 1 file changed
Thanks Tom. I'm just publishing this quick fix so that I can continue my
debugging with umr, and your solution sounds more reasonable ; )
BR,
Xiaojie
> On Feb 14, 2020, at 10:55 PM, StDenis, Tom wrote:
>
> Hi,
>
> Thanks for the patch however since the *.i files are machine generate I'd
> r
[AMD Official Use Only - Internal Distribution Only]
Sure, I'll send v2 soon.
BR,
Xiaojie
From: StDenis, Tom
Sent: Wednesday, February 19, 2020 7:51 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH umr] fix field name
[AMD Official Use Only - Internal Distribution Only]
Thanks Tom.
BR,
Xiaojie
From: StDenis, Tom
Sent: Wednesday, February 19, 2020 8:01 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH umr v2] fix field names for
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, February 20, 2020 2:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 1 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 97605e963
gfxoff doesn't work on navi12 yet, so disable it for now
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 066ba593af23..d644669e5d93 10
s/r list in rlc firmware is ready, so remove the special autoload handling
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ps
firmware header information is printed for direct fw loading but not
added for psp fw loading yet
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 54 +
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/driv
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 35fd46bdfc53..82f6b413718b 100644
--- a/drivers/gpu/drm/am
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ++---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 1 -
drivers/gpu/drm/amd/amdg
Reviewed-by: Xiaojie Yuan
Xiaojie
> On Aug 19, 2019, at 12:00 AM, Christophe JAILLET
> wrote:
>
> '_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use
> '_navi12_ip_offset_HEADER' instead here.
>
> Signed-off-by: Chri
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:
(enab
v2: set num_types based on num_instances
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of
Thanks Alex. I've sent out patch v2.
BR,
Xiaojie
> On Aug 21, 2019, at 9:30 PM, Alex Deucher wrote:
>
>> On Wed, Aug 21, 2019 at 9:23 AM Yuan, Xiaojie wrote:
>>
>> navi1x has 2 sdma engines but commit
>> "e7b58d03b678 drm/amdgpu: reorganize sdma v4 co
The GRBM register interface is now capable of bursting 1 cycle per
register wr->wr, wr->rd much faster than previous muticycle per
transaction done interface. This has caused a problem where status
registers requiring HW to update have a 1 cycle delay, due to the
register update having to go throu
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Aug 23, 2019, at 10:45 PM, Alex Deucher wrote:
>
> So that we properly handle them on older asics.
>
> Fixes: 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm
> hub")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/a
jpeg pg depends on vcn pg
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 2d908afbf525..1970843f225f 100
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a3d99f2ddf6b..9eda82d4430e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/d
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 9eda82d4430e..384f8f512fc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/d
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Aug 28, 2019, at 9:56 PM, Alex Deucher wrote:
>
> No need to add new asic cases. This is a sw display
> implementation, so just drop the error message so when
> we add new asics, all we have to do is add the virtual
> dce IP module.
>
> Signed-off-b
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 --
4 files changed, 8 deletions(-)
diff --git a/drivers
When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an
unallocated amdgpu_firmware_info instance.
This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have
optimized out such 'defined but not referenced' variable.
[ 1120.798564] BUG: unable to handle kernel NULL poi
v2: declare as (struct common_firmware_header *) type because
struct xxx_firmware_header inherits from it
When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an
unallocated amdgpu_firmware_info instance.
This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have
Thanks Kevin. I've sent out v2 patch.
BR,
Xiaojie
From: Wang, Kevin(Yang)
Sent: Thursday, September 5, 2019 6:26 PM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: fix null pointer deref in firmware header
printing
except soc_bounding_box which is not integrated in discovery table yet
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_devi
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index ab8c92a60fc
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Sep 18, 2019, at 3:52 AM, Alex Deucher wrote:
>
> We can remove this later as things get closer to launch.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 082a0b3298a9..22406f56c818 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_
when gfxoff is enabled, applying this workaround makes sdma hang while
entering desktop.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdg
Oops, you are right Evan. I'll send another patch.
It's a little counter-intuitive that asic type id of navi12 is larger than
navi14.
BR,
Xiaojie
From: Quan, Evan
Sent: Tuesday, September 24, 2019 10:09 AM
To: Yuan, Xiaoji
when gfxoff is enabled, sdma hangs while entering desktop without this
workaround
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v1
e >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12)
||
BR,
Xiaojie
From: Quan, Evan
Sent: Tuesday, September 24, 2019 11:18 AM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking; Xiao, Jack; Yin, Tianci (Rico)
Subject
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Tuesday, September 24, 2019 4:35 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/atomfirmware: simplify the interf
Fixes: 767acabdac81 ("drm/amd/powerplay: add baco smu reset function for smu11")
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index cb3f61
Hi Alex,
This patch is to add the asic_type check which is missing after drm-next branch
rebase.
BR,
Xiaojie
From: Yuan, Xiaojie
Sent: Thursday, September 26, 2019 4:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com ; Yuan, Xiaojie
Subject
Sent: Thursday, September 26, 2019 10:20 PM
To: Alex Deucher
Cc: Deucher, Alexander ; Yuan, Xiaojie
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma'
workaround for navi
Am 26.09.2019 15:51 schrieb Alex Deucher :
On Thu, Sep 26,
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 5a34d01f7f7c..44152c1f01c7 100644
--- a/drivers/gpu/drm
SMU firmware has fix the bug, so remove this workaround.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
ind
sdma will hang once sequence number to be polled reaches 0x1000_
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index a
: Wednesday, October 9, 2019 9:35 PM
To: Yuan, Xiaojie ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan ; Feng,
Kenneth
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit
What version of firmware has the fix? Was it recently
Ping ...
BR,
Xiaojie
From: Yuan, Xiaojie
Sent: Wednesday, October 9, 2019 7:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ;
Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Yuan, Xiaojie
Subject: [PATCH 1/2] drm/amd/powerplay: add
IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 15 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/a
Thanks Alex. I'll try to use the new api and send v2 patch.
BR,
Xiaojie
From: Alex Deucher
Sent: Thursday, October 10, 2019 8:57 PM
To: Yuan, Xiaojie
Cc: amd-gfx@lists.freedesktop.org ; Xiao, Jack
; Zhang, Hawking
Subject: Re: [PATCH] drm/amdgpu/disc
IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.
Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.
v2: use DISCOVERY_TMR_SIZE macro as bo size
use amdgpu_bo_create_kernel_at() to allocate bo
Signed-off-by: Xiaojie Yuan
Reviewed-by: Hawk
Hi there,
Could someone give an RB or ACK? This patch has been verified on both navi12
and navi14.
Thanks.
BR,
Xiaojie
From: Deucher, Alexander
Sent: Thursday, October 10, 2019 8:20 PM
To: Feng, Kenneth ; Yuan, Xiaojie ;
amd-gfx@lists.freedesktop.org
Cc: Xiao
this helps to know whether the pptable is from firmware or vbios
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9883f0a
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c3f48fae6f32..339d063e24ff 100644
--- a/drivers/gpu/drm/amd/
Current SMU IF version check is too strict, driver with old smu11_driver_if.h
sometimes works fine with new SMU firmware. We prefer to see a warning instead
a error for debug purposes.
BR,
Xiaojie
From: Yuan, Xiaojie
Sent: Wednesday, June 26, 2019 2:24
Thanks Evan, got your point. Then I'll keep the patch only in our bring up
branch.
BR,
Xiaojie
From: Quan, Evan
Sent: Thursday, June 27, 2019 9:51:22 AM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Wang, Kevin(Yang)
Subject: RE: [PATCH] dr
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Monday, July 1, 2019 10:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE
Reco
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Monday, July 1, 2019 10:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/gfx10: use reset default for PA_SC_FIFO_SIZE
Rec
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Saturday, July 6, 2019 2:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/psp11: simplify the ucode register logic
Split it b
Hi Alex,
I see there are many 'auto' module params for amdgpu, could you please explain
about the historical intention of using value '-1'?
and shall we check 'amdgpu_discovery' against '-1' for all the code paths in
amdgpu_device.c and navi10_reg_init.c?
BR,
Xiaojie
__
Got it. Thanks for the explanation.
Patch is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: Deucher, Alexander
Sent: Monday, July 8, 2019 11:38 PM
To: Yuan, Xiaojie; Alex Deucher; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu: enable IP
and we might need a follow-up patch to check if (amdgpu_discovery && asic_type
>= CHIP_NAVI10) in amdgpu_device.c.
BR,
Xiaojie
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Monday, July 8, 2019 11:45 PM
To: Deucher, Alexander; Alex Deuch
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Jul 9, 2019, at 2:48 AM, Alex Deucher wrote:
>
> Use the IP discovery table rather than hardcoding the
> settings in the driver.
>
> Reviewed-by: Xiaojie Yuan
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Wednesday, July 10, 2019 11:58 PM
To: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie; Clements, John; Deucher,
Alexander
Cc: Zhang, Hawking
Subject: [PATCH 2/2] drm
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Wednesday, July 10, 2019 11:58 PM
To: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie; Clements, John; Deucher,
Alexander
Cc: Zhang, Hawking
Subject: [PATCH 1/2] drm
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Tianci Yin
Sent: Thursday, July 11, 2019 4:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack; Yuan, Xiaojie; Yin, Tianci (Rico); Zhang, Hawking
Subject: [PATCH] drm/amdgpu/discovery
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 87596c69b235..a8b526dbb6c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Saturday, July 27, 2019 3:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu/gfx10: update golden settings for navi14
Updat
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Alex Deucher
Sent: Saturday, July 27, 2019 3:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdkfd: enable KFD support for navi14
Same as navi10.
Hi Likun,
Looks like you can pin csb buffer @gfx_v8_0_hw_init() just like what following
patch does for gfx9, so that we can still use the common function
amdgpu_gfx_rlc_init_csb():
commit 137dc4b9060e99a22dce59b42ca71912cf0180f3
Author: Evan Quan
Date: Wed Jul 4 16:21:52 2018 +0800
drm
c: Deucher, Alexander ; Gao, Likun
> ; Paul Gover ; Yuan, Xiaojie
>
> Subject: [PATCH] drm/amdgpu: pin the csb buffer on hw init for gfx v8
>
> From: Likun Gao
>
> Without this pin, the csb buffer will be filled with inconsistent data after
> S3 resume. And that will
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: Tianci Yin
Sent: Monday, August 5, 2019 5:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking; Xiao, Jack; Yuan, Xiaojie; Yin, Tianci (Rico)
Subject: [PATCH] drm/amdgpu/soc15: fix external_rev_id for
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 14 +-
drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c | 14 +-
drivers/gpu/drm/amd/amdgpu/nv.c
Alex has helped to reviewed these patches in AMD internally.
Re-send them to public mail list.
Xiaojie Yuan (10):
drm/amdgpu: enable gfx clock gatings for navi12
drm/amdgpu: enable hdp clock gating for navi12
drm/amdgpu/sdma5: set sdma clock gating for navi12
drm/amdgpu: enable sdma clock
enables following gfx clock gating features:
- medium grained clock gating
- medium grained light sleep
- coarse grained clock gating
- cp memory light sleep
- rlc memory light sleep
CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it.
Signed-off-by: Xiaojie Yuan
Reviewed-by: Al
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