reboot VM.
Patch 0006 -0007: refine set clockgating code for tonga/polars.
Best Regards
Rex
-Original Message-
From: Deucher, Alexander
Sent: Tuesday, December 06, 2016 5:07 AM
To: Zhu, Rex; Alex Deucher; StDenis, Tom
Cc: amd-gfx list
Subject: RE: [PATCH] drm/amdgpu: refine pg code
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Zhu, Rex
> Sent: Friday, December 02, 2016 7:25 AM
> To: Alex Deucher; StDenis, Tom
> Cc: amd-gfx list
> Subject: RE: [PATCH] drm/amdgpu: refine pg code for gfx_
---Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com]
Sent: Thursday, December 01, 2016 11:44 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: refine pg code for gfx_v8.
On Thu, Dec 1, 2016 at 3:24 AM, Rex Zhu wrote:
> 1. bit CP_PG_DISABLE was reversed.
Pl
On Thu, Dec 1, 2016 at 3:24 AM, Rex Zhu wrote:
> 1. bit CP_PG_DISABLE was reversed.
Please split this out as a separate patch. Also, with this fixed, we
should be able to enable the AMD_PG_SUPPORT_CP flag for CZ and ST.
> 2. load RLC_SRM_INDEX_CNTL_ADDR/DATA_x pairs
>with valid addr/data.
x Zhu
Sent: Thursday, December 1, 2016 03:24
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amdgpu: refine pg code for gfx_v8.
1. bit CP_PG_DISABLE was reversed.
2. load RLC_SRM_INDEX_CNTL_ADDR/DATA_x pairs
with valid addr/data.
3. always init gfx pg.
4. delete repeated
1. bit CP_PG_DISABLE was reversed.
2. load RLC_SRM_INDEX_CNTL_ADDR/DATA_x pairs
with valid addr/data.
3. always init gfx pg.
4. delete repeated check for pg mask.
Change-Id: I9fcc8d1f79f5fa1803cb2625aa292188a656ae6b
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 85 +++
