Re: [PATCH 1/2] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"
This patch is:
Reviewed-by: Leo Liu
On 2019-08-15 2:19 p.m., Thai, Thong wrote:
> This reverts commit 69fcd7347f6fb11edc7eaea7c7b9cff0044ce17e.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +++--
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 +++--
> 2 files changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 8b43c5b21ae9..35a0a1396be7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -84,8 +84,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> case CHIP_RENOIR:
> fw_name = FIRMWARE_RENOIR;
> if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
> - (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
> - adev->asic_type != CHIP_RENOIR) /* to be removed while vcn
> psp loading works */
> + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
> adev->vcn.indirect_sram = true;
> break;
> default:
> @@ -139,8 +138,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> }
>
> bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
> - adev->asic_type == CHIP_RENOIR)
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> bo_size +=
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
> r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
> @@ -233,8 +231,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
> unsigned offset;
>
> hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
> - adev->asic_type == CHIP_RENOIR) {
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data +
> offset,
> le32_to_cpu(hdr->ucode_size_bytes));
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 84aa77470802..b12c5e57f18b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -142,8 +142,7 @@ static int vcn_v2_0_sw_init(void *handle)
> if (r)
> return r;
>
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
> - adev->asic_type != CHIP_RENOIR) {
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> const struct common_firmware_header *hdr;
> hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id =
> AMDGPU_UCODE_ID_VCN;
> @@ -360,8 +359,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
> uint32_t offset;
>
> /* cache window 0: fw */
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
> - adev->asic_type != CHIP_RENOIR) {
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> @@ -406,8 +404,7 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
> amdgpu_device *adev, bool indirec
> uint32_t offset;
>
> /* cache window 0: fw */
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
> - adev->asic_type != CHIP_RENOIR) {
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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[PATCH 1/2] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"
This reverts commit 69fcd7347f6fb11edc7eaea7c7b9cff0044ce17e.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 +++--
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 8b43c5b21ae9..35a0a1396be7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -84,8 +84,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
case CHIP_RENOIR:
fw_name = FIRMWARE_RENOIR;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
- adev->asic_type != CHIP_RENOIR) /* to be removed while vcn
psp loading works */
+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
default:
@@ -139,8 +138,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
- adev->asic_type == CHIP_RENOIR)
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
bo_size +=
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, >vcn.vcpu_bo,
@@ -233,8 +231,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
unsigned offset;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
- adev->asic_type == CHIP_RENOIR) {
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data +
offset,
le32_to_cpu(hdr->ucode_size_bytes));
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 84aa77470802..b12c5e57f18b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -142,8 +142,7 @@ static int vcn_v2_0_sw_init(void *handle)
if (r)
return r;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
- adev->asic_type != CHIP_RENOIR) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
const struct common_firmware_header *hdr;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id =
AMDGPU_UCODE_ID_VCN;
@@ -360,8 +359,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
uint32_t offset;
/* cache window 0: fw */
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
- adev->asic_type != CHIP_RENOIR) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -406,8 +404,7 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
amdgpu_device *adev, bool indirec
uint32_t offset;
/* cache window 0: fw */
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
- adev->asic_type != CHIP_RENOIR) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
--
2.17.1
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