RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
Thanks all, I am modifying the patch, and testing.
Best wishes
Emily Deng
>-Original Message-
>From: Zhu, Rex
>Sent: Thursday, August 16, 2018 2:25 PM
>To: 'Alex Deucher'
>Cc: Deng, Emily ; 'amd-gfx list' g...@lists.freedesktop.org>
>Subject: RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do
>invalidate tlb
>
>
>
>> -Original Message-
>> From: Zhu, Rex
>> Sent: Thursday, August 16, 2018 1:41 PM
>> To: 'Alex Deucher'
>> Cc: Deng, Emily ; amd-gfx list > g...@lists.freedesktop.org>
>> Subject: RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq
>> to do invalidate tlb
>>
>>
>>
>> > -Original Message-
>> > From: Alex Deucher
>> > Sent: Wednesday, August 15, 2018 10:14 PM
>> > To: Zhu, Rex
>> > Cc: Deng, Emily ; amd-gfx list > > g...@lists.freedesktop.org>
>> > Subject: Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use
>> > kiq to do invalidate tlb
>> >
>> > On Wed, Aug 15, 2018 at 9:56 AM Zhu, Rex wrote:
>> > >
>> > >
>> > >
>> > > > -----Original Message-
>> > > > From: amd-gfx On Behalf
>> > > > Of Emily Deng
>> > > > Sent: Wednesday, August 15, 2018 5:48 PM
>> > > > To: amd-gfx@lists.freedesktop.org
>> > > > Cc: Deng, Emily
>> > > > Subject: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use
>> > > > kiq to do invalidate tlb
>> > > >
>> > > > To avoid the tlb flush not interrupted by world switch, use kiq
>> > > > and one command to do tlb invalidate.
>> > > >
>> > > > v2:
>> > > > Add firmware version checking.
>> > > >
>> > > > v3:
>> > > > Refine the code, and move the firmware checking into
>> > > > gfx_v9_0_ring_emit_reg_write_reg_wait.
>> > > >
>> > > > SWDEV-161497
>> > >
>> > > The "SWDEV-161497" is meanless.
>> > > you can describe the issue or just remove the bug number.
>> > >
>> > > >
>> > > > Signed-off-by: Emily Deng
>> > > > ---
>> > > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
>> > > > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
>> > > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
>> > > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
>> > > >
>> > > > 4 files changed, 79 insertions(+), 4 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> > > > index 07924d4..67b584b 100644
>> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> > > > @@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
>> > > > AMDGPU_CP_KIQ_IRQ_LAST
>> > > > };
>> > > >
>> > > > +#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
>> > > > +#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
>> > > > +#define MAX_KIQ_REG_TRY 20
>> > > > +
>> > > > int amdgpu_device_ip_set_clockgating_state(void *dev,
>> > > > enum amd_ip_block_type
>> > > > block_type,
>> > > > enum
>> > > > amd_clockgating_state state); diff --git
>> > > > a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>> > > > index 21adb1b6..3885636 100644
>> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>> > > > @@ -22,9 +22,6 @@
>> > > > */
>> > > >
>> > > > #include "amdgpu.h"
>> > > > -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
>> > > > -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ -
>> > #define
>> > > > MAX_KIQ_REG_TRY 20
>> > > >
>> > > > uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { diff
>> > > > --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> > > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> > > > index 76d9
RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
> -Original Message-
> From: Zhu, Rex
> Sent: Thursday, August 16, 2018 1:41 PM
> To: 'Alex Deucher'
> Cc: Deng, Emily ; amd-gfx list g...@lists.freedesktop.org>
> Subject: RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do
> invalidate tlb
>
>
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Wednesday, August 15, 2018 10:14 PM
> > To: Zhu, Rex
> > Cc: Deng, Emily ; amd-gfx list > g...@lists.freedesktop.org>
> > Subject: Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq
> > to do invalidate tlb
> >
> > On Wed, Aug 15, 2018 at 9:56 AM Zhu, Rex wrote:
> > >
> > >
> > >
> > > > -Original Message-
> > > > From: amd-gfx On Behalf Of
> > > > Emily Deng
> > > > Sent: Wednesday, August 15, 2018 5:48 PM
> > > > To: amd-gfx@lists.freedesktop.org
> > > > Cc: Deng, Emily
> > > > Subject: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq
> > > > to do invalidate tlb
> > > >
> > > > To avoid the tlb flush not interrupted by world switch, use kiq
> > > > and one command to do tlb invalidate.
> > > >
> > > > v2:
> > > > Add firmware version checking.
> > > >
> > > > v3:
> > > > Refine the code, and move the firmware checking into
> > > > gfx_v9_0_ring_emit_reg_write_reg_wait.
> > > >
> > > > SWDEV-161497
> > >
> > > The "SWDEV-161497" is meanless.
> > > you can describe the issue or just remove the bug number.
> > >
> > > >
> > > > Signed-off-by: Emily Deng
> > > > ---
> > > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
> > > > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
> > > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
> > > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
> > > >
> > > > 4 files changed, 79 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > > index 07924d4..67b584b 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > > @@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
> > > > AMDGPU_CP_KIQ_IRQ_LAST
> > > > };
> > > >
> > > > +#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> > > > +#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
> > > > +#define MAX_KIQ_REG_TRY 20
> > > > +
> > > > int amdgpu_device_ip_set_clockgating_state(void *dev,
> > > > enum amd_ip_block_type
> > > > block_type,
> > > > enum
> > > > amd_clockgating_state state); diff --git
> > > > a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > index 21adb1b6..3885636 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > @@ -22,9 +22,6 @@
> > > > */
> > > >
> > > > #include "amdgpu.h"
> > > > -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> > > > -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ -
> > #define
> > > > MAX_KIQ_REG_TRY 20
> > > >
> > > > uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { diff
> > > > --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > > index 76d979e..c9b3db4 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > > @@ -4348,8 +4348,21 @@ static void
> > > > gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> > > > uint32_t ref,
> > > > uint32_t mask) {
> > > > int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> > > > + struct amdgpu_device *adev = ring->adev;
> > > > + bool fw_version_ok = false;
> > > >
> > > > - if (amdgpu_sriov_vf(ring->adev))
> > > > + if (ring->f
RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, August 15, 2018 10:14 PM
> To: Zhu, Rex
> Cc: Deng, Emily ; amd-gfx list g...@lists.freedesktop.org>
> Subject: Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do
> invalidate tlb
>
> On Wed, Aug 15, 2018 at 9:56 AM Zhu, Rex wrote:
> >
> >
> >
> > > -Original Message-
> > > From: amd-gfx On Behalf Of
> > > Emily Deng
> > > Sent: Wednesday, August 15, 2018 5:48 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deng, Emily
> > > Subject: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to
> > > do invalidate tlb
> > >
> > > To avoid the tlb flush not interrupted by world switch, use kiq and
> > > one command to do tlb invalidate.
> > >
> > > v2:
> > > Add firmware version checking.
> > >
> > > v3:
> > > Refine the code, and move the firmware checking into
> > > gfx_v9_0_ring_emit_reg_write_reg_wait.
> > >
> > > SWDEV-161497
> >
> > The "SWDEV-161497" is meanless.
> > you can describe the issue or just remove the bug number.
> >
> > >
> > > Signed-off-by: Emily Deng
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
> > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
> > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
> > >
> > > 4 files changed, 79 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > index 07924d4..67b584b 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > @@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
> > > AMDGPU_CP_KIQ_IRQ_LAST
> > > };
> > >
> > > +#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> > > +#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
> > > +#define MAX_KIQ_REG_TRY 20
> > > +
> > > int amdgpu_device_ip_set_clockgating_state(void *dev,
> > > enum amd_ip_block_type
> > > block_type,
> > > enum amd_clockgating_state
> > > state); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > index 21adb1b6..3885636 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > @@ -22,9 +22,6 @@
> > > */
> > >
> > > #include "amdgpu.h"
> > > -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> > > -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ -
> #define
> > > MAX_KIQ_REG_TRY 20
> > >
> > > uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { diff --git
> > > a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > index 76d979e..c9b3db4 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > @@ -4348,8 +4348,21 @@ static void
> > > gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> > > uint32_t ref,
> > > uint32_t mask) {
> > > int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> > > + struct amdgpu_device *adev = ring->adev;
> > > + bool fw_version_ok = false;
> > >
> > > - if (amdgpu_sriov_vf(ring->adev))
> > > + if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
> > > + if ((adev->gfx.me_fw_version >= 0x009c) && (adev-
> > > >gfx.me_feature_version >= 42))
> > > + if ((adev->gfx.pfp_fw_version >= 0x00b1)
> > > + &&
> > > (adev->gfx.pfp_feature_version >= 42))
> > > + fw_version_ok = true;
> > > + } else {
> > > + if ((adev->gfx.mec_fw_version >= 0x0193) &&
> > > + (adev-
> > > >gfx.mec_feature_version >= 42))
> > > + fw_version_ok = true;
> > > + }
> >
> > Maybe we can add a flag and set the flag when request_firmware.
>
Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
On Wed, Aug 15, 2018 at 9:56 AM Zhu, Rex wrote:
>
>
>
> > -Original Message-
> > From: amd-gfx On Behalf Of Emily
> > Deng
> > Sent: Wednesday, August 15, 2018 5:48 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deng, Emily
> > Subject: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do
> > invalidate tlb
> >
> > To avoid the tlb flush not interrupted by world switch, use kiq and one
> > command to do tlb invalidate.
> >
> > v2:
> > Add firmware version checking.
> >
> > v3:
> > Refine the code, and move the firmware
> > checking into gfx_v9_0_ring_emit_reg_write_reg_wait.
> >
> > SWDEV-161497
>
> The "SWDEV-161497" is meanless.
> you can describe the issue or just remove the bug number.
>
> >
> > Signed-off-by: Emily Deng
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
> >
> > 4 files changed, 79 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 07924d4..67b584b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
> > AMDGPU_CP_KIQ_IRQ_LAST
> > };
> >
> > +#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> > +#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
> > +#define MAX_KIQ_REG_TRY 20
> > +
> > int amdgpu_device_ip_set_clockgating_state(void *dev,
> > enum amd_ip_block_type
> > block_type,
> > enum amd_clockgating_state state);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > index 21adb1b6..3885636 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > @@ -22,9 +22,6 @@
> > */
> >
> > #include "amdgpu.h"
> > -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> > -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
> > -#define MAX_KIQ_REG_TRY 20
> >
> > uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { diff --git
> > a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 76d979e..c9b3db4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -4348,8 +4348,21 @@ static void
> > gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> > uint32_t ref, uint32_t mask)
> > {
> > int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> > + struct amdgpu_device *adev = ring->adev;
> > + bool fw_version_ok = false;
> >
> > - if (amdgpu_sriov_vf(ring->adev))
> > + if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
> > + if ((adev->gfx.me_fw_version >= 0x009c) && (adev-
> > >gfx.me_feature_version >= 42))
> > + if ((adev->gfx.pfp_fw_version >= 0x00b1) &&
> > (adev->gfx.pfp_feature_version >= 42))
> > + fw_version_ok = true;
> > + } else {
> > + if ((adev->gfx.mec_fw_version >= 0x0193) && (adev-
> > >gfx.mec_feature_version >= 42))
> > + fw_version_ok = true;
> > + }
>
> Maybe we can add a flag and set the flag when request_firmware.
I was going to suggest the same thing.
>
> > +
> > + fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok
Also is this specific to vega10 or do all gfx9 parts have this fix?
Please verify.
Alex
> > :
> > +false;
> > +
> > + if (amdgpu_sriov_vf(adev) && fw_version_ok)
> > gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
> > ref, mask, 0x20);
> > else
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index ed467de..3419178 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -311,6 +311,60 @@ static uint32_t
> >
Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
Am 15.08.2018 um 14:54 schrieb Emily Deng:
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
v3:
Refine the code, and move the firmware
checking into gfx_v9_0_ring_emit_reg_write_reg_wait.
v4:
Change the name amdgpu_kiq_invalidate_tlb to amdgpu_kiq_reg_write_reg_wait.
Remove the in_interrupt.
Refine code.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 60
4 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6265b88..19ef7711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -212,6 +212,10 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
};
+#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e..e010166 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4348,8 +4348,21 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct
amdgpu_ring *ring,
uint32_t ref, uint32_t mask)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ struct amdgpu_device *adev = ring->adev;
+ bool fw_version_ok = false;
- if (amdgpu_sriov_vf(ring->adev))
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ if ((adev->gfx.me_fw_version >= 0x009c) &&
(adev->gfx.me_feature_version >= 42)
+ && (adev->gfx.pfp_fw_version >= 0x00b1) &&
(adev->gfx.pfp_feature_version >= 42))
+ fw_version_ok = true;
The indentation here is wrong and the && belongs at the end of the line.
+ } else {
+ if ((adev->gfx.mec_fw_version >= 0x0193) &&
(adev->gfx.mec_feature_version >= 42))
+ fw_version_ok = true;
+ }
+
+ fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok :
false;
+
+ if (amdgpu_sriov_vf(adev) && fw_version_ok)
Please squash the second patch into this one. The goal is to use the
same code path on both SRIOV and bare metal.
I would rather separate our this change into a patch and then make the
TLB invalidation the second patch.
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..9726c7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,59 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int
vmid)
return req;
}
+signed long amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev, struct amdgpu_vmhub *hub,
+ unsigned eng, u32 req, uint32_t vmid)
That is still specialized, e.g. you assume that you work with a VMHUB
here instead of specifying the registers, req and value separately.
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
+ struct amdgpu_ring *ring = >ring;
+
+ if (!ring->ready) {
+ return -EINVAL;
+ }
Please drop the {} here.
Christian.
+
+ spin_lock_irqsave(>ring_lock, flags);
+
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+ amdgpu_fence_emit_polling(ring, );
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because
[PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
v3:
Refine the code, and move the firmware
checking into gfx_v9_0_ring_emit_reg_write_reg_wait.
v4:
Change the name amdgpu_kiq_invalidate_tlb to amdgpu_kiq_reg_write_reg_wait.
Remove the in_interrupt.
Refine code.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 60
4 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6265b88..19ef7711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -212,6 +212,10 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
};
+#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e..e010166 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4348,8 +4348,21 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct
amdgpu_ring *ring,
uint32_t ref, uint32_t mask)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ struct amdgpu_device *adev = ring->adev;
+ bool fw_version_ok = false;
- if (amdgpu_sriov_vf(ring->adev))
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ if ((adev->gfx.me_fw_version >= 0x009c) &&
(adev->gfx.me_feature_version >= 42)
+ && (adev->gfx.pfp_fw_version >= 0x00b1) &&
(adev->gfx.pfp_feature_version >= 42))
+ fw_version_ok = true;
+ } else {
+ if ((adev->gfx.mec_fw_version >= 0x0193) &&
(adev->gfx.mec_feature_version >= 42))
+ fw_version_ok = true;
+ }
+
+ fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok :
false;
+
+ if (amdgpu_sriov_vf(adev) && fw_version_ok)
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..9726c7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,59 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int
vmid)
return req;
}
+signed long amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev, struct
amdgpu_vmhub *hub,
+ unsigned eng, u32 req, uint32_t vmid)
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
+ struct amdgpu_ring *ring = >ring;
+
+ if (!ring->ready) {
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(>ring_lock, flags);
+
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+ amdgpu_fence_emit_polling(ring, );
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+* block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+* is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+* never return if we keep waiting in virt_kiq_rreg, which cause
+* gpu_recover() hang there.
+*
+* also don't wait anymore for IRQ context
+* */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq;
+
+ might_sleep();
+
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+
RE: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
>-Original Message-
>From: amd-gfx On Behalf Of
>Christian König
>Sent: Wednesday, August 15, 2018 7:14 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do
>invalidate tlb
>
>Am 15.08.2018 um 13:08 schrieb Deng, Emily:
>>> -Original Message-
>>> From: amd-gfx On Behalf Of
>>> Christian König
>>> Sent: Wednesday, August 15, 2018 6:50 PM
>>> To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>>> Subject: Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq
>>> to do invalidate tlb
>>>
>>> Am 15.08.2018 um 11:48 schrieb Emily Deng:
>>>> To avoid the tlb flush not interrupted by world switch, use kiq and
>>>> one command to do tlb invalidate.
>>>>
>>>> v2:
>>>> Add firmware version checking.
>>>>
>>>> v3:
>>>> Refine the code, and move the firmware checking into
>>>> gfx_v9_0_ring_emit_reg_write_reg_wait.
>>>>
>>>> SWDEV-161497
>>>>
>>>> Signed-off-by: Emily Deng
>>>> ---
>>>>drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
>>>>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
>>>>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
>>>>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
>>>
>>>>4 files changed, 79 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> index 07924d4..67b584b 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> @@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
>>>>AMDGPU_CP_KIQ_IRQ_LAST
>>>>};
>>>>
>>>> +#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
>>>> +#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
>>>> +#define MAX_KIQ_REG_TRY 20
>>>> +
>>>>int amdgpu_device_ip_set_clockgating_state(void *dev,
>>>> enum amd_ip_block_type
>>>> block_type,
>>>> enum amd_clockgating_state
>>>> state);
>>> diff --git
>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>>>> index 21adb1b6..3885636 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>>>> @@ -22,9 +22,6 @@
>>>> */
>>>>
>>>>#include "amdgpu.h"
>>>> -#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
>>>> -#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
>>>> -#define MAX_KIQ_REG_TRY 20
>>>>
>>>>uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
>>>>{
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> index 76d979e..c9b3db4 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> @@ -4348,8 +4348,21 @@ static void
>>> gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
>>>> uint32_t ref,
>>>> uint32_t mask)
>>>>{
>>>>int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>>>> + struct amdgpu_device *adev = ring->adev;
>>>> + bool fw_version_ok = false;
>>>>
>>>> - if (amdgpu_sriov_vf(ring->adev))
>>>> + if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
>>>> + if ((adev->gfx.me_fw_version >= 0x009c) && (adev-
>>>> gfx.me_feature_version >= 42))
>>>> + if ((adev->gfx.pfp_fw_version >= 0x00b1) &&
>>>> +(adev->gfx.pfp_feature_version >= 42))
>>> Why "if (...) if (...)" ? Just if (... && ...) should do as well.
>> Ok, will modify.
>>>> + fw_version_ok = true;
>>>> + } else {
>>>> + if ((adev->gfx.mec_fw_version >= 0x0193) && (adev-
>>>> gfx.mec_feature_version >= 42))
>>>>
Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
Am 15.08.2018 um 13:08 schrieb Deng, Emily:
-Original Message-
From: amd-gfx On Behalf Of
Christian König
Sent: Wednesday, August 15, 2018 6:50 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do
invalidate tlb
Am 15.08.2018 um 11:48 schrieb Emily Deng:
To avoid the tlb flush not interrupted by world switch, use kiq and
one command to do tlb invalidate.
v2:
Add firmware version checking.
v3:
Refine the code, and move the firmware checking into
gfx_v9_0_ring_emit_reg_write_reg_wait.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
4 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 07924d4..67b584b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
};
+#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_clockgating_state state);
diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e..c9b3db4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4348,8 +4348,21 @@ static void
gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
uint32_t ref, uint32_t mask)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ struct amdgpu_device *adev = ring->adev;
+ bool fw_version_ok = false;
- if (amdgpu_sriov_vf(ring->adev))
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ if ((adev->gfx.me_fw_version >= 0x009c) && (adev-
gfx.me_feature_version >= 42))
+ if ((adev->gfx.pfp_fw_version >= 0x00b1) &&
+(adev->gfx.pfp_feature_version >= 42))
Why "if (...) if (...)" ? Just if (... && ...) should do as well.
Ok, will modify.
+ fw_version_ok = true;
+ } else {
+ if ((adev->gfx.mec_fw_version >= 0x0193) && (adev-
gfx.mec_feature_version >= 42))
+ fw_version_ok = true;
+ }
+
+ fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok :
+false;
+
+ if (amdgpu_sriov_vf(adev) && fw_version_ok)
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..3419178 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,60 @@ static uint32_t
gmc_v9_0_get_invalidate_req(unsigned int vmid)
return req;
}
+signed long amdgpu_kiq_invalidate_tlb(struct amdgpu_device *adev, struct
amdgpu_vmhub *hub,
+ unsigned eng, u32 req, uint32_t vmid)
Better make that function just a generic reg_write_reg_wait function, instead of
specialized for tlb flushing.
Do you mean rename the function to amdgpu_reg_write_reg_wait?
Yeah, something like that. I suggest amdgpu_kiq_reg_write_reg_wait() or
otherwise you might run into a name clash.
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
+ struct amdgpu_ring *ring = >ring;
+
+ if (!ring->ready) {
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(>ring_lock, flags);
+
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
eng,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+ amdgpu_fence_emit_polling(ring, );
Re: [PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
Am 15.08.2018 um 11:48 schrieb Emily Deng:
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
v3:
Refine the code, and move the firmware
checking into gfx_v9_0_ring_emit_reg_write_reg_wait.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
4 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 07924d4..67b584b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
};
+#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e..c9b3db4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4348,8 +4348,21 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct
amdgpu_ring *ring,
uint32_t ref, uint32_t mask)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ struct amdgpu_device *adev = ring->adev;
+ bool fw_version_ok = false;
- if (amdgpu_sriov_vf(ring->adev))
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ if ((adev->gfx.me_fw_version >= 0x009c) &&
(adev->gfx.me_feature_version >= 42))
+ if ((adev->gfx.pfp_fw_version >= 0x00b1) &&
(adev->gfx.pfp_feature_version >= 42))
Why "if (...) if (...)" ? Just if (... && ...) should do as well.
+ fw_version_ok = true;
+ } else {
+ if ((adev->gfx.mec_fw_version >= 0x0193) &&
(adev->gfx.mec_feature_version >= 42))
+ fw_version_ok = true;
+ }
+
+ fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok :
false;
+
+ if (amdgpu_sriov_vf(adev) && fw_version_ok)
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..3419178 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,60 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int
vmid)
return req;
}
+signed long amdgpu_kiq_invalidate_tlb(struct amdgpu_device *adev, struct amdgpu_vmhub *hub,
+ unsigned eng, u32 req, uint32_t vmid)
Better make that function just a generic reg_write_reg_wait function,
instead of specialized for tlb flushing.
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
+ struct amdgpu_ring *ring = >ring;
+
+ if (!ring->ready) {
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(>ring_lock, flags);
+
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+ amdgpu_fence_emit_polling(ring, );
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+* block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+* is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+* never return if we keep waiting in virt_kiq_rreg, which cause
+* gpu_recover() hang there.
+*
+* also don't wait anymore for IRQ context
+* */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto
[PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
v3:
Refine the code, and move the firmware
checking into gfx_v9_0_ring_emit_reg_write_reg_wait.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
4 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 07924d4..67b584b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
};
+#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e..c9b3db4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4348,8 +4348,21 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct
amdgpu_ring *ring,
uint32_t ref, uint32_t mask)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ struct amdgpu_device *adev = ring->adev;
+ bool fw_version_ok = false;
- if (amdgpu_sriov_vf(ring->adev))
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ if ((adev->gfx.me_fw_version >= 0x009c) &&
(adev->gfx.me_feature_version >= 42))
+ if ((adev->gfx.pfp_fw_version >= 0x00b1) &&
(adev->gfx.pfp_feature_version >= 42))
+ fw_version_ok = true;
+ } else {
+ if ((adev->gfx.mec_fw_version >= 0x0193) &&
(adev->gfx.mec_feature_version >= 42))
+ fw_version_ok = true;
+ }
+
+ fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok :
false;
+
+ if (amdgpu_sriov_vf(adev) && fw_version_ok)
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..3419178 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,60 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int
vmid)
return req;
}
+signed long amdgpu_kiq_invalidate_tlb(struct amdgpu_device *adev, struct
amdgpu_vmhub *hub,
+ unsigned eng, u32 req, uint32_t vmid)
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
+ struct amdgpu_ring *ring = >ring;
+
+ if (!ring->ready) {
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(>ring_lock, flags);
+
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+ amdgpu_fence_emit_polling(ring, );
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+* block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+* is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+* never return if we keep waiting in virt_kiq_rreg, which cause
+* gpu_recover() hang there.
+*
+* also don't wait anymore for IRQ context
+* */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq;
+
+ if (in_interrupt())
+ might_sleep();
+
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+ msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+ r = amdgpu_fence_wait_polling(ring, seq,
[PATCH 1/2] drm/amdgpu/sriov: For sriov runtime, use kiq to do invalidate tlb
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
v3:
Refine the code, and move the firmware
checking into gfx_v9_0_ring_emit_reg_write_reg_wait.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 15 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 61
4 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 07924d4..67b584b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -210,6 +210,10 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST
};
+#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e..c9b3db4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4348,8 +4348,21 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct
amdgpu_ring *ring,
uint32_t ref, uint32_t mask)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ struct amdgpu_device *adev = ring->adev;
+ bool fw_version_ok = false;
- if (amdgpu_sriov_vf(ring->adev))
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ if ((adev->gfx.me_fw_version >= 0x009c) &&
(adev->gfx.me_feature_version >= 42))
+ if ((adev->gfx.pfp_fw_version >= 0x00b1) &&
(adev->gfx.pfp_feature_version >= 42))
+ fw_version_ok = true;
+ } else {
+ if ((adev->gfx.mec_fw_version >= 0x0193) &&
(adev->gfx.mec_feature_version >= 42))
+ fw_version_ok = true;
+ }
+
+ fw_version_ok = (adev->asic_type == CHIP_VEGA10) ? fw_version_ok :
false;
+
+ if (amdgpu_sriov_vf(adev) && fw_version_ok)
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..3419178 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,60 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int
vmid)
return req;
}
+signed long amdgpu_kiq_invalidate_tlb(struct amdgpu_device *adev, struct
amdgpu_vmhub *hub,
+ unsigned eng, u32 req, uint32_t vmid)
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = >gfx.kiq;
+ struct amdgpu_ring *ring = >ring;
+
+ if (!ring->ready) {
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(>ring_lock, flags);
+
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+ amdgpu_fence_emit_polling(ring, );
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+* block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+* is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+* never return if we keep waiting in virt_kiq_rreg, which cause
+* gpu_recover() hang there.
+*
+* also don't wait anymore for IRQ context
+* */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq;
+
+ if (in_interrupt())
+ might_sleep();
+
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+ msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+ r = amdgpu_fence_wait_polling(ring, seq,
