Re: [PATCH 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

2018-07-12 Thread Michel Dänzer 
On 2018-07-12 09:38 AM, Christian König wrote:
> Am 11.07.2018 um 18:23 schrieb Michel Dänzer:
>> From: Michel Dänzer 
>>
>> Instead of CPU invisible VRAM. Preparation for the following, no
>> functional change intended.
>>
>> Cc: sta...@vger.kernel.org
>> Signed-off-by: Michel Dänzer 
>>
>> [...]
>>  
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> index 9ee678d63890..752484328665 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> @@ -917,7 +917,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo,
>> u32 domain,
>>   domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
>>   if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
>>   adev->vram_pin_size += amdgpu_bo_size(bo);
>> -    adev->invisible_pin_size +=
>> amdgpu_vram_mgr_bo_invisible_size(bo);
>> +    adev->visible_pin_size +=
>> +    amdgpu_bo_size(bo) - amdgpu_vram_mgr_bo_invisible_size(bo);
> 
> Any particular reason why we should not invert
> amdgpu_vram_mgr_bo_invisible_size() as well?

Right, that occurred to me as well in the meantime. I was planning to
send a follow-up patch for this, but since patch 3 needs a v2 anyway,
I'll do a v2 of this one as well.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

2018-07-12 Thread Christian König 

Am 11.07.2018 um 18:23 schrieb Michel Dänzer:

From: Michel Dänzer 

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 5 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 --
  3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f4db10..77ab06bf26d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1593,7 +1593,7 @@ struct amdgpu_device {
  
  	/* tracking pinned memory */

u64 vram_pin_size;
-   u64 invisible_pin_size;
+   u64 visible_pin_size;
u64 gart_pin_size;
  
  	/* amdkfd interface */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d041dddaad0c..b1ea43ee8b87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -504,7 +504,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
vram_gtt.vram_size = adev->gmc.real_vram_size;
vram_gtt.vram_size -= adev->vram_pin_size;
vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
adev->invisible_pin_size);
+   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= adev->gart_pin_size;
@@ -525,8 +525,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.cpu_accessible_vram.total_heap_size =
adev->gmc.visible_vram_size;
mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size -
-   (adev->vram_pin_size - adev->invisible_pin_size);
+   adev->gmc.visible_vram_size - adev->visible_pin_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(>mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9ee678d63890..752484328665 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -917,7 +917,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
adev->vram_pin_size += amdgpu_bo_size(bo);
-   adev->invisible_pin_size += 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size +=
+   amdgpu_bo_size(bo) - 
amdgpu_vram_mgr_bo_invisible_size(bo);


Any particular reason why we should not invert 
amdgpu_vram_mgr_bo_invisible_size() as well?


Apart from that looks good to me,
Christian.


} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
adev->gart_pin_size += amdgpu_bo_size(bo);
}
@@ -969,7 +970,8 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
  
  	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {

adev->vram_pin_size -= amdgpu_bo_size(bo);
-   adev->invisible_pin_size -= 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size -=
+   amdgpu_bo_size(bo) - 
amdgpu_vram_mgr_bo_invisible_size(bo);
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
adev->gart_pin_size -= amdgpu_bo_size(bo);
}


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[PATCH 1/3] drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

2018-07-11 Thread Michel Dänzer 
From: Michel Dänzer 

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 5 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 --
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eaba0f4db10..77ab06bf26d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1593,7 +1593,7 @@ struct amdgpu_device {
 
/* tracking pinned memory */
u64 vram_pin_size;
-   u64 invisible_pin_size;
+   u64 visible_pin_size;
u64 gart_pin_size;
 
/* amdkfd interface */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d041dddaad0c..b1ea43ee8b87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -504,7 +504,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
vram_gtt.vram_size = adev->gmc.real_vram_size;
vram_gtt.vram_size -= adev->vram_pin_size;
vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
-   vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
adev->invisible_pin_size);
+   vram_gtt.vram_cpu_accessible_size -= adev->visible_pin_size;
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= adev->gart_pin_size;
@@ -525,8 +525,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.cpu_accessible_vram.total_heap_size =
adev->gmc.visible_vram_size;
mem.cpu_accessible_vram.usable_heap_size =
-   adev->gmc.visible_vram_size -
-   (adev->vram_pin_size - adev->invisible_pin_size);
+   adev->gmc.visible_vram_size - adev->visible_pin_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(>mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9ee678d63890..752484328665 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -917,7 +917,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
adev->vram_pin_size += amdgpu_bo_size(bo);
-   adev->invisible_pin_size += 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size +=
+   amdgpu_bo_size(bo) - 
amdgpu_vram_mgr_bo_invisible_size(bo);
} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
adev->gart_pin_size += amdgpu_bo_size(bo);
}
@@ -969,7 +970,8 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 
if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
adev->vram_pin_size -= amdgpu_bo_size(bo);
-   adev->invisible_pin_size -= 
amdgpu_vram_mgr_bo_invisible_size(bo);
+   adev->visible_pin_size -=
+   amdgpu_bo_size(bo) - 
amdgpu_vram_mgr_bo_invisible_size(bo);
} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
adev->gart_pin_size -= amdgpu_bo_size(bo);
}
-- 
2.18.0

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