Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

2019-08-16 Thread Kevin Wang
sure, i know, I feel this is not a good way to do code when other asics have 
similar problems.
we'd better add a helper function to check which sysfs interface is supported 
for each asic.
or move these sysfs interface to asic file to create.

anyway, we can optimize this logic later.
Reviewed-by: Kevin Wang <mailto:kevin1.w...@amd.com>

Best Regards,
Kevin

On 8/16/19 3:52 PM, Quan, Evan wrote:
Bascially, we should not expose the sysfs interface for those features not 
supported by the ASIC.
As, there are some tools/tests which judges whether the feature is supported by 
the existence of the file.
This can fix some test failure in rocm test suit.

Regards,
Evan
From: Wang, Kevin(Yang) <mailto:kevin1.w...@amd.com>
Sent: Friday, August 16, 2019 3:16 PM
To: Quan, Evan <mailto:evan.q...@amd.com>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only 
through sysfs

I don't recommend it. What's the problem if we keep it the way it is?
maybe other asic also has same problems, if do it, the other asic should  add a 
condition in there too.
eg: navi10 don't support sensor of  "pp_dpm_pcie".

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only 
through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 DRM_ERROR("failed to create device file 
pp_dpm_socclk\n");
 return ret;
 }
-   ret = device_create_file(adev->dev, _attr_pp_dpm_dcefclk);
-   if (ret) {
-   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, 
_attr_pp_dpm_dcefclk);
+   if (ret) {
+   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
+   return ret;
+   }
 }
 }
 if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 return ret;
 }
 }
-   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
-   if (ret) {
-   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
+   if (ret) {
+   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+   return ret;
+   }
 }
 ret = device_create_file(adev->dev, _attr_pp_sclk_od);
 if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 device_remove_file(adev->dev, _attr_pp_dpm_mclk);
 if (adev->asic_type >= CHIP_VEGA10) {
 device_remove_file(adev->dev, _attr_pp_dpm_socclk);
-   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
 }
-   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
 if (adev->asic_type >= CHIP_VEGA20)
 device_remove_file(adev->dev, _attr_pp_dpm_fclk);
 device_remove_file(adev->dev, _attr_pp_sclk_od);
--
2.22.0

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RE: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

2019-08-16 Thread Quan, Evan
Bascially, we should not expose the sysfs interface for those features not 
supported by the ASIC.
As, there are some tools/tests which judges whether the feature is supported by 
the existence of the file.
This can fix some test failure in rocm test suit.

Regards,
Evan
From: Wang, Kevin(Yang) 
Sent: Friday, August 16, 2019 3:16 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only 
through sysfs

I don't recommend it. What's the problem if we keep it the way it is?
maybe other asic also has same problems, if do it, the other asic should  add a 
condition in there too.
eg: navi10 don't support sensor of  "pp_dpm_pcie".

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only 
through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 DRM_ERROR("failed to create device file 
pp_dpm_socclk\n");
 return ret;
 }
-   ret = device_create_file(adev->dev, _attr_pp_dpm_dcefclk);
-   if (ret) {
-   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, 
_attr_pp_dpm_dcefclk);
+   if (ret) {
+   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
+   return ret;
+   }
 }
 }
 if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 return ret;
 }
 }
-   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
-   if (ret) {
-   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
+   if (ret) {
+   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+   return ret;
+   }
 }
 ret = device_create_file(adev->dev, _attr_pp_sclk_od);
 if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 device_remove_file(adev->dev, _attr_pp_dpm_mclk);
 if (adev->asic_type >= CHIP_VEGA10) {
 device_remove_file(adev->dev, _attr_pp_dpm_socclk);
-   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
 }
-   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
 if (adev->asic_type >= CHIP_VEGA20)
 device_remove_file(adev->dev, _attr_pp_dpm_fclk);
 device_remove_file(adev->dev, _attr_pp_sclk_od);
--
2.22.0

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Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

2019-08-16 Thread Wang, Kevin(Yang)
I don't recommend it. What's the problem if we keep it the way it is?
maybe other asic also has same problems, if do it, the other asic should  add a 
condition in there too.
eg: navi10 don't support sensor of  "pp_dpm_pcie".

Best Regards,
Kevin

From: amd-gfx  on behalf of Evan Quan 

Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Quan, Evan 
Subject: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only 
through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 DRM_ERROR("failed to create device file 
pp_dpm_socclk\n");
 return ret;
 }
-   ret = device_create_file(adev->dev, _attr_pp_dpm_dcefclk);
-   if (ret) {
-   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, 
_attr_pp_dpm_dcefclk);
+   if (ret) {
+   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
+   return ret;
+   }
 }
 }
 if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 return ret;
 }
 }
-   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
-   if (ret) {
-   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
+   if (ret) {
+   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+   return ret;
+   }
 }
 ret = device_create_file(adev->dev, _attr_pp_sclk_od);
 if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 device_remove_file(adev->dev, _attr_pp_dpm_mclk);
 if (adev->asic_type >= CHIP_VEGA10) {
 device_remove_file(adev->dev, _attr_pp_dpm_socclk);
-   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
 }
-   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
 if (adev->asic_type >= CHIP_VEGA20)
 device_remove_file(adev->dev, _attr_pp_dpm_fclk);
 device_remove_file(adev->dev, _attr_pp_sclk_od);
--
2.22.0

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[PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

2019-08-16 Thread Evan Quan
Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
DRM_ERROR("failed to create device file 
pp_dpm_socclk\n");
return ret;
}
-   ret = device_create_file(adev->dev, _attr_pp_dpm_dcefclk);
-   if (ret) {
-   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, 
_attr_pp_dpm_dcefclk);
+   if (ret) {
+   DRM_ERROR("failed to create device file 
pp_dpm_dcefclk\n");
+   return ret;
+   }
}
}
if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
return ret;
}
}
-   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
-   if (ret) {
-   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-   return ret;
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = device_create_file(adev->dev, _attr_pp_dpm_pcie);
+   if (ret) {
+   DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+   return ret;
+   }
}
ret = device_create_file(adev->dev, _attr_pp_sclk_od);
if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
device_remove_file(adev->dev, _attr_pp_dpm_mclk);
if (adev->asic_type >= CHIP_VEGA10) {
device_remove_file(adev->dev, _attr_pp_dpm_socclk);
-   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_dcefclk);
}
-   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
+   if (adev->asic_type != CHIP_ARCTURUS)
+   device_remove_file(adev->dev, _attr_pp_dpm_pcie);
if (adev->asic_type >= CHIP_VEGA20)
device_remove_file(adev->dev, _attr_pp_dpm_fclk);
device_remove_file(adev->dev, _attr_pp_sclk_od);
-- 
2.22.0

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