RE: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication

[Yu, Xiangliang]

> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, December 20, 2016 7:25 AM
> To: Yu, Xiangliang <xiangliang...@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>;
> dl.SRDC_SW_GPUVirtualization
> <dl.srdc_sw_gpuvirtualizat...@amd.com>; Liu, Shaoyun
> <shaoyun....@amd.com>
> Subject: Re: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox
> communication
> 
> On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu <xiangliang...@amd.com>
> wrote:
> > GPU guest driver send mailbox messages to hyperverisor to request full
> > access to all of registers and release it when access is done.
> >
> > Signed-off-by: Xiangliang Yu <xiangliang...@amd.com>
> > Signed-off-by: shaoyunl <shaoyun@amd.com>
> > ---
> >  drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h |   3 +
> >  drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c  | 128
> > ++
> >  2 files changed, 131 insertions(+)
> >  create mode 100644 drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
> >
> > diff --git a/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> > b/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> > index cc3123b..54e7b31 100644
> > --- a/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> > +++ b/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> > @@ -85,4 +85,7 @@ extern void amd_xgpu_free(struct amd_xgpu *xgpu);
> >
> >  extern int xgpu_allocate_csa(struct amd_xgpu *xgpu);  extern void
> > xgpu_destroy_csa(struct amd_xgpu_csa *csa);
> > +
> > +extern int xgpu_request_full_gpu_access(struct amdgpu_device *adev,
> > +bool init); extern int xgpu_release_full_gpu_access(struct
> > +amdgpu_device *adev, bool init);
> >  #endif
> > diff --git a/drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
> > b/drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
> > new file mode 100644
> > index 000..b74b501
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
> > @@ -0,0 +1,128 @@
> > +/*
> > + * Copyright 2016 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > +included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN
> NO EVENT
> > +SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> > +DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > +OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE
> > +OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: xiangliang...@amd.com
> > + */
> > +#include "amd_mxgpu.h"
> > +#include "bif/bif_5_0_d.h"
> > +#include "bif/bif_5_0_sh_mask.h"
> > +
> > +/* mailbox messages request */
> > +enum idh_request {
> > +   IDH_REQ_GPU_INIT_ACCESS = 1,
> > +   IDH_REL_GPU_INIT_ACCESS,
> > +   IDH_REQ_GPU_FINI_ACCESS,
> > +   IDH_REL_GPU_FINI_ACCESS,
> > +   IDH_REQ_GPU_RESET_ACCESS
> > +};
> > +
> > +/* mailbox messages data */
> > +enum idh_event {
> > +   IDH_CLR_MSG_BUF = 0,
> > +   IDH_READY_TO_ACCESS_GPU,
> > +   IDH_FLR_NOTIFICATION,
> > +   IDH_FLR_NOTIFICATION_CMPL
> > +};
> > +
> > +/* mailbox state */
> > +enum mail_state {
> > +   AMDGPU_START_INIT = 1,
> > +   AMDGPU_END_INIT,
> > +   AMDGPU_START_FINI,
> > +   AMDGPU_END_FINI,
> > +};
> > +
> > +/*
> > + * Mailbox communicate between PF and VF  */ static int
> > +xgpu_request_reg_access(struct amdgpu_device *adev,
> > +  enum mail_state state) {
> > +   u32 temp, timeout = 15;
> > +   u32 req = IDH_R

Re: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication

[Alex Deucher]

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu  wrote:
> GPU guest driver send mailbox messages to hyperverisor to request
> full access to all of registers and release it when access is done.
>
> Signed-off-by: Xiangliang Yu 
> Signed-off-by: shaoyunl 
> ---
>  drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h |   3 +
>  drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c  | 128 
> ++
>  2 files changed, 131 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
>
> diff --git a/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h 
> b/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> index cc3123b..54e7b31 100644
> --- a/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> +++ b/drivers/gpu/drm/amd/mxgpu/amd_mxgpu.h
> @@ -85,4 +85,7 @@ extern void amd_xgpu_free(struct amd_xgpu *xgpu);
>
>  extern int xgpu_allocate_csa(struct amd_xgpu *xgpu);
>  extern void xgpu_destroy_csa(struct amd_xgpu_csa *csa);
> +
> +extern int xgpu_request_full_gpu_access(struct amdgpu_device *adev, bool 
> init);
> +extern int xgpu_release_full_gpu_access(struct amdgpu_device *adev, bool 
> init);
>  #endif
> diff --git a/drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c 
> b/drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
> new file mode 100644
> index 000..b74b501
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/mxgpu/mxgpu_mb.c
> @@ -0,0 +1,128 @@
> +/*
> + * Copyright 2016 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: xiangliang...@amd.com
> + */
> +#include "amd_mxgpu.h"
> +#include "bif/bif_5_0_d.h"
> +#include "bif/bif_5_0_sh_mask.h"
> +
> +/* mailbox messages request */
> +enum idh_request {
> +   IDH_REQ_GPU_INIT_ACCESS = 1,
> +   IDH_REL_GPU_INIT_ACCESS,
> +   IDH_REQ_GPU_FINI_ACCESS,
> +   IDH_REL_GPU_FINI_ACCESS,
> +   IDH_REQ_GPU_RESET_ACCESS
> +};
> +
> +/* mailbox messages data */
> +enum idh_event {
> +   IDH_CLR_MSG_BUF = 0,
> +   IDH_READY_TO_ACCESS_GPU,
> +   IDH_FLR_NOTIFICATION,
> +   IDH_FLR_NOTIFICATION_CMPL
> +};
> +
> +/* mailbox state */
> +enum mail_state {
> +   AMDGPU_START_INIT = 1,
> +   AMDGPU_END_INIT,
> +   AMDGPU_START_FINI,
> +   AMDGPU_END_FINI,
> +};
> +
> +/*
> + * Mailbox communicate between PF and VF
> + */
> +static int xgpu_request_reg_access(struct amdgpu_device *adev,
> +  enum mail_state state)
> +{
> +   u32 temp, timeout = 15;
> +   u32 req = IDH_REQ_GPU_INIT_ACCESS;
> +
> +   if (state == AMDGPU_START_FINI)
> +   req = IDH_REQ_GPU_FINI_ACCESS;
> +   else if (state != AMDGPU_START_INIT)
> +   return -EINVAL;
> +
> +   WREG32(mmMAILBOX_MSGBUF_TRN_DW0, req);
> +   WREG32(mmMAILBOX_CONTROL,
> +   REG_SET_FIELD(RREG32(mmMAILBOX_CONTROL),
> +   MAILBOX_CONTROL, TRN_MSG_VALID, 1));
> +
> +   /* wait respond from PF */
> +   while (true) {
> +   temp = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
> +   if (temp == IDH_READY_TO_ACCESS_GPU)
> +   break;
> +   if (timeout == 0) {
> +   pr_err("amdgpu: VF request GPU access failed(0x%x) \
> +   in state %d\n", temp, state);
> +   return -ETIME;
> +   }
> +   msleep(20);
> +   timeout -= 20;
> +   }
> +   return 0;
> +}
> +
> +static int xgpu_release_reg_access(struct amdgpu_device *adev,
> +  enum mail_state state)
> +{
> +   u32 rel = IDH_REL_GPU_INIT_ACCESS;
> +
> +   if (state == AMDGPU_END_FINI)
> +   rel = IDH_REL_GPU_FINI_ACCESS;
> +   else if (state != AMDGPU_END_INIT)
> +   return -EINVAL;
> +
> +   WREG32(mmMAILBOX_MSGBUF_TRN_DW0, rel);
> +   WREG32(mmMAILBOX_CONTROL,
> +