RE: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

2017-02-21 Thread Deucher, Alexander 
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Xiaojie Yuan
> Sent: Tuesday, February 21, 2017 5:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yuan, Xiaojie
> Subject: [PATCH] drm/amdgpu: add HDMI audio support for si dce6
> 
> Signed-off-by: Xiaojie Yuan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130
> +++---
>  1 file changed, 121 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index c940bec..1398db6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct
> amdgpu_device *adev)
>   adev->mode_info.audio.enabled = false;
>  }
> 
> -/*
> -static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder,
> uint32_t clock)
> +static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
>  {
> - DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_encoder *amdgpu_encoder =
> to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
> >enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt-
> >offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL,
> HDMI_NULL_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL,
> HDMI_GC_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL,
> HDMI_GC_CONT, 1);
> + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset,
> tmp);
> +}
> +
> +static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
> +uint32_t clock, int bpc)
> +{
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
> + struct amdgpu_encoder *amdgpu_encoder =
> to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-
> >enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt-
> >offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL,
> HDMI_ACR_AUTO_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL,
> HDMI_ACR_SOURCE,
> + bpc > 8 ? 0 : 1);
> + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset,
> tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32,
> acr.cts_32khz);
> + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32,
> acr.n_32khz);
> + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44,
> acr.cts_44_1khz);
> + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44,
> acr.n_44_1khz);
> + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48,
> acr.cts_48khz);
> + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48,
> acr.n_48khz);
> + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
>  }
> -*/
> 
>  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder
> *encoder,
>  struct drm_display_mode *mode)
> @@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct
> drm_encoder *encoder, u32 clock)
>   struct drm_device *dev = encoder->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder-
> >crtc);
> + int em =
> amdgpu_atombios_encoder_get_encoder_mode(encoder);
>   u32 tmp;
> 
>   /*
> @@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct
> drm_encoder *encoder, u32 clock)
>   tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
>   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
>   DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc-
> >crtc_id);
> - tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> DCCG_AUDIO_DTO_SEL, 1);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> + DCCG_AUDIO_DTO_SEL, 0);
> + } else if (ENCODER_MODE_IS_DP(em)) {
> + tmp = REG_SET_FIELD(tmp,

Re: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

2017-02-21 Thread Christian König 
Not much of an issue, but when sending out a second version of a patch 
we usually put a v2 on the subject line to indicate that.


Additional to that the patch also needs at least a little bit of commit 
message.


With that fixed it is Acked-by: Christian König .

Regards,
Christian.

Am 21.02.2017 um 13:08 schrieb Edward O'Callaghan:

Reviewed-by: Edward O'Callaghan 

On 02/21/2017 09:39 PM, Xiaojie Yuan wrote:

Signed-off-by: Xiaojie Yuan 
---
  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130 +++---
  1 file changed, 121 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index c940bec..1398db6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct amdgpu_device 
*adev)
adev->mode_info.audio.enabled = false;
  }
  
-/*

-static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t 
clock)
+static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
  {
-   DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
+   struct drm_device *dev = encoder->dev;
+   struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+   u32 tmp;
+
+   tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
+   tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
+   tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
+   WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
+}
+
+static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
+  uint32_t clock, int bpc)
+{
+   struct drm_device *dev = encoder->dev;
+   struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
+   struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+   struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+   u32 tmp;
+
+   tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 
1);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
+   bpc > 8 ? 0 : 1);
+   WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
+
+   tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
+   WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
+   tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
+   WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
+
+   tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, 
acr.cts_44_1khz);
+   WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
+   tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
+   WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
+
+   tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
+   WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
+   tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
+   tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
+   WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
  }
-*/
  
  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,

   struct drm_display_mode *mode)
@@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
*encoder, u32 clock)
struct drm_device *dev = encoder->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
+   int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
u32 tmp;
  
  	/*

@@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
*encoder, u32 clock)
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
-   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 1);
+   if (em == ATOM_ENCODER_MODE_HDMI) {
+   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
+   DCCG_AUDIO_DTO_SEL, 0);
+   } else if (ENCODER_MODE_IS_DP(em)) {
+   tmp =

Re: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

2017-02-21 Thread Edward O'Callaghan 
Reviewed-by: Edward O'Callaghan 

On 02/21/2017 09:39 PM, Xiaojie Yuan wrote:
> Signed-off-by: Xiaojie Yuan 
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130 
> +++---
>  1 file changed, 121 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index c940bec..1398db6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct amdgpu_device 
> *adev)
>   adev->mode_info.audio.enabled = false;
>  }
>  
> -/*
> -static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t 
> clock)
> +static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
>  {
> - DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
> + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
> +}
> +
> +static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
> +uint32_t clock, int bpc)
> +{
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
> + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 
> 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
> + bpc > 8 ? 0 : 1);
> + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
> + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
> + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, 
> acr.cts_44_1khz);
> + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
> + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
> + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
> + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
>  }
> -*/
>  
>  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
>  struct drm_display_mode *mode)
> @@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
> *encoder, u32 clock)
>   struct drm_device *dev = encoder->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
> + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
>   u32 tmp;
>  
>   /*
> @@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
> *encoder, u32 clock)
>   tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
>   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
>   DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
> - tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 1);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> + DCCG_AUDIO_DTO_SEL, 0);
> + } else if (ENCODER_MODE_IS_DP(em)) {
> + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
> + DCCG_AUDIO_DTO_SEL, 1);
> + }
>   WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
> - WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
> - WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> +