just as bad as each other,
and both are bound by exactly the same restrictions whereby they
license IP from all over the place and have no legal right to
opensource a lot of what they do. TI have only very recently given a
fig about actually developing decent kernels
ng of new technology at high
prices and low turnaround times, they simply don't.
Maybe when the Cortex-A15 is out and we have ARM servers floating
around, the dream of a Power User ARM Smartbook with a huge screen, a
ton of RAM and processing power enough to spook a hor
On Wed, Feb 2, 2011 at 9:30 AM, Luke Kenneth Casson Leighton
wrote:
> On Wed, Feb 2, 2011 at 1:41 PM, Gordan Bobic wrote:
>>> ARM CPUs don't have the concept of a BIOS, so the screen timings are
>>> hard-coded into the kernel driver. you *can't* just whop a new screen
>>> in and expect it to wo
AP4 are phone/tablet chips almost entirely focused on Android. MX53
is for in-flight entertainment, Ford Sync, handheld media tablets,
that kind of thing. Remember when you think about speeds on devices,
they are always listed as maximums. Yes, SATA-II is 3Gbit/s (actually
about 2.4Gbit after you ge
t done something like it already - you'd think the
largest most successful consumer-oriented open source distribution in
the last 5 years would do well to have development hardware available.
--
Matt Sealey
Product Development Analyst, Genesi USA, Inc.
___
ter on, but I suspect it would be more likely that one would
> create optimized NEON binaries and perhaps one day switch to a D32 base
> set of configuration flags once nobody is using D16 v7 devices.
Marvell ARMADA 200 series and Tegra2...
> Philippe: If I'm crazy, let me know
d) then you are onto
a winner, otherwise it may be that it is just hiding the work. How
exactly would we determine whether the security engine is really
making a difference to performance?
--
Matt Sealey
Product Development Analyst, Genesi USA, Inc.
___
arm mailing list
arm@lists.fedoraproject.org
https://admin.fedoraproject.org/mailman/listinfo/arm
surely,
no magic batching up of transactions. If there is a complete lack of
performance improvement then you can basically put that down to FIFO
inside the chip not hitting the alarm level required for the chip to
empty it on the other side..
--
Matt Sealey
Product Development Analyst, Genesi USA,
