Well, one can do this, there were discussion about replacing of VCXO with
internall PLL (there is Xilinx note about it)
But it requires additional work in gateware and it is not trivial to make it
working reliably.
Greg
-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.
> Since we are not going to use White Rabbit, I propose removing them.
Do we have an alternate time/synchronization protocol planned for DRTIO? Does
it make sense to leave WR components as a fallback for risk mitigation, in case
we change our minds subsequently?
OK
On 30 June 2016 at 10:50, Sébastien Bourdeauducq wrote:
> On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote:
>
>> In case of WR it already worked quite well 6 years ago but later on this
>> circuit was modified several times:)
>> All the time little things.
>> So since we have mo
On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote:
In case of WR it already worked quite well 6 years ago but later on this
circuit was modified several times:)
All the time little things.
So since we have more important things to do I'd leave it as it is.
Since we are not going to
Well, it is straightforward. But devil is in the details.
In case of WR it already worked quite well 6 years ago but later on this
circuit was modified several times:)
All the time little things.
So since we have more important things to do I'd leave it as it is.
We can install both options on the
On Thursday, June 30, 2016 04:38 PM, Grzegorz Kasprowicz wrote:
But it requires additional work in gateware and it is not trivial to make it
working reliably.
What are the difficulties? Looking briefly at the White Rabbit DDMTD
paper, it sounds pretty straightforward to me except that we may
