2:59 PM
To: Grzegorz Kasprowicz
Cc: artiq@lists.m-labs.hk
Subject: SFP/SATA cables for connecting Ethernet on Sayma
Hi Greg,
just a quick note about the SFP/SATA cable that is necessary to connect
Ethernet on a Sayma directly. I suggest building them from a passive SFP copper
cable (e.g.
the person managing the list at
> >> artiq-ow...@lists.m-labs.hk
> >>
> >> When replying, please edit your Subject line so it is more specific
> >> than "Re: Contents of ARTIQ digest..."
> >>
> >>
> >>
Usually one can expect half of octopart prices.
So the difference would be about 30$
On 29 June 2017 at 21:43, Joe Britton via ARTIQ
wrote:
> Octopart Avnet costs for 1 unit
>
> XC7A100T-2CSG324C $131.22
> XC7A50T-2CSG324C $74.98
>
> Greg, What is the cost differential between 50T-2 and 100T-2 a
look here
https://cloud.githubusercontent.com/assets/4325054/24015076/98f7653a-0a87-11e7-93d2-7df1831b2422.jpg
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You don’t have to do combined order. Just drop an email that you want to order
10 pieces with each board shipped to certain place. Only transportation cost
will apply.
Greg
From: Neal Pisenti [mailto:npise...@gmail.com]
Sent: Wednesday, March 15, 2017 9:37 PM
To: Grzegorz Kasprowicz
I already received assembled 3U boards including VHDCI carrier and BNC IO.
So we can test whole setup in the lab quickly.
You can help us with simple HDL design for KC705 that i.e. toggles IOs or
makes loopback: ttl->lvds->VHDCI-> FPGA-> VHDCI->lvds->TTL.
At the moment we are so occupied with other
It is compatible with VHDCI carrier - I used the same pinout.
I have 2 pieces in lab to do tests.
Moreover, to do quick tests I designed another simple adapter that converts TTL
to LVDS. Sources are here:
https://github.com/m-labs/sinara/tree/master/ARTIQ_ALTIUM/Kasli/3U/PCB_3U_Tester.
Can be us
Just use Aurora IP core or something with similar functionality. You have 2
bidir links, one can be used for DRTIO, second for simple control protocol.
>From one side you have some inputs that are repeated on the other side.
You can run UART, SPI or whatever you want since it is transparent.
I used
We can use multiple 10Gbit links in parallel between Metlinos but the
latency would be the same.
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on Sayma RTM FPGA we have enough pins to do p2p connections for all SPI
chips, and so I did.
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Yes, I can.
RF signals on the backplane are single ended so I'd need to use some driver
or balun.
On 9 October 2016 at 16:19, Sébastien Bourdeauducq wrote:
> On Sunday, October 09, 2016 10:20 PM, Grzegorz Kasprowicz wrote:
>
>> Which FPGA - on AMC or on RTM should generate SYS
Which FPGA - on AMC or on RTM should generate SYSREF clock? I mean
connection of HMC7043 RFSYNCIN pins.
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is intended as a preliminary indication to the host in
> which the module is installed that the received signal strength is below
> the specified range. If the Rx_LOS function is not implemented, or is
> reported via the two-wire interface only, the Rx_LOS contact shall be held
>
Hi All
On Sunday, July 24, 2016 07:59 AM, j arl wrote:
>
>> The bitfiles for the sayma_motherboard FPGA will be stored in flash.
>> We've discussed several ways of updating the bitfiles. a) serial JTAG
>> b) DRTIO over microTCA Port4 c) Ethernet microTCA Port0.
>>
>> Update method (a) is implement
On 24 July 2016 at 16:11, Sébastien Bourdeauducq wrote:
> On Sunday, July 24, 2016 10:04 PM, Grzegorz Kasprowicz wrote:
>
>> This can be also done using single FLASH and multi boot. Xilinx has
>> such option but never tested it.
>>
>
> I have used some of the multib
On 24 July 2016 at 14:19, Sébastien Bourdeauducq wrote:
> Hi,
>
> On Sunday, July 24, 2016 07:33 PM, Grzegorz Kasprowicz wrote:
>
>> > When receiving a bitfile, a board (Metlino/Sayma) writes it to its
>> > flash memory (via a SPI master core inside the FPGA) and
On 19 July 2016 at 17:47, j arl wrote:
> Greg, Others, Thinking about using SFP+ on new hardware (Sayma,
> Metlino). If SFP+ is backward compatible with SFP, m-labs could
> attempt DRTIO using SFP+ transceivers and fall back to
> WhiteRabbit-approved SFP as backup [1]. Please confirm the followin
18:17, Sébastien Bourdeauducq wrote:
> On Tuesday, June 28, 2016 04:00 PM, Grzegorz Kasprowicz wrote:
>
>> For Sayma board to not waste precious GTX we will add PHY with
>> 1000Base-X. We can also route it to SATA connector and provide dedicated
>> SATA-SFP cables. Most
-labs.hk]
Sent: Thursday, June 30, 2016 5:57 AM
To: Grzegorz Kasprowicz ; j arl
Cc: Robert Jördens ; artiq@lists.m-labs.hk
Subject: Re: clock recovery on Metlino and Kasli
Hi,
my question was whether one can get rid of all those 6 parts and replace them
with a Si5324 circuit (instead of #1 and
OK
On 30 June 2016 at 10:50, Sébastien Bourdeauducq wrote:
> On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote:
>
>> In case of WR it already worked quite well 6 years ago but later on this
>> circuit was modified several times:)
>> All the time little thi
n the PCB to have upgrade path.
Greg
On 30 June 2016 at 10:39, Sébastien Bourdeauducq wrote:
> On Thursday, June 30, 2016 04:38 PM, Grzegorz Kasprowicz wrote:
>
>> But it requires additional work in gateware and it is not trivial to make
>> it working reliably.
>>
we can use Si instead of CDCM61004RHBT
Greg
On 29 June 2016 at 04:56, Sébastien Bourdeauducq wrote:
> On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
>
>> For synchronisation over fibre we can use existing White Rabbit core.
>> The card requires only 2 VCXO os
a new thread.
>
> On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
> > For synchronisation over fibre we can use existing White Rabbit core.
> > The card requires only 2 VCXO oscillators and FPGA logic. The WR core
> > consumes 50% of small Spartan 45T. It
Hi All
All the AMC boards we designed and published on OHWR can be run stand-alone.
For the moment there is SATA connector on it routed to one of GTP/GTX. One
can use custom made SATA-SFP cable (simple and cheap) and connect it to
media converter or directly to the ethernet switch.
We use such setu
For synchronisation over fibre we can use existing White Rabbit core.
The card requires only 2 VCXO oscillators and FPGA logic. The WR core
consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy.
On 24 June 2016 at 20:39, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:
> >
ackplane communication...
Indeed, in this way we could move the noise spectrum much higher, where it’s
easier to filter it out.
Greg
From: kaspr...@gmail.com <mailto:kaspr...@gmail.com>
[mailto:kaspr...@gmail.com] On Behalf Of Grzegorz Kasprowicz
Sent: 08 April 2016 11:34
To: Thoma
synchronously apply reset pulse to all AMCs, exactly in the same ways as
in case of clock distribution over the backplane .
Best regards,
Greg
From: Thomas Harty [mailto:thomas.ha...@physics.ox.ac.uk]
Sent: Friday, April 08, 2016 8:04 PM
To: Grzegorz Kasprowicz
Cc: Slichter, Daniel H. (Fed
Sébastien Bourdeauducq ; Grzegorz Kasprowicz
Cc: 'Grzegorz Kasprowicz' ; artiq@lists.m-labs.hk
Subject: RE: [ARTIQ] FW: initial specification of the project
> On Saturday, 9 April 2016 6:10:36 PM HKT Grzegorz Kasprowicz wrote:
> > Why do you think that CPUs have negative value? You d
> > Why do you think that CPUs have negative value? You don't have to use
> them
> > at all.
>
> I already explained that the MPSoC has to be dealt with and cannot be
> completely ignored. If we have two SDRAM systems, maybe we can to a
> reasonable
> extent, but then it does complicate the board.
7;t have to use them
at all.
On the MCH Tongue 3, there is single port Ethernet connection that can be
used for slow control and remote upgrade.
Greg
-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
Sent: Saturday, April 09, 2016 5:48 PM
To: Grzegorz Kasprowicz
ZU7 you have 24+4 transceivers, but with ZU11 you have 32+4
ones:)
All in compatible package.
Greg
-Original Message-
From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov]
Sent: Saturday, April 09, 2016 1:42 AM
To: Grzegorz Kasprowicz ; 'Sébastien Bourdeauducq'
Cc:
artiq-boun...@lists.m-labs.hk] On Behalf Of Sébastien
Bourdeauducq
Sent: Friday, April 08, 2016 11:20 AM
To: artiq@lists.m-labs.hk
Cc: Grzegorz Kasprowicz
Subject: [ARTIQ] current HW specifications draft
Hi,
attached is the latest spec document, integrating new feedback. Let us know
if anythi
boards to support.
Greg
-Original Message-
From: Grzegorz Kasprowicz [mailto:gkasp...@elka.pw.edu.pl]
Sent: Friday, April 08, 2016 2:00 PM
To: 'Sébastien Bourdeauducq'
Cc: 'Grzegorz Kasprowicz' ; 'Slichter, Daniel H.
(Fed)' ; artiq@lists.m-labs.hk
Su
One more thing
In case of ZynQ, instead of ZU11, we have smaller GTX count version - ZU7 in
the same package.
Its cost is about 700-750$.
So we can install ZU7 by default, and when necessary, upgrade it to ZU11.
Greg
-Original Message-
From: Grzegorz Kasprowicz [mailto:gkasp
riginal Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
Sent: Friday, April 08, 2016 12:13 PM
To: Grzegorz Kasprowicz
Cc: 'Grzegorz Kasprowicz' ; 'Slichter, Daniel H. (Fed)'
; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project
On F
Anyway, we have already plenty of things to do so I'd relay on existing
backplane at the moment:)
On 8 April 2016 at 12:51, Grzegorz Kasprowicz wrote:
> Well, I don't have such template so all must be done from scratch.
> It's really big piece of PCB, we need at leas
On Friday, 8 April 2016 12:37:02 PM HKT Grzegorz Kasprowicz wrote:
> > Modification of the backplane is quite difficult and expensive.
>
> If we have a minimalistic backplane with just power, maybe IPMI, 4x
> differential pairs between MCH and each AMCs, and clock - why is t
dedicated to the clock distribution.
Greg
On 8 April 2016 at 12:25, Sébastien Bourdeauducq wrote:
> On Friday, 8 April 2016 12:02:43 PM HKT Grzegorz Kasprowicz wrote:
> > The MTCA backplane is not designed to distribute RF or analog clocks.
> >
> > Definitely they cannot be directly
Hi
The MTCA backplane is not designed to distribute RF or analog clocks.
Definitely they cannot be directly used to feed DACs or RF modules.
If you don't care about phase noise in Hz.kHz region, we can use PLL with
VCXO on each FMC board. But for GHz range it's hard to find VCXo and we
would hav
Sent: Thursday, March 31, 2016 9:55 PM
To: Slichter, Daniel H. (Fed)
Cc: Sébastien Bourdeauducq ; Grzegorz Kasprowicz
; Grzegorz Kasprowicz ; Leibrandt,
David R. (Fed) ; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] TTL + slow DACs
On Thu, Mar 31, 2016 at 7:45 PM, Slichter, Daniel H. (Fed)
wrote:
>
maller one because they
belong to different price steps.
Greg
-Original Message-
From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov]
Sent: Thursday, March 31, 2016 5:30 PM
To: Sébastien Bourdeauducq ; Grzegorz Kasprowicz
Cc: Robert Jördens ; Grzegorz Kasprowicz
; Leibrand
Here is the box
http://www.ohwr.org/projects/spec-box-1n/wiki
On 31 March 2016 at 15:57, Grzegorz Kasprowicz wrote:
> for this purpose one can use this board
> http://www.ohwr.org/projects/spec/wiki
> there is available also stand-alone aluminium box.The cost can be lowered
> by f
:48, Grzegorz Kasprowicz wrote:
> Well, yes, providing that you find charger that won't fail after 500 hours
> :)
>
>
> -Original Message-
> From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
> Sent: Thursday, March 31, 2016 12:42 PM
> To: Grzegorz Kasprow
The only chip that is available now, from US+ series is ZU9
-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
Sent: Thursday, March 31, 2016 12:57 PM
To: artiq@lists.m-labs.hk
Cc: Grzegorz Kasprowicz ; Florent Kermarrec
Subject: Re: [ARTIQ] DSP gateware
On
Well, yes, providing that you find charger that won't fail after 500 hours
:)
-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
Sent: Thursday, March 31, 2016 12:42 PM
To: Grzegorz Kasprowicz
Cc: Slichter, Daniel H. (Fed) ; Robert Jördens
; Grzegorz Kaspr
Yes, but for such speed you don't need to match better than several mm.
Greg
On 31 March 2016 at 13:51, Robert Jördens wrote:
> On Thu, Mar 31, 2016 at 8:51 AM, Florent Kermarrec
> wrote:
> > When choosing between Artix7 or Kintex7 you also have to consider that
> > Artix7 only have HR IOs whic
Well, we can use in this case the AMC board plugged into dual AMC box which
has 4 SFPs.
In some cases this could be an overkill, but it is working solution.
http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki
On 31 March 2016 at 12:05, Sébastien Bourdeauducq wrote:
> On Wednesday, 30 March 2016
HI
With US+ series, we have much better choice, between Kintex and Virtex
families in same package.
Kintex 7 chips are quite expensive, in the price of XC7K325T you can get
ZynQ US+ with almost twice more GTH and logic resources. Remember also
about limitations of JESD204B - in case of Artix you wo
this architecture.
>
>
>
> *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
> *Sent:* Wednesday, March 30, 2016 3:36 PM
>
> *To:* Slichter, Daniel H. (Fed)
> *Cc:* Robert Jördens ; Grzegorz Kasprowicz <
> gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) &l
On 31 March 2016 at 04:58, Sébastien Bourdeauducq wrote:
> On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote:
> > Well, you don't have to write it.
> > It is already available for RTOS and linux.
>
> We are not using RTOS or Linux.
>
you can also p
>
>
> Using the alternating grounds a la CERN seems like a suitable solution to
> me for sending in these additional analog rails.
>
>
>
> *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
> *Sent:* Wednesday, March 30, 2016 3:13 PM
> *To:* Slichter, Daniel
t; daughtercard itself, as close to the amplifiers etc as possible.
>
>
>
> Using the alternating grounds a la CERN seems like a suitable solution to
> me for sending in these additional analog rails.
>
>
>
> *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
> *Sent
Well, CERN does it in their FMC carriers. They use HPC routed like LPC and
then some of grounds are used as symmetrical analog supplies. In this way
if you plug wrong board, it will short the supply but no damage will occur.
I assume that low nosie DC/DC converters + LDOs will be installed on the
A
verified.
On 30 March 2016 at 23:02, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:
> This is an interesting potential solution although I am not sure how the
> signal integrity is at ~3 GHz, for example.
>
>
>
> *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.
Actually HPC with LPC IO assignment and 8 x GTP links is popular
configuration
So you have 34 LVDS pairs and 8 GTP links.
On 30 March 2016 at 23:00, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:
> > On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed)
> > wrote:
> > > Now,
les&biw=1920&bih=917&source=lnms&tbm=isch&sa=X&ved=0ahUKEwj19L7younLAhUKvXIKHQVBCg8Q_AUIBigB#tbm=isch&q=castellated+RF+modules>
On 30 March 2016 at 22:40, Grzegorz Kasprowicz wrote:
> One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6
> ones
One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6
ones, we won't be able to screw them.
But we can install MMCX ones for clocks and fit in total of 7 RF connectors,
Look here
http://www.ohwr.org/attachments/3390/fmc_top.jpg
Greg
On 30 March 2016 at 22:38, Grzegorz Kaspr
Well, we can do another crazy thing - solder small module with RF stuff on
the FMC board, under same shield.
In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the
functionality by soldering (automatic or manual) of just RF modules. WE can
even design such modules to hold the fro
the project
On Wed, Mar 30, 2016 at 9:53 PM, Grzegorz Kasprowicz
wrote:
> Maybe we should come back to the roots:) What if we use standard FMCs
> (LPC) with DAC/ADC channels and RF stuff _on_ them.
> JESD204B and some pins would go to the FPGA while DAC and RF clock would be
> fed
/fmc-adc-130m-16b-4cha/wiki
In this way we could use existing AFCK for quick tests
-Original Message-
From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov]
Sent: Wednesday, March 30, 2016 5:46 PM
To: Leibrandt, David R. (Fed) ; Sébastien
Bourdeauducq ; Grzegorz Kasprowicz
Cc
Are we talking about double width AMCs?
Two DAC channels and 2 RF modules should fit.
Greg
-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk]
Sent: Wednesday, March 30, 2016 5:46 PM
To: Leibrandt, David R. (Fed)
Cc: Grzegorz Kasprowicz ; 'Grzegorz Kaspr
On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote:
> [GK] If you don't use ARM, you still get hardened SDRAM controller and
> GBE MACs.
Yes, that's what I was saying: you cannot get rid of them (i.e. use their
pins like other IOs). So you need to use t
, March 30, 2016 1:50 PM
To: Grzegorz Kasprowicz
Cc: 'Slichter, Daniel H. (Fed)' ; 'Grzegorz
Kasprowicz' ; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project
On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote:
> - they can b
I can agree that FMC is not the best idea in case of RF stuff.
There are multipin RF board 2 board coaxial connectors which can be used for
plugin modules. And such modules can be easily shielded using i.e. Wurth
shields or EZ-Shields from Harwin that can be easily customized.
Greg
-Original
PM
To: Robert Jördens
Cc: Grzegorz Kasprowicz ; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project
Let me make clear that I don't have any specific opposition to FMC for the
power/digital signals. The only reason for considering other types of
connectors wou
2016 5:06 PM
To: Sébastien Bourdeauducq ; Grzegorz Kasprowicz
Cc: artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project
> > * we want to avoid RTMs and instead put the DAC/ADCs on the AMC card
> > and have analog plug-ins using the FMC form factor
There are FMC-type connectors with much smaller number of pins (SEARAY series)
Greg
-Original Message-
From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Robert Jördens
Sent: Tuesday, March 29, 2016 1:01 PM
To: Sébastien Bourdeauducq
Cc: Grzegorz Kasprowicz ; artiq@lists.m
On Friday, 25 March 2016 12:24:02 PM HKT you wrote:
> * whether or not we use Zynq remains to be decided.
> **The price difference is not that high (a few tens of $) and we get
> plenty of CPU power
Yes, but Zynq chips are annoying to program (even if we do not use the ARM
cores) and more propri
One can always use 2mm or 1.27mm pin headers.
1.27 are quite fragile, but 2mm should be fine and are easily available.
Greg
-Original Message-
From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov]
Sent: Tuesday, March 29, 2016 11:34 PM
To: Grzegorz Kasprowicz ; 'R
: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Slichter,
Daniel H. (Fed)
Sent: Monday, March 28, 2016 5:25 PM
To: Sébastien Bourdeauducq
Cc: Grzegorz Kasprowicz ; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project
The beauty of SMP connectors is that they
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