Re: [ARTIQ] DSP gateware

2016-08-01 Thread Leibrandt, David R. (Fed)
, 2016 5:32 AM To: artiq@lists.m-labs.hk; Jonathan Mizrahi <jmizr...@umd.edu>; Sébastien Bourdeauducq <s...@m-labs.hk>; Joe Britton <joe.britton@gmail.com>; Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov>; Leibrandt, David R. (Fed) <david.leibra...@nist.gov>

Re: [ARTIQ] proposed DAC gateware

2016-07-29 Thread Leibrandt, David R. (Fed)
Maybe this is implied, but it'd be nice to have example artiq experiments that demonstrate at least all of the functionality covered by the test cases. -Original Message- From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of j arl Sent: Thursday, July 28, 2016 3:14 PM To:

Re: [ARTIQ] FW: initial specification of the project

2016-03-30 Thread Leibrandt, David R. (Fed)
I like this plan. I think 4 + 4 channels will also make the front panel connector density more reasonable. What are you thinking for number of daughter cards? I suppose that more would give us more flexibility, but less would be more economical in terms of cost and layout area. Perhaps two